Annealing effect on dielectric and leakage current characteristics of Mn-doped Ba0.6Sr0.4TiO3 thin films as gate insulators for low voltage ZnO thin film transistor

We report on the dielectric properties and leakage current characteristics of 3 mol% Mn-doped Ba_0.6Sr_0.4TiO₃ (BST) thin films post-annealed up to 600 °C following room temperature deposition. The suitability of 3 mol% Mn-doped BST films as gate insulators for low voltage ZnO thin film transistors (TFTs) is investigated. The dielectric constant of 3 mol% Mn-doped BST films increased from 24 at in-situ deposition up to 260 at an annealing temperature of 600 °C due to increased crystallinity and the formation of perovskite phase. The measured leakage current density of 3 mol% Mn-doped BST films remained on the order of 5 × 10^− 9 to 10^− 8 A/cm² without further reduction as the annealing temperature increased, thereby demonstrating significant improvement in the leakage current characteristics of in-situ grown Mn-doped BST films as compared to that (5 × 10^− 4 A/cm² at 5 V) of pure BST films. All room temperature processed ZnO-TFTs using a 3 mol% Mn-doped BST gate insulator exhibited a field effect mobility of 1.0 cm²/Vs and low voltage device performance of less than 7 V.     

Dependence of Zr content on electrical properties of Bi3.15Nd0.85Ti3-xZrxO12 thin films synthesized by chemical solution deposition (CSD)

The Bi_3.15Nd_0.85Ti_3-xZr_xO₁₂ (BNTZ) thin films with Zr content (x = 0, 0.05, 0. 1, 0.15, and 0.2) were prepared on Pt/Ti/SiO₂/Si (100) substrates by chemical solution deposition (CSD) technique. The crystal structures of BNTZ films were analyzed by X-ray diffraction (XRD). The effects of Zr contents on the ferroelectric, dielectric properties, and leakage current of BNTZ films were thoroughly investigated. The XRD results demonstrated that all the films possessed a single phase bismuth-layered structure and exhibited the highly preferred (117) orientation. Among these films, the film with Zr content x = 0.1 held the maximum remanent polarization (2P_r) of 50.21 μC/cm² and a low coercive field (2E_c) of 210 kV/cm.     

Optimization of n nc-Si:H and a-SiNx:H layers for their application in nc-Si:H TFT

The n-type doped silicon thin films were deposited by plasma enhanced chemical vapor deposition (PECVD) technique at high and low H₂ dilutions. High H₂ dilution resulted in n⁺ nanocrystalline silicon films (n⁺ nc-Si:H) with the lower resistivity (ρ ∼0.7 Ω cm) compared to that of doped amorphous silicon films (∼900 Ω cm) grown at low H₂ dilution. The change of the lateral ρ of n⁺ nc-Si:H films was measured by reducing the film thickness via gradual reactive ion etching. The ρ values rise below a critical film thickness, indicating the presence of the disordered and less conductive incubation layer. The 45 nm thick n⁺ nc-Si:H films were deposited in the nc-Si:H thin film transistor (TFT) at different RF powers, and the optimum RF power for the lowest resistivity (∼92 Ω cm) and incubation layer was determined. On the other hand, several deposition parameters of PECVD grown amorphous silicon nitride (a-SiN_x:H) thin films were changed to optimize low leakage current through the TFT gate dielectric. Increase in NH₃/SiH₄ gas flow ratio was found to improve the insulating property and to change the optical/structural characteristics of a-SiN_x:H film. Having lowest leakage currents, two a-SiN_x:H films with NH₃/SiH₄ ratios of ∼19 and ∼28 were used as a gate dielectric in nc-Si:H TFTs. The TFT deposited with the NH₃/SiH₄∼19 ratio showed higher device performance than the TFT containing a-SiN_x:H with the NH₃/SiH₄∼28 ratio. This was correlated with the N−H/Si−H bond concentration ratio optimized for the TFT application.     

Electrical Properties and Leakage Current Mechanisms of Bi<Subscript>3.2</Subscript>Gd<Subscript>0.8</Subscript>Ti<Subscript>3</Subscript>O<Subscript>12</Subscript> Thin Films Prepared by a Sol-Gel Method

Bi_3.2Gd_0.8Ti₃O₁₂ (BGTO) thin films were deposited on Pt(111)/Ti/SiO₂/Si(100) substrates using the sol-gel method and rapid thermal annealing in an oxygen atmosphere. The effects of annealing temperature (500–800°C) on microstructure and electrical properties of thin films were investigated. X-ray diffraction analysis shows that the BGT thin films have a bismuth-layered perovskite structure with preferred (117) orientation. The intensities of (117) peaks increases with increasing annealing temperature. The leakage current density (J) was 3.69×10⁻⁸ A/cm² at 200 kV/cm. It was found that the leakage current was affected not only by the microstructure but also by the interface between the Pt electrode and BGTO thin films. In the low electric field region, the leakage current was controlled by Poole–Frenkel emission. In addition, the mechanism can be explained by Schottky emission from the Pt electrode in the high electric field region.     

Amorphous InGaZnO thin film transistors with SiO2/HfO2 double-layer gate dielectric fabricated at low temperature

Amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) with double-layer gate dielectric were fabricated at low temperature and characterized. A stacked 150 nm-thick SiO₂/50 nm-thick HfO₂ dielectric layer was employed to improve the capacitance and leakage characteristics of the gate oxide. The SiO₂/HfO₂ showed a higher capacitance of 35 nF/cm² and a lower leakage current density of 4.6 nA/cm² than 200 nm-thick SiO₂. The obtained saturation mobility (μ_sat), threshold voltage (V_th), and subthreshold swing (S) of the fabricated TFTs were 18.8 cm² V^?1 s^?1, 0.88 V, and 0.48 V/decade, respectively. Furthermore, it was found that oxygen pressure during the IGZO channel layer deposition had a great influence on the performance of the TFTs.     

Electron transport in InGaO3(ZnO)m (m=integer) studied using single-crystalline thin films and transparent MISFETs

We have investigated the characteristics of transparent metal-insulator-semiconductor field-effect transistors (MISFETs) fabricated using InGaO₃(ZnO)_m (m=integer) single-crystalline thin films as n-channel layers and amorphous alumina as gate insulator films. The MISFETs exhibit good characteristics such as insensitivity to visible light illumination, off-current as low as ∼1 nA with a positive threshold voltage of ∼3 V and on/off current ratio of 10⁵. The field-effect mobility increased from ∼1 to ∼10 cm² (V s)⁻¹ as the m-value increased. Room temperature Hall mobility also increased. However, unexpectedly these values were lower than the field-effect mobility. It is explained by existence of shallow localized state in the homologous compounds.     

Evaluation of Y2O3 gate insulators for a-IGZO thin film transistors

In this work, Y₂O₃ was evaluated as a gate insulator for thin film transistors fabricated using an amorphous InGaZnO₄ (a-IGZO) active layer. The properties of Y₂O₃ were examined as a function of various processing parameters including plasma power, chamber gas conditions, and working pressure. The leakage current density for the Y₂O₃ film prepared under the optimum conditions was observed to be ~ 3.5 × 10^− 9 A/cm² at an electric field of 1 MV/cm. The RMS roughness of the Y₂O₃ film was improved from 1.6 nm to 0.8 nm by employing an ALD (Atomic Layer Deposition) HfO₂ underlayer. Using the optimized Y₂O₃ deposition conditions, thin film transistors (TFTs) were fabricated on a glass substrate. The important TFT device parameters of the on/off current ratio, sub-threshold swing, threshold voltage, and electric field mobility were measured to be 7.0 × 10⁷, 0.18 V/dec, 1.1 V, and 3.3 cm²/Vs, respectively. The stacked insulator consisting of Y₂O₃/HfO₂ was highly effective in enhancing the device properties.     

Growth and characterization of HfO2 high-k gate dielectric films by laser molecular beam epitaxy (LMBE)

The HfO₂ gate dielectric films were fabricated by the laser molecular beam epitaxy (LMBE) technique. High-resolution transmission electron microscopy (HRTEM) observation showed that under optimized condition, there is no detectable SiO₂ interfacial layer in the as-deposited film and a SiO₂ interfacial layer of about 0.4 nm was formed at the Si interface due to the post deposition annealing. Capacitance–voltage (C–V) measurement of the film revealed that the equivalent oxide thickness was about 1.3 nm. Such a film showed very low leakage current density of 1.5 × 10⁻² A cm⁻² at 1 V gate bias from the current–voltage (I–V) analysis. The conduction mechanisms as a function of temperature T and electric field E were also systematically studied.     

Hysteresis in metal insulator semiconductor structures with high temperature annealed ZrO2/SiOx layers

Hysteresis behaviour in sandwich structure — zirconium oxide/chemical silicon oxide, annealed at temperature of 850 °C in oxygen ambient, was studied. Formation of thin ZrSi_xO_y layer due to the high temperature annealing was found. Metal-insulator-semiconductor (MIS) capacitors using ZrO₂/ZrSi_xO_y/SiO_x insulator were studied. High-frequency capacitance-voltage (HF C-V), current-voltage (I-V) and current-time (I-t) measurements were carried out on the Al/ZrO₂/ZrSi_xO_y/SiO_x/Si capacitors.Two leakage current components were identified — tunneling current component at high electric fields and transient current component at low fields. The transient leakage currents are due to charge trapping phenomena. The measured I-t characteristics are related with charging/discharging and dielectric relaxation phenomena. A counter-clockwise HF C-V hysteresis, larger than 2 V at thickness of the stack structure of about 50 nm was observed.Metal-insulator-semiconductor field effect transistors (MISFETs) using ZrO₂/ZrSi_xO_y/SiO_x-gate insulator were studied. P-channel MISFETs with aluminum gate electrode were fabricated on standard n-type silicon substrates. Due to charging/discharging phenomena in the gate dielectric the transistors can be switched between On- and Off-state with the polarity of applied stress voltage.     

Structural and optical properties of ZnO films grown on silicon and their applications in MOS devices in conjunction with ZrO<Subscript>2</Subscript> as a gate dielectric

Photoluminescence (PL) properties of undoped ZnO thin films grown by rf magnetron sputtering on silicon substrates have been investigated. ZnO/Si substrates are characterized by Rutherford backscattering (RBS), X-ray diffraction (XRD), Fourier transform infrared (FTIR), and X-ray photoelectron spectroscopy (XPS). ZrO₂ thin films have been deposited on ZnO using microwave plasma enhanced chemical vapour deposition at a low temperature (150°C). Using metal insulator semiconductor (MIS) capacitor structures, the reliability and the leakage current characteristics of ZrO₂ films have been studied both at room and high temperatures. Schottky conduction mechanism is found to dominate the current conduction at a high temperature. Good electrical and reliability properties suggest the suitability of deposited ZrO₂ thin films as an alternative as gate dielectric on ZnO/n-Si heterostructure for future device applications.     

Effect of oxygen to argon ratio on the properties of thin SiO<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript> films deposited by r.f. sputtering

Energy Dispersive X-ray and X-ray Photoelectron (XPS) spectroscopies show that SiO _x films deposited by reactive r.f. magnetron sputtering at partial pressure ratios R between oxygen and argon in a wide range (1–0.005) have compositions close to the stoichiometric one. For these films high temperature annealing at 1,000 °C shifts the band in the Fourier Transform-Infrared spectrum due to the Si–O–Si stretching vibration to values typical of stoichiometric SiO₂. Further decrease of R leads to splitting of the Si 2p XPS line indicating increase of the Si content and formation of a second phase in a SiO₂ matrix. The electrical properties of test MOS structures with SiO _x gate dielectric, regarding defect density in the oxide and at the SiO _x /c-Si interface, degrade with the decrease of R. High temperature annealing at 1,000 °C strongly improves the properties of all films regarding leakage current and properties of the interface.     

Microstructure and electrical properties of Al2O3-ZrO2 composite films for gate dielectric applications

Al₂O₃-ZrO₂ composite films were fabricated on Si by ultrahigh vacuum electron-beam coevaporation. The crystallization temperature, surface morphology, structural characteristics and electrical properties of the annealed films are investigated. Our results indicate that the amorphous and mixed structure is maintained up to an annealing temperature of 900 °C, which is much higher than that of pure ZrO₂ film, and the interfacial oxide layer thickness does not increase after annealing at 900 °C. However, a portion of the Al₂O₃-ZrO₂ film becomes polycrystalline after 1000 °C annealing and interfacial broadening is observed. Possible explanations are given to explain our observations. A dielectric constant of 20.1 is calculated from the 900 °C-annealed ZrO₂-Al₂O₃ film based on high-frequency capacitance-voltage measurements. This dielectric characteristic shows an equivalent oxide thickness (EOT) as low as 1.94 nm. An extremely low leakage current density of ∼2×10⁻⁷ A/cm² at a gate voltage of 1 V and low interface state density are also observed in the dielectric film.     

Thermal treatment effects on interfacial layer formation between ZrO2 thin films and Si substrates

This paper describes the growth condition of stoichiometric ZrO₂ thin films on Si substrates and the interfacial structure of ZrO₂ and Si substrates. The ZrO₂ thin films were prepared by rf-magnetron sputtering from Zr target with mixed gas of O₂ and Ar at room temperature followed by post-annealing in O₂ ambient. The stoichiometric ZrO₂ thin films with smooth surface were grown at high oxygen partial pressure. The thick Zr-free SiO₂ layer was formed with both Zr silicide and Zr silicate at the interface between ZrO₂ and Si substrate during the post-annealing process due to rapid diffusion of oxygen atoms through the ZrO₂ thin films. After post annealing at 650-750 °C, the multi-interfacial layer shows small leakage current of less than 10⁻⁸ A/cm² that is corresponding to the high-temperature processed thermal oxidized SiO₂.     

Fabrication and electrical properties of metal-oxide semiconductor capacitors based on polycrystalline p-CuxO and HfO2/SiO2 high-κ stack gate dielectrics

Polycrystalline p-type Cu_xO films were deposited after the growth of HfO₂ dielectric on Si substrate by pulsed laser deposition, and Cu_xO metal-oxide-semiconductor (MOS) capacitors with HfO₂/SiO₂ stack gate dielectric were primarily fabricated and investigated. X-ray diffraction and X-ray photoelectron spectroscopy were applied to analyze crystalline structure and Cu⁺/Cu²⁺ ratios of Cu_xO films respectively. SiO₂ interlayer formed between the high-κ dielectric and substrate was estimated by the transmission electron microscope. Results of electrical characteristic measurement indicate that the permittivity of HfO₂ is about 22, and the gate leakage current density of MOS capacitor with 11.3 nm HfO₂/SiO₂ stack dielectrics is ∼ 10⁻⁴ A/cm². Results also show that the annealing in N₂ can improve the quality of Cu_xO/HfO₂ interface and thus reduce the gate leakage density.     

CdS nanoparticles incorporated onion-like mesoporous silica films: Ageing-induced large stokes shifted intense PL emission

CdS nanoparticles (NPs) were generated in onion-like ordered mesoporous SiO₂ films through a modified sol–gel process using P123 as a structure directing agent. Initially Cd²⁺ doped (12 equivalent mol% with respect to the SiO₂) mesoporous SiO₂ films were prepared on glass substrate. These films after heat-treatment at 350 °C in air yielded transparent mesoporous SiO₂ films having hexagonally ordered onion-like pore channels embedded with uniformly dispersed CdO NPs. The generated CdO NPs were transformed into CdS NPs after exposing the films in H₂S gas at 200 °C for 2 h. The as-prepared CdS NPs incorporated mesoporous SiO₂ films (transparent and bright yellow in color) showed a band-edge emission at 485 nm and a weak surface defect related emission at 530 nm. During ageing of the films in ambient condition the band-edge emission gradually weakened with time and almost disappeared after about 15 days with concomitant increase of defect related strong surface state emission band near 615 nm. This transformation was related to the decay of initially formed well crystalline CdS to relatively smaller and weakly crystalline CdS NPs with surface defects due to gradual oxidation of surface sulfide. At this condition the embedded CdS NPs show large Stokes shifted (∼180 nm) intense broad emission which could be useful for luminescent solar concentrators. The detailed process was monitored by UV–Visible, FTIR and Raman spectroscopy, XPS, XRD and TEM studies. The evolution of photoluminescence (PL) and life times of CdS/SiO₂ films were monitored with respect to the ageing time.     

Low voltage ZnO thin-film transistors with Ti-substituted BZN gate insulator for flexible electronics

We report the fabrication of ZnO based thin-film transistors (TFTs) with high-k gate insulator of Ti-substituted Bi_1.5ZnNb_1.5O₇ (BZN) films. (Bi_1.5Zn_0.5)(Zn_0.4Nb_1.43Ti_0.3O₇) film deposited on Pt/Ti/SiO₂/Si substrate by pulsed laser deposition at room temperature exhibits high dielectric constant of 73 at 100 kHz, while BZN film shows much lower dielectric constant of 50, respectively. The increasing dielectric constant with increasing Ti substitution can be attributed to the presence of a highly polarizable TiO₆ octahedra and its strong correlation with the NbO₆ octahedra. All room temperature processed ZnO based TFTs using Ti-substituted BZN gate insulator exhibited filed effect mobility of 0.75 cm²/Vs and low voltage device performance less than 2.5 V.     

Effect of oxygen pressure of SiOx buffer layer on the electrical properties of GZO film deposited on PET substrate

The present work was made to investigate the effect of oxygen pressure of SiO_x layer on the electrical properties of Ga-doped ZnO (GZO) films deposited on poly-ethylene telephthalate (PET) substrate by utilizing the pulsed-laser deposition at ambient temperature. For this purpose, the SiO_x buffer layers were deposited at various oxygen pressures ranging from 13.3 to 46.7 Pa. With increasing oxygen pressure during the deposition of SiO_x layer as a buffer, the electrical resistivity of GZO/SiO_x/PET films gradually decreased from 7.6 × 10^− 3 to 6.8 × 10^− 4 Ω·cm, due to the enhanced mobility of GZO films. It was mainly due to the grain size of GZO films related to the roughened surface of the SiO_x buffer layers. In addition, the average optical transmittance of GZO/SiO_x/PET films in a visible regime was estimated to be ~ 90% comparable to that of GZO deposited onto a glass substrate.     

Effect of N2O plasma treatment on the improvement of instability under light illumination for InGaZnO thin-film transistors

This paper investigates the impact of N₂O plasma treatment on the light-induced instability of InGaZnO thin film transistors with a SiO₂ passivation layer deposited by plasma-enhanced-chemical-vapor-deposition (PECVD). For the untreated device, because the deposition of the SiO₂ passivation layer by PECVD causes extra trap states, the anomalous subthreshold leakage current can be attributed to a lowering of the source side barrier due to trap-assisted photogenerated holes. In contrast, the N₂O plasma treatment applied to both the gate insulator and the active layer effectively suppresses the device instability under illumination. In order to clarify the influence of the N₂O plasma treatment, this study investigates a device with treatment of only the gate insulator. This device shows a slight decrease of light-induced subthreshold leakage current. This demonstrates that N₂O plasma treatment on IGZO active layer after its deposition is critical in preventing damage from the subsequent SiO₂ passivation deposition process. In addition, the instability of threshold voltage (V_T) under negative bias illumination stress (NBIS) is significantly improved by the N₂O plasma treatment. Furthermore, a different dark recovery rate follows NBIS for untreated and N₂O plasma-treated devices, indicating different hole-trapping levels exist in the energy band.     

Electrical properties of alumina films grown on Si at low temperature using catalytic CVD

The electrical properties of alumina films formed at substrate temperatures as low as 27 °C using tri-methyl aluminum (TMA) and molecular oxygen (O₂) by catalytic chemical vapor deposition (Cat-CVD) have been investigated by capacitance-voltage (C-V), current-voltage (I-V) measurements and X-ray photoelectron spectroscopy (XPS). Substrate temperature dependence of dielectric constant and leakage current of the films has been explained on the basis of deficiency in oxygen. Interface trapping density of the order of 10⁹ ev^− 1cm^− 2 has been obtained. Angle resolved XPS measurements have revealed that the direct bonding of alumina and Si was realized with very small interface trapping density.     

Rutile-type TiO2 thin film for high-k gate insulator

We investigated rutile-type titanium dioxide (TiO₂) films for possible use as a high-k gate insulator. The TiO₂ thin films were directly deposited on Si substrates using a RF magnetron sputtering method with a sintered oxide target. A single phase of rutile-type TiO₂ whose dielectric constant of approximately 75 was obtained when the film was deposited in an inert gas atmosphere and annealed at 800 °C in an oxidizing gas atmosphere. The oxygen ions were deficient in the as-deposited film, and consequently, a sufficient oxygen supply was needed to crystallize the film to a single phase of rutile during the post-annealing. However, the interfacial SiO₂ layer between the TiO₂ and the Si substrate simultaneously grew thicker than 2 nm. As the interfacial SiO₂ grew, the leakage current was decreased and the equivalent oxide thickness was increased, in the Au/rutile-type TiO₂/Si capacitor. Therefore, we concluded that the growth of the interfacial SiO₂ layer thicker than 2 nm is inevitable to form the single phase of rutile-type TiO₂ and to decrease the leakage.