Interface reactions at TiN/HfSiON gate stacks: Dependence on the electrode structure and deposition method

We systematically investigated intrinsic and extrinsic thermal reactions at TiN/HfSiON gate stacks. The formation of an ultrathin TiO₂ interlayer was found to be an intrinsic reaction at the metal/insulator interface, but growth of SiO₂ underlayers between HfSiON and Si substrates, which determines the electrical thickness of metal-oxide-semiconductor (MOS) devices, depends on the structure and deposition method of the gate electrodes. Physical vapor deposition (PVD) grown TiN electrodes covered with W overlayers exhibited excellent thermal stability at up to 1000 °C. Formation of ultrathin TiO₂ interlayers reduced gate leakage current (I_g), and growth of the oxide underlayer was suppressed by less than a few angstroms even for 1000 °C annealing. In contrast, we found that halogen impurities within CVD-grown metal electrodes enhance interface SiO₂ growth, resulting in deterioration of equivalent oxide thickness (EOT) versus I_g characteristics of the gate stacks.     

Interfacial reaction and electrical properties of HfO2 film gate dielectric prepared by pulsed laser deposition in nitrogen: role of rapid thermal annealing and gate electrode

The high-k dielectric HfO(2) thin films were deposited by pulsed laser deposition in nitrogen atmosphere. Rapid thermal annealing effect on film surface roughness, structure and electrical properties of HfO(2) film was investigated. The mechanism of interfacial reaction and the annealing atmosphere effect on the interfacial layer thickness were discussed. The sample annealed in nitrogen shows an amorphous dominated structure and the lowest leakage current density. Capacitors with high-k HfO(2) film as gate dielectric were fabricated, using Pt, Au, and Ti as the top gate electrode whereas Pt constitutes the bottom side electrode. At the gate injection case, the Pt- and Au-gated metal oxide semiconductor devices present a lower leakage current than that of the Ti-gated device, as well as similar leakage current conduction mechanism and interfacial properties at the metal/HfO(2) interface, because of their close work function and chemical properties.     

Effects of growth temperature and film thickness on the electrical properties of Ba0.7Sr0.3TiO3 thin films grown on platinized silicon substrates by pulsed laser deposition

Barium strontium titanate Ba_0.7Sr_0.3TiO₃ (BST) thin films, with different growth temperatures (T_g) as well as different film thicknesses, have been prepared on Pt/Ti/SiO₂/Si substrates by a reactive pulsed laser deposition method. We observed strong dependences of dielectric properties, such as the Curie-Weiss temperature, dielectric constant, loss tangent, dielectric tunability and leakage current, on the T_g and the BST film thickness. With increase of T_g from 630 to 750 °C, the dielectric constant gradually increases due to the increase in the crystallinity and the grain size. However, the dielectric tunability, loss tangent and leakage current characteristics drastically degrade when the T_g increases up to 750 °C, due to the diffuse and rough interface. The BST film grown at 690 °C shows the best overall dielectric properties with a figure-of-merit of 33 (at 400 kV/cm). These results suggest that film growth process could be optimized by systematically investigating the structure-property relationships. Furthermore, as the BST film thickness increases from 250 to 560 nm, the dielectric properties are remarkably enhanced. The film thickness effect is attributed to the interfacial low-dielectric layers (the so-called “dead layer”) between the BST film and both metal electrodes, which is well explained in terms of a series capacitor model. The thickness and the average dielectric constant for the dead layer are experimentally estimated to be 1.9 nm and 20.3, respectively, in Pt/BST/Pt capacitors.     

HfO2 gate insulator formed by atomic layer deposition for thin-film-transistors

We have investigated the effects of annealing temperature on the physical and electrical properties of the HfO₂ film deposited by an atomic layer deposition (ALD) method for high-k gate oxides in thin-film-transistors (TFTs). The ALD deposition of HfO₂ directly on the Si substrate at 300 °C results in the formation of thin HfSi_xO_y interfacial layer between Si and HfO₂. The subsequent low temperature N₂-annealing of HfO₂ films (i.e., 300 °C) using a rapid thermal processor (RTP) improves the overall electrical characteristics of HfSi_xO_y-HfO₂ films. Based on the current work, we suggest that HfO₂ film deposited by the ALD method is suitable for high-k gate oxides in TFTs, which have to be fabricated at low temperature.     

Thermal stability of advanced gate stacks consisting of a Ru electrode and Hf-based gate dielectrics for CMOS technology

Metallic Ru and Hf-based dielectrics such as HfO₂, HfSiO_x and HfSiON, are promising materials for the gate electrode and gate dielectrics, respectively. This paper reports on the thermal stability of gate stack systems comprised of Ru/Hf-based dielectrics. Layers of both types of material were prepared on Si substrate by metal-organic chemical vapour deposition (MOCVD). The stacks underwent exposure by rapid thermal annealing (RTA) in pure nitrogen ambience at temperatures 800, 900, and 1000 °C for 10 s. The samples were analysed using Rutherford backscattering spectrometry (RBS). Small changes were found in the stacks treated at 800 and 900 °C. The most stable stack was found to be one with a HfSiON dielectric layer, which was resistant also at temperature 900 °C. However, the annealing at 1000 °C induced massive diffusion at both interfaces for all types of stack. The results imply a limited thermal stability of the Ru/Hf-based dielectric gate stacks during the source/drain activation step.     

Growth characteristics and electrical properties of La2O3 gate oxides grown by thermal and plasma-enhanced atomic layer deposition

We comparatively investigated thermal and plasma-enhanced atomic layer deposition (T-ALD and PE-ALD, respectively) of lanthanium oxide (La₂O₃) films using tris(isopropyl-cyclopentadienyl)lanthanum [La(iPrCp)₃] as a La precursor. H₂O and O₂ plasma were used as reactants for T-ALD and PE-ALD La₂O₃, respectively. Both of the processes exhibited ALD mode growth with good self-saturation behavior and produced pure La₂O₃ films. However, PE-ALD La₂O₃ showed higher growth rate and dielectric constant value than those of T-ALD La₂O₃. In addition, lower leakage current density and interface state density were observed for PE-ALD La₂O₃, compared to those of the T-ALD La₂O₃. These experimental results indicate that the PE-ALD La₂O₃ process using La(iPrCp)₃ precursor can be one of the viable options applicable into future microelectronic industry.     

Fabricating gate insulator by low temperature solution-based process

Solution-processed gate insulator was fabricated using polymethylphenylsilane (PMPS) as a liquid precursor. The spin-coated PMPS films were transformed into SiO₂ films after exposing to ultraviolet (UV) with 365 nm of wavelength. Fourier transform infrared spectra showed the variations of photo oxidation according to UV exposing time. The peak intensity of Si-O-Si bond increases with the UV energy, while the intensities of the methyl and phenyl peaks decrease. The electrical characteristics of PMPS-based spin-on glass (PMPS-SOG) were analyzed by capacitance-voltage and leakage current measurements. The dielectric constant was 4.14 and leakage current density was 10^− 7 A/cm². The low temperature below 200 °C fabrication processing of PMPS-SOG could be achieved by UV exposing. PMPS-SOG, forming SiO₂, is applicable to gate insulator by low temperature solution-based process.     

Microstructure and electrical properties of Al2O3-ZrO2 composite films for gate dielectric applications

Al₂O₃-ZrO₂ composite films were fabricated on Si by ultrahigh vacuum electron-beam coevaporation. The crystallization temperature, surface morphology, structural characteristics and electrical properties of the annealed films are investigated. Our results indicate that the amorphous and mixed structure is maintained up to an annealing temperature of 900 °C, which is much higher than that of pure ZrO₂ film, and the interfacial oxide layer thickness does not increase after annealing at 900 °C. However, a portion of the Al₂O₃-ZrO₂ film becomes polycrystalline after 1000 °C annealing and interfacial broadening is observed. Possible explanations are given to explain our observations. A dielectric constant of 20.1 is calculated from the 900 °C-annealed ZrO₂-Al₂O₃ film based on high-frequency capacitance-voltage measurements. This dielectric characteristic shows an equivalent oxide thickness (EOT) as low as 1.94 nm. An extremely low leakage current density of ∼2×10⁻⁷ A/cm² at a gate voltage of 1 V and low interface state density are also observed in the dielectric film.     

Study of reactive sputtering titanium oxide for metal-oxide-semiconductor capacitors

Metal oxide semiconductor (MOS) capacitors with titanium oxide (TiO_x) dielectric layer, deposited with different oxygen partial pressure (30, 35 and 40%) and annealed at 550, 750 and 1000 °C, were fabricated and characterized.Capacitance-voltage and current-voltage measurements were utilized to obtain, the effective dielectric constant, effective oxide thickness, leakage current density and interface quality. The obtained TiO_x films present a dielectric constant varying from 40 to 170 and a leakage current density, for a gate voltage of − 1 V, as low as 1 nA/cm² for some of the structures, acceptable for MOS fabrication, indicating that this material is a viable high dielectric constant substitute for current ultra thin dielectric layers.     

Integrations and challenges of novel high-k gate stacks in advanced CMOS technology

Due to the limitations in conventional complementary metal-oxide-semiconductor (CMOS) scaling technology in recent years, innovation in transistor structures and integration of novel materials has been a key to enhancing the performance of CMOS field-effect transistors (FETs) of past technology generations. Tremendous progress of high dielectric constant (high-k) gate stacks has been made in recent years and some of them have come into application in CMOS devices. However, many challenges remain, such as: (a) suitable permittivity, band gap and band alignment for dielectrics, on Si, (b) thermodynamic stability and interface engineering at both high-k/Si interface and metal/metal interface, (c) depletion effect, high gate resistance and its incompatibility with high-k for metal gate, and (d) low performance attributed to threshold voltage instability. Based on current progress and fundamental considerations, we review the current status and challenges in novel high-k dielectrics and metal gates research for planar CMOS devices and alternative device technologies to provide insights for future research. Finally, this review concludes with perspectives towards the future gate stack technology and challenges in advanced CMOS devices.     

Atomic-layer-deposited (ALD) Al_2O_3passivation dependent interface chemistry,band alignment and electrical properties of HfYO/Si gate stacks

In this work, the effects of atomic-layer-deposited(ALD) Al_2O_3 passivation layers with different thicknesses on the interface chemistry and electrical properties of sputtering-derived HfYO gate dielectrics on Si substrates have been investigated. The results of electrical measurements and X-ray photoelectron sepectroscopy(XPS) showed that 1-nm-thick Al_2O_3 passivation layer is optimized to obtain excellent electrical and interfacial properties for HfYO/Si gate stack. Then, the metal-oxide-semiconductor capacitors with HfYO/1-nm Al_2O_3/Si/Al gate stack were fabricated and annealed at different temperatures in forming gas(95% N_2+5% H_2). Capacitance-voltage(C-V) and current density-voltage(J-V) characteristics showed that the 250℃-annealed HYO high-k gate dielectric thin film demonstrated the lowest border trapped oxide charge density(-3.3 × 10~(10) cm~(-2)), smallest gate-leakage current(2.45 × 10~(-6) A/cm~2 at 2 V)compared with other samples. Moreover, the annealing temperature dependent leakage current conduction mechanism for Al/HfYO/Al_2O_3/Si/Al MOS capacitor has been investigated systematically. Detailed electrical measurements reveal that Poole-Frenkle emission is the main dominant emission in the region of low and medium electric fields while direct tunneling is dominant conduction mechanism at high electric fields.     

Temperature dependence of the work function of ruthenium-based gate electrodes

The effect of device fabrication temperature on the work function of ruthenium (Ru) metal gate and its bilayers was investigated. The work function shows strong temperature dependence when Ru electrodes are deposited on silicon oxide, SiO₂, but not on hafnium silicates (HfSiO_x). Specifically, the work function of Ru on SiO₂ increased from 4.5 eV at 500 °C to 5.0 eV at 700 °C. On further annealing to 900 °C or higher, the work function dropped to about 4.4 eV. In the case of HfSiO_x, the work function of Ru changed by less than 100 mV over the same temperature range. Identical temperature dependence was observed using hafnium (Hf)/Ru and tantalum (Ta)/Ru bilayers. However, the peak values of the work function decreased with increasing Hf/Ru and Ta/Ru thickness ratios. Materials analysis suggests that these trends are driven by interactions at the Ru metal gate-dielectric interface.     

Oligo- and polymeric FET devices: Thiophene-based active materials and their interaction with different gate dielectrics

Derivatives of both oligo- and polythiophene-based FET were recently considered for low cost electronic applications. In the device optimization, factors like redox reversibility of the molecule/polymer, electronic level compatibility with source/drain electrodes, packing closeness, and orientation versus the electrodes, can determine the overall performance. In addition, a gate insulator with a high dielectric constant, a low leakage current, and capability to promote ordering in the semiconductor is required to increase device performances and to lower the FET operating voltage. In this view, Al₂O₃ appears a good candidate, although its widespread adoption is limited by the disorder that such oxide induces on the semiconductor with detrimental consequences on semiconductor electrical properties.In this contribution, an overview of recent results obtained on thiophene-derivative-based FET devices, fabricated by different growth techniques, and using both thermally grown SiO₂ and Al₂O₃ from atomic layer deposition gate insulators will be reported and discussed with particular reference to organic solid state aggregation, morphology, and organic–inorganic interface.     

Low voltage ZnO thin-film transistors with Ti-substituted BZN gate insulator for flexible electronics

We report the fabrication of ZnO based thin-film transistors (TFTs) with high-k gate insulator of Ti-substituted Bi_1.5ZnNb_1.5O₇ (BZN) films. (Bi_1.5Zn_0.5)(Zn_0.4Nb_1.43Ti_0.3O₇) film deposited on Pt/Ti/SiO₂/Si substrate by pulsed laser deposition at room temperature exhibits high dielectric constant of 73 at 100 kHz, while BZN film shows much lower dielectric constant of 50, respectively. The increasing dielectric constant with increasing Ti substitution can be attributed to the presence of a highly polarizable TiO₆ octahedra and its strong correlation with the NbO₆ octahedra. All room temperature processed ZnO based TFTs using Ti-substituted BZN gate insulator exhibited filed effect mobility of 0.75 cm²/Vs and low voltage device performance less than 2.5 V.     

Electrical properties of pulsed laser deposited Bi<Subscript>2</Subscript>Zn<Subscript>2/3</Subscript>Nb<Subscript>4/3</Subscript>O<Subscript>7</Subscript> thin films for high K gate dielectric application

Metal Insulator Semiconductor (MIS) capacitors with monoclinic bismuth zinc niobate pyrocholre having the composition Bi2Zn2_/3Nb_4/3O₇ (m-BZN) dielectric layer were fabricated and characterized. Capacitance voltage (C–V) and current voltage measurements were utilized to obtain the dielectric properties, leakage current density and interface quality. The results shows that the obtained m-BZN thin films presents a high dielectric constant in between 30 and 70, a good interface quality with silicon and a leakage current density of 10 μA/cm² for a field strength of 100 kV/cm which is acceptable for high performance logic circuits. The equilent oxide thickness for the films annealed at 200 °C was 10 nm. These results suggest that m-BZN thin films can be potentially integrated as gate dielectric materials in CMOS technology.     

Perspectives paper: First principles modeling of high-k gate dielectrics

Aggressive scaling has led to silicon dioxide (SiO₂) gate dielectrics as thin as 15 Å in state-of-the-art CMOS technologies. As a consequence, static leakage power due to direct tunneling through the gate oxide has been increasing at an exponential rate. As technology roadmaps call for sub-10 Å gate oxides within the next five years, a variety of alternative high-k materials are being investigated as possible replacements for SiO₂. The higher dielectric constants in these materials allow the use of physically thicker films, potentially reducing the tunneling current while maintaining the gate capacitance needed for scaled device operation. Recognizing that the current Si/SiO₂ system benefits from nearly 30 years of research, developing a replacement material for SiO₂ presents an immense challenge. This has prompted recent interest in novel computational approaches, such as first principles density functional theory (DFT) simulations, to computationally screen candidate dielectrics by predicting their properties based on the microscopic interactions within the system. This paper provides perspectives on the application of DFT simulations to address challenging problems of high-k gate dielectric research. We provide background and motivation for the development of high-k materials and highlight opportunities for theoretical study of such materials. We also describe specific examples of recent first principles work related to two particularly promising materials systems: silicates and aluminates.     

Structural and optical properties of ZnO films grown on silicon and their applications in MOS devices in conjunction with ZrO<Subscript>2</Subscript> as a gate dielectric

Photoluminescence (PL) properties of undoped ZnO thin films grown by rf magnetron sputtering on silicon substrates have been investigated. ZnO/Si substrates are characterized by Rutherford backscattering (RBS), X-ray diffraction (XRD), Fourier transform infrared (FTIR), and X-ray photoelectron spectroscopy (XPS). ZrO₂ thin films have been deposited on ZnO using microwave plasma enhanced chemical vapour deposition at a low temperature (150°C). Using metal insulator semiconductor (MIS) capacitor structures, the reliability and the leakage current characteristics of ZrO₂ films have been studied both at room and high temperatures. Schottky conduction mechanism is found to dominate the current conduction at a high temperature. Good electrical and reliability properties suggest the suitability of deposited ZrO₂ thin films as an alternative as gate dielectric on ZnO/n-Si heterostructure for future device applications.     

Structural, optical and electrical properties of high-k ZrO2 dielectrics on Si prepared by plasma assisted pulsed laser deposition

ZrO₂ films were grown on p-type Si(100) using plasma assisted pulsed laser deposition and the electrical characteristics of the ZrO₂ dielectrics incorporated in metal oxide silicon (MOS) capacitors were studied in combination with their structural and optical properties. The ZrO₂ dielectric layers are of polycrystalline structure with a monoclinic phase and show good interfacial properties without obvious SiO_x interface. The electrical performance of the capacitors exhibits typical MOS-type capacitance-voltage (C-V) and leakage current density-voltage (J-V) characteristics. Thermal annealing of the ZrO₂ dielectrics results in an improvement in C-V and J-V characteristics and a reduction in C-V hysteresis without obvious introduction of leakage paths for the fabricated MOS capacitors. The dielectric constant was calculated to be 15.4 and the leakage current density was measured to be 6.7 × 10^− 6 A/cm² at a gate voltage of + 1.0 V for 900 °C annealed ZrO₂ dielectric layers with an equivalent oxide thickness of 5.2 nm.     

Tunneling currents through ultra thin HfO2/Al2O3/HfO2 triple layer gate dielectrics for advanced MIS devices

The dramatic scaling down of silicon integrated circuits has led to an intensive study of high dielectric constant materials as an alternative to the conventional insulators currently employed in microelectronics, i.e., silicon dioxide, silicon nitride, or oxynitride, which seem to have reached their physical limit in terms of reduction of thickness due to large leakage gate current. Introducing a physically thicker high-K material can reduce the leakage current to the acceptable limit. There are many potential candidates for high-K gate dielectrics with the K-valves ranging from 9 to 80. These are Al₂O₃, Y₂O₃, La₂O₃, Ta₂O₅, TiO₂, ZrO₂ and HfO₂. It is important to study the various leakage mechanisms in these films with the aim of improving their leakage current characteristics for use in advanced microelectronics devices. A procedure for calculating the tunneling current for stacked dielectrics is developed and subsequently applied to ultra thin films with equivalent oxide thickness (EOT) of 3.0 nm. Tunneling currents have been calculated as a function of gate voltage for different structures. Direct and Fowler-Nordheim tunneling currents through triple layer dielectrics are investigated for substrate injection. Using exact tunneling transmission calculations, current density–gate voltage (J _g?V _g) characteristics for ultra thin single layer gate dielectrics with different thicknesses have been shown to agree well with recently reported experiments. Extensions of this approach demonstrate that tunneling currents in HfO₂/Al₂O₃/HfO₂ structure with equivalent oxide thickness of 3.0 nm can be significantly lower than that through single layer oxides of the same thickness.     

Evaluation of Y2O3 gate insulators for a-IGZO thin film transistors

In this work, Y₂O₃ was evaluated as a gate insulator for thin film transistors fabricated using an amorphous InGaZnO₄ (a-IGZO) active layer. The properties of Y₂O₃ were examined as a function of various processing parameters including plasma power, chamber gas conditions, and working pressure. The leakage current density for the Y₂O₃ film prepared under the optimum conditions was observed to be ~ 3.5 × 10^− 9 A/cm² at an electric field of 1 MV/cm. The RMS roughness of the Y₂O₃ film was improved from 1.6 nm to 0.8 nm by employing an ALD (Atomic Layer Deposition) HfO₂ underlayer. Using the optimized Y₂O₃ deposition conditions, thin film transistors (TFTs) were fabricated on a glass substrate. The important TFT device parameters of the on/off current ratio, sub-threshold swing, threshold voltage, and electric field mobility were measured to be 7.0 × 10⁷, 0.18 V/dec, 1.1 V, and 3.3 cm²/Vs, respectively. The stacked insulator consisting of Y₂O₃/HfO₂ was highly effective in enhancing the device properties.