结构件质量对直通率的影响与保证（待续）

以实现整机直通率为出发点，分析结构件对直通率的影响，提出按直通率目标值对主要结构件进行不良率的分配，并依据结构件的平均质量（过程平均）来确定逐批和交收检查的合格质量水平和检查水平。     

加强工艺管理,提高彩电基板质量

衡量彩色电视机生产质量水平的重要指标是装配直通率(又称之工程良品率)。装配直通率取决于产品的设计质量、元器件上机良品率、生产线的技术状态、生产工艺、操作人员的技术熟练程度和企业的管理水平等方面。我国目前所生产的各种型号的彩     

SMT印制电路板设计常见问题及解决方法

印制电路板的布线设计是否符合SMT工艺技术和工艺设备的要求,对印制板组件装联质量的直通率有着直接的非常重要的影响。PCB布线设计满足制造要求是保证表面组装质量的关键要素之一。对SMT印制电路板设计中的常见问题进行了举例说明并给出了正确的解决方法,同时给出了消除不良设计和实现可制造性设计的8项措施。     

邑子组装中焊接设备工艺调试步骤与技巧

再流焊接技术和波峰焊接技术是目前电子组装中两大关键技术。其参数设定及工艺调整的优劣直接影响到产品焊接质量及生产直通率。针对目前焊接技术工艺特点,结合实际生产经验,对其调试步骤及技巧给予了指导性论述,并总结了实操过程中一些关键技术及要点。     

如何有效控制湿度敏感器件

湿度敏感器件(MSD)对SMT生产直通率和产品的可靠性的影响不亚于ESD，所以认识MSD的重要性，深入了解MSD的损害机理，学习相关标准，通过规范化MSD的过程控制方法，避免由于吸湿造成在回流焊接过程中的元器件损坏来降低由此造成的产品不良率，提高产品的可靠性是SMT不可推脱的责任。     

无线数字机顶盒的常见故障及其维修方法

实际生产中由于机器性能、操作方法和物料性能方面的问题不可能做到百分百的直通率,总是会出现这样或者那样的问题,本文就以机顶盒的常见故障分类介绍其维修方法。1机顶盒的测试流程在拿到一台坏机以后,首先要对它进行全面的检查,而不只是看它出问题的那个地方,因为它可能是几个地方同时出问题。     

大力发展面向世界工厂的职业教育和培训第一届“电子制造可靠性工程”培训讲座

对电子制造工程师而言，最关心无外乎两件事：一是直通率问题；二是产品的长期可靠性问题。本次讲座针对电子产品的可靠性问题，系统阐述可靠性的基础理论、主要失效形式、失效机理、可靠性设计（DFR）以及备受关注的无铅导入后的无铅可靠性问题。     

技术释疑——为您解决生产技术疑难

问题1：手机组装中常见的工艺问题有哪些,其产生的主要原因是什么？ 解答：手机板由于生产批量大及元件工艺兼容性比较好,就整个业界看,直通率都比较高,平均来说一般超过99％。焊接问题总的来说不多,主要集中在PCB、屏蔽框、连接器、EMI器件上。     

微机电系统（MEMS）器件的自动化封装

在过去的十年中，MEMS已经迅速发展到许多商业产品的重要位置。这些芯片级的器件在汽车，宇航，生物医学，国防和许多其它工业方面的新用途，每天都有新发现。将来随着MEMS器件的广泛应用，无可质疑，它们的需求量也会变大，同时也需要有能够进行大批量、高直通率的生产方法。自动化是解决这个问题的措施。在不久以前，MEMS的低产量和高复杂性，使得MEMS器件封装厂家不甚考虑其工艺自动化。结果，许多MEMS器件生产在设计元件时，都不考虑自动化问题。采用可自动化组装的设计(DFA)(以下简称为自动化设计)会确保将来在再设计时节省成本。自动化设计MEMS器件意味着，要确保它们拥有精确的物理特性和更精确的制造精度，以适应自动装配工艺所需。一般来说，自动组装设备只能贴放符合它所需精密度的元件。例如：在电信业中阵列开关中使用光学MEMS器件。此MEMS必须精确放置。其精度沿X、Y和Z轴为5微米，绕0轴为两个微弧度。这种和其他相似的应用都要求元件具有很高的质量。在对ⅧMS产品预测中，显示需求量增长。很明显，对于大批量、高直通率的制造，其解决途径之一是自动化设计MEMS元件。设计必须为了适应大批量生产，设计他们的MEMS元件。如上所述，这个过程需要细心和勤奋，带给顾客的价格降低和带给生产产量和直通率增加，将使双方受益。     

浅析SMT回流焊接缺陷分析

表面组装技术（SMT）的应用是电子装联时代的一场革命,随着电子装联的小型化、高密度化的发展．随着无铅焊接工艺的应用,回流焊接的工艺方法受到了越来越多的挑战。要完成高质量和高直通率的电子产品,对焊接缺陷必须具备较强的诊断和分析能力,找出产生缺陷的相关因素,改善工艺过程．找出最好的办法有效地控制缺陷率。最大化提高产品的品质,最大化降低返工或返修造成的成本是SMT业者一个永远追求的目标。本篇论文着重讨论部分回流焊接缺陷,给大家一个针对相关缺陷分析的思路和方法。     

关于缺陷密度DO的研究

在半导体图片制造过程中，提高成品率是我们一直追求的目标。本文从成品率失效模式入手，介绍一种评价半导体生产线的新方法：缺陷密度DO，从而对工艺水平的评价提供一个较为客观的依据。本文从DO／Yield模型的建立，基本计算公式介绍，DO／Yield模型的计算机程序开发，以及DO／Yield模型的实际应用等几个方面加以阐述。     

Yield sensitivity of HEMT circuits to process parameter variations

The authors summarize the use of a graphical tool, yield factor histograms, to study the yield sensitivity of HEMT circuits to process parameter variations. A computer program called SPICENTER is used to incorporate the HEMT statistical physical model with a SPICE circuit model and then to generate the yield factor histograms and yield sensitivities as functions of the process parameters. The authors present the application of these tools to digital and microwave circuits. Two example HEMT circuits, a two-input NOR gate and an inverter chain, illustrate the concepts. Yield sensitivity is presented as yield percent change per parameter percent change     

The application of submicron lithography defect simulation to ICyield improvement

Yield improvement efforts traditionally involve extensive experimental work aimed at diagnosis of defect sources. This paper proposes a methodology for supplementing such experimental work with defect simulation. In particular, it is shown that lithography defect simulation can provide insight into defect mechanisms that cause major distortions in photoresist profiles. The nature of the distorted patterns can assist us in yield improvement efforts, since by comparing simulation results with the observed photoresist profiles on wafers, defect sources may be identified. Several lithography defect diagnosis examples are presented to demonstrate the approach     

Hierarchical mapping of spot defects to catastrophic faults-designand applications

This paper describes the defect to fault mapper (DEFAM), and its use in integrated circuit test quality analysis and yield prediction. DEFAM analyzes the effects of spot defects on a design during the manufacturing process, and computes the probability of circuit faults that may occur. Unlike traditional tools, DEFAM exploits the design hierarchy to reduce the required analysis effort. It also reports faults in terms of the design hierarchy, which is essential for many applications. Yield analysis results are given for CMOS designs of up to 164 K transistors. Test quality analysis results are given for an adder module     

Using yield models to accelerate learning curve progress[semiconductor industry]

Worldwide competitive pressure is driving successful semiconductor companies toward ever improving performance-price ratios. In addition, this pressure is accelerating the rate of performance-price improvement. Using yield models can accelerate the rate at which processing experience reduces manufacturing costs. This paper reviews learning curves, outlines an improvement strategy using yield models, presents enhancements, and illustrates an application of yield models to accelerate learning. Detailed, validated models can simulate the yield effects of process and equipment improvement plans. Yield models, used with short-loop defect monitors, allow rapid feedback of experimental results to yield improvement efforts by compressing normal processing cycle times     

A neural-network approach to recognize defect spatial pattern insemiconductor fabrication

Yield enhancement in semiconductor fabrication is important. Even though IC yield loss may be attributed to many problems, the existence of defects on the wafer is one of the main causes. When the defects on the wafer form spatial patterns, it is usually a clue for the identification of equipment problems or process variations. This research intends to develop an intelligent system, which will recognize defect spatial patterns to aid in the diagnosis of failure causes. The neural-network architecture named adaptive resonance theory network 1 (ART1) was adopted for this purpose. Actual data obtained from a semiconductor manufacturing company in Taiwan were used in experiments with the proposed system. Comparison between ART1 and another unsupervised neural network, self-organizing map (SOM), was also conducted. The results show that ART1 architecture can recognize the similar defect spatial patterns more easily and correctly     

基于关键面积的冗余集成电路成品率分析

利用关键面积的思想分析了冗余电路的成品率,并给出了其计算模型.实例模拟表明,与传统的成品率分析方法相比,该模型预测IC成品率具有更高的精度.     

2007年显示周:显示器制造业发展的重点在于经济效益的提高及性能的扩展

在显示器制造业领域,产率和产能是两个关键指标。但是这两方面的进展如何呢?在2007年显示周中,那是大量报告和展览的重点,其中降低成本、扩展性能在显示器制造业中占据着核心位置。     

High Density CID Imagers

The fabrication and performance of large (16K, 60K, and 78K cells) high density CID self-scanned imager arrays is described. Array fabrication used overlapping electrodes of two levels of polysilicon or a first level of polysilicon and a second level of antimony tin oxide. Yield considerations and the special processing steps required to fabricate these large chips are examined. Quantum efficiency curves of these structures are compared.     

High density CID imagers

The fabrication and performance of large (16K, 60K, and 78K cells) high density CID self-scanned imager arrays is described. Array fabrication used overlapping electrodes of two levels of polysilicon or a first level of polysilicon and a second level of antimony tin oxide. Yield considerations and the special processing steps required to fabricate these large chips are examined. Quantum efficiency curves of these structures are compared.