New DCT Computation Technique Based on Scalable Resources

The applicability of MPEG video coding can be improved by scaling both the algorithmic complexity and resource usage, considering the desired application and device that is going to be used. This paper presents a new DCT computation technique of which both the quality and amount of computations is optimised for a limited number of operations. For halved computing resources, about 2-4 SNR dB improvement was obtained when compared to a diagonally oriented computation of coefficients, matching with the conventional MPEG scanning.     

Computation reduction for standard-based video encoders based on the energy preservation property of DCT

Based on the energy preservation property of DCT, an optimization technique for motion estimation (ME), DCT, and quantization for standard-based video encoders is developed. First, a stopping criterion for ME is proposed to reduce the number of checking points in finding the motion vectors, and save the computations. The advantage of introducing such a stopping criterion lies in its adaptability to the quantization parameter and applicability to various fast ME algorithms. Then, the DCT and quantization are jointly optimized by tracing the remaining signal energy and removing unnecessary calculations in the process of DCT and quantization. A pruned 2-D DCT based on Huang's fast DCT algorithm is presented to demonstrate the superiority of this algorithm to the full DCT and an existing all-zero block detection method. Although proved to be computationally efficient, the algorithms introduce no obvious quality loss.     

一种同时计算DFT系数和MDCT系数的新算法

DVT和MDCT是音频编码算法中应用较多的2种时频分析方法。给出了一种同时计算DFT系数和MDCT系数的算法，并对原理进行了简要分析。仿真结果表明，该算法误差小，具有一定的实用性。     

CORDIC-Based Unified Architectures for Computation of DCT/IDCT/DST/IDST

In this paper, CORDIC (coordinate rotation digital computer)-based Cooley-Tukey fast Fourier transform (FFT)-like algorithms for power-of-two point discrete cosine transform/discrete sine transform/inverse discrete cosine transform/inverse discrete sine transform are proposed and their corresponding unified architectures are developed by fully reusing the unique two basic processing elements. The proposed algorithms have some distinguished advantages, such as FFT-like regular data flow, unique post-scaling factor, and arithmetic-sequence rotation angles. The developed unified architectures can compute four different transforms by simple routing the data flow according to the specific transform without feeding different transform coefficients or different transform kernels. The unfolding technique is used to overcome the problem of difficult to realize pipeline that occur in iterative CORDIC algorithms. Compared to existing unified architectures, the proposed architectures have a superior performance in terms of hardware complexity, control complexity, throughput, scalability, modularity, and pipelinability.     

A vehicle detection scheme based on two-dimensional HOG features in the DFT and DCT domains

Multidimensional Systems and Signal Processing - Histogram of oriented gradients (HOG) are often used as features for object detection in images, since they are robust to changes in illumination...     

ESPRIT-like estimation of real-valued sinusoidal frequencies

Subspace-based estimation of multiple real-valued sine wave frequencies is considered in this paper. A novel data covariance model is proposed. In the proposed model, the dimension of the signal subspace equals the number of frequencies present in the data, which is half of the signal subspace dimension for the conventional model. Consequently, an ESPRIT-like algorithm using the proposed data model is presented. The proposed algorithm is then extended for the case of complex-valued sine waves. Performance analysis of the proposed algorithms are also carried out. The algorithms are tested in numerical simulations. When compared with ESPRIT, the newly proposed algorithm results in a significant reduction in computational burden without any compromise in the accuracy.     

一种快速DCT变换方法的优化

对用查表法实现DCT变换的方法进行了优化,将有用的余弦乘积值简化至71个,从而缩小了系数表的规模,加快了变换速度,并详细给出了实现的过程。     

一种快速DCT算法的研究

由于在H．261、H．263、MPEG-1以及MPEG-2等视频编解码标准中,运行频率最高的运算是离散余弦变换(DCT)。因此,运用DCT矩阵的基本性质和基本定律分析,提出了一种快速的离散DCT算法,对于视频编解码的实时处理有着重要的意义。     

Two-stage decomposition of the DCT

The DCT kernel matrix is first decomposed into a block diagonal structure (BDS) with diagonal skew-circular correlated (SCCR) sub-matrices of length 2, 4, ..., N/2 by coset decomposition, and then each of these independent SCCR sub-matrices is further split into two stages by decomposing its elements into a linear combination of other simple basis functions. The preprocessing stage can be treated as a new transform approximated to the DCT, and is suitable for image compression. Various preprocessing stages are obtained by choosing various basis functions. The postprocessing stage is used for converting the preprocessing stage back to the DCT. Both the preprocessing stage and the postprocessing stage are BDSs containing independent diagonal SCCR sub-matrices, thus the fast and parallel computation of both the preprocessing and the postprocessing stages is feasible using methods such as a semisystolic array or distributed arithmetic implementation     

An Orthogonal Time-Frequency Extraction Approach to 2D Systolic Architecture for 1D DFT Computation

An expandable two-dimensional systolic array consisting of N homogeneous processing elements in a rectangular sturcture to compute the one-dimensional DFT transform is proposed. DFT of size N = M² can be computed in 2M steps of pipelined operations, achieving the optimal Area–Time complexity of AT² = O(N²). The architecture is based on a new approach that exploits the symbiosis between the one-dimensional systolic arrays of Kung [6] and Chang [7]. After a two-dimensional formulation with Common Factor Algorithm, recursive time and frequency extractions are applied to the column and row transforms respectively. Twiddle factor multiplication is integrated gracefully into the row recursion. The rearrangement of the input data enables the recursive operations to be pipelined orthogonally in the dual-mode processing elements. The proposed array structure is modular and expandable. A DFT of size 2^LN can be readily computed with 2^L N-size arrays abutted together without reconfiguration. VHDL modules have been written and simulated successfully for the proposed architecture.     

Compression of hyperspectral imagery using the 3-D DCT and hybridDPCM/DCT

Two systems are presented for compression of hyperspectral imagery which utilize trellis coded quantization (TCQ). Specifically, the first system uses TCQ to encode transform coefficients resulting from the application of an 8×8×8 discrete cosine transform (DCT). The second systems uses DPCM to spectrally decorrelate the data, while a 2D DCT coding scheme is used for spatial decorrelation. Side information and rate allocation strategies are discussed. Entropy-constrained code-books are designed using a modified version of the generalized Lloyd algorithm. These entropy constrained systems achieve compression ratios of greater than 70:1 with average PSNRs of the coded hyperspectral sequences exceeding 40.0 dB     

NEDA: a low-power high-performance DCT architecture

Conventional distributed arithmetic (DA) is popular in application-specific integrated circuit (ASIC) design, and it features on-chip ROM to achieve high speed and regularity. In this paper, a new DA architecture called NEDA is proposed, aimed at reducing the cost metrics of power and area while maintaining high speed and accuracy in digital signal processing (DSP) applications. Mathematical analysis proves that DA can implement inner product of vectors in the form of two's complement numbers using only additions, followed by a small number of shifts at the final stage. Comparative studies show that NEDA outperforms widely used approaches such as multiply/accumulate (MAC) and DA in many aspects. Being a high-speed architecture free of ROM, multiplication, and subtraction, NEDA can also expose the redundancy existing in the adder array consisting of entries of 0 and 1. A hardware compression scheme is introduced to generate a butterfly structure with minimum number of additions. NEDA-based architectures for 8 /spl times/ 8 discrete cosine transform (DCT) core are presented as an example. Savings exceeding 88% are achieved, when the compression scheme is applied along with NEDA. Finite word-length simulations demonstrate the viability and excellent performance of NEDA.     

一种用新的D CT算法的C P L D实现

研究了一种基于多项式变换PT法的高效DCT（Discrete Cosine Transfrom)算法,并对该算法进行CPLD（Complex Programmable Logic Device)设计。该设计中,提出了一种全新的硬件实现结构－－查找表（LUT）,该结构在乘法次数及资源利用率方面都比现行的其它算法具有更多的优越性能。     

一维长序DFT的协处理阵列结构设计与实现

文章针对一维长序DFT计算问题，分析其计算结构以及算法的并行性，提出一种阵列协处理结构．并分析这种协处理机结构上DFT计算的组织及具体实施算法步骤和方法，并对这种协处理阵列结构上运行的DFT进行复杂性分析。这对计算DFT专用集成协处理结构芯片开发，提高专用嵌套系统性能非常实用。     

Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Codec

Several parallel, pipelined and folded architectures with different throughput rates are presented for computation of DCT, one of the fundamental operations in image/video coding. This paper begins with a new decomposition algorithm for the 1-D DCT coefficient matrix. Then the 2-D DCT problem is converted into the corresponding 1-D counterpart through a regular index mapping technique. Afterward, depending on the trade-off between hardware complexity and speed performance, the derived decomposition algorithm is transformed into different parallel-pipelined and folded architectures that realize the butterfly operations and the post-processing operations. Compared to other DCT processor, our proposed parallel-pipelined architectures, without any intermediate transpose memory, have the features of modularity, regularity, locality, scalability, and pipelinability, with arithmetic hardware cost proportional to the logarithm of the transform length.     

On the computation of two-dimensional DCT

A new fast algorithm for the type-II two-dimensional (2-D) discrete cosine transform (DCT) is presented. It shows that the 2-D DCT can be decomposed into cosine-cosine, cosine-sine, sine-cosine, and sine-sine sequences that can be further decomposed into a number of similar sequences. Compared with other reported algorithms, the proposed one achieves savings on the number of arithmetic operations and has a recursive computational structure that leads to a simplification of the input/output indexing process. Furthermore, the new algorithm supports transform sizes (p₁*2^m1)×(p₂*2 ^m2), where p₁ and p₂ are arbitrarily odd integers, which provides a wider range of choices on transform sizes for various applications     

Computation of the continuous-time PAR of an OFDM signal with BPSKsubcarriers

A procedure for computing the continuous-time peak-to-average power ratio (PAR) of an orthogonal frequency-division multiplexing (OFDM) signal, with binary phase-shift keying (BPSK) subcarriers, is developed. It is shown that the instantaneous envelope power function (EPF) can be transformed into a linear sum of Chebyshev polynomials. Consequently, the roots of the derivative of EPF can be obtained by solving a polynomial. Using the procedure to evaluate the difference between the continuous-time and discrete-time PAR, it is shown that an oversampling factor of four is accurate     

一种射频识别卡电路的可测性设计

随着CMOS器件进入深亚微米阶段,集成电路的规模、复杂度以及测试成本都急剧提高,与此同时人们对集成电路的可靠性要求也越来越高。集成电路系统的测试是一个费时而艰巨的过程,必须综合考虑到测试的功能、性能等诸多问题,并能以较低的成本来实现较高质量的测试,因此对超大规模集成电路的测试研究已成为IC设计中不可缺少的一部分。而可测试性设计(DFT)就是通过增加辅助电路来降低电路的测试难度、从而降低其测试成本的一种测试。文章针对一款非接触式射频卡电路,分析了其工作原理和模块组成,研究了其测试电路,通过对输出端口信息的测试,可以清楚地知道内部各模块的功能与性能,达到了验证电路可靠性的目的。     

AWG中阵列波导耦合系数的计算

针对阵列波导光栅（AWG）中阵列波导耦合系数的计算问题，提出了基于光束传播方法（BPM）的叠加积分方法的修正方法。将修正前、后的结果与简单叠加积分方法的结果作了分析比较，从而验证了修正方法的正确性。分析了阵列波导之间的耦合对耦合系数的影响，阵列波导间距越小，影响越大。     

Computation of the scattering from inhomogeneous objects with adiscrete rotational symmetry and a nonsymmetric part

Using a specific solver for circulant matrices can reduce the cost of computing the scattering from a discrete rotational symmetric object by up to several orders of magnitude. A solver is developed for symmetric objects with a nonsymmetrical part (such as an antenna on a body of revolution). This solver has been implemented in a finite-element code based upon a hybrid formulation. The hybrid formulation combines integral equations and partial differential equations; it can handle inhomogeneous anisotropic objects of arbitrary shape. Results on inhomogeneous objects with defects are shown. The solver can also be used to perform a parametric study of the defects