Cu—Cu键合工艺及其在高功率声光器件中的应用

介绍了一种低温Cu—Cu扩散键合工艺技术,利用电子束蒸发Cr/Cu薄膜作为键合层制作了声光调制器。实验表明,Cr/Cu/Cu/Cr键合层厚为755.5 nm、键合温度120℃、键合压强30 MPa时,器件键合强度可达2.7 MPa。采用该工艺制作的调制器能够承受的最大电功率为8 W/mm~2,且峰值衍射效率达到70%,为研制高功率声光器件奠定了工艺基础。     

一种高功率密度声光器件

针对高功率密度声光器件的应用需求,采用高熔点金属材料来制备器件键合层。通过ANSYS有限元分析软件建立器件热仿真模型,完成了对器件的热设计优化,并制作器件进行了验证。结果表明,器件在2 000 nm工作波长下衍射效率为81.6%,功率密度达到125.0 W/cm~2。     

Si面键合技术及其应用

回顾了Ｓｉ面键合技术的历史，研究了国外此工艺技术发展过程与趋势，分析了Ｓｉ面直接键合技术的特点和它在压电与声光器件中的应用。     

单偏振光纤声光调制器

该文介绍了一种全光纤耦合的单偏振声光调制器的设计及应用。理论分析了光纤声光调制器的工作原理,描述了单偏振光纤声光调制器的关键指标(插入损耗、消光比、光脉冲上升时间)的设计方法和单偏振光纤准直器的耦合工艺方法。设计制作了工作在1.06 μm波长的高速低插损单偏振光纤声光调制器,其偏振消光比达到42 dB,能有效隔离系统偏振噪声。     

Au/Sn共晶键合技术在MEMS封装中的应用

研究了Au/Sn共晶圆片键合技术在MEMS气密性封装中的应用。设计了共晶键合多层材料的结构和密封环图形,盖帽层采用Ti/Ni/Au/Sn/Au结构,器件层采用Ti/Ni/Au结构,盖帽层腔体尺寸为4.5 mm×4.5 mm×20μm,Au/Sn环的宽度为700μm,优化了键合工艺,对影响气密性的因素(如组分配比、键合前处理和键合温度等)进行了分析。两层硅片在氮气气氛中靠静态的压力实现紧密接触。在峰值温度为300℃、持续时间为2 min的条件下实现了良好的键合效果,其剪切力平均值达到16.663 kg,漏率小于2×10-3 Pa·cm3/s,满足检验标准(GJB548A)的要求,验证了Au/Sn共晶键合技术在MEMS气密封装中的适用性。     

通过热应力分析改善AOTF键合层附着力

针对声光可调滤光器(AOTF)压电换能器和声光晶体键合后出现附着力差的问题开展分析,根据热应力理论计算AOTF键合层各层的热应力分布情况,提出通过增加过渡层改善键合层应力特性。当过渡层Au膜厚为200nm时,理论上键合层和声光晶体间的热应力减小到-0.613 MPa,能够保证膜层的附着强度。测试结果显示,添加过渡层后频率响应的3dB带宽增加,衍射效率提高了2%~4%。     

用于MEMS器件的键合工艺研究进展

随着MEMS器件的广泛研究和快速进步,非硅基材料被广泛用于MEMS器件中.键合技术成为MEMS器件制作、组装和封装的关键性技术之一,它不仅可以降低工艺的复杂性,而且使许多新技术和新应用在MEMS器件中得以实现.目前主要的键合技术包括直接键合、阳极键合、粘结剂键合和共晶键合.     

一种具有偏振保持能力的光纤耦合声光器件

该文报道了一种具有偏振保持能力的光纤耦合声光器件,对声光介质及保偏光纤的偏振特性进行了分析,并对器件设计思路及性能参数进行了介绍。样品器件采用TeO2作为声光介质;PM980光纤作为耦合光纤;在工作波长1 053nm、频率100 MHz下获得插入损耗为2.4dB、通断消光比为50dB、偏振消光比为22.24dB。     

微米尺度下键合强度的评价方法和测试结构

在MEMS器件的设计与加工过程中，键合技术是体硅工艺的一项关键技术。由于MEMS器件的特点，其键合的面积通常是在微米到毫米量级内．传统测试键合强度的方法不再适用，该尺度下键合强度的测试与评价成为MEMS工艺测试的难点之一。文章提出了一种新型的测试结构．对面积为微米量级下键合的最大抗扭强度进行了测试。实验设计一系列的单晶硅悬臂梁结构测试键合面积在微米量级时的最大剪切力．键合面为常用的正方形．其边长从6μm到120μm，计算得出的剪力与采用实体单元有限元分析结果计算出的作用力相对误差为4．9％，这一误差在工程中是可以接受的。实验得出最大剪切扭矩和相应的键合面积的曲线。MEMS器件的设计人员可以根据结论曲线．针对所需的抗扭强度设计相应的键合面积。     

硅MEMS器件键合强度在线检测方法

键合强度是MEMS器件研制中一个重要的工艺质量参数,键合强度检测对器件的可靠性具有十分重要的作用。为了获得MEMS器件制造工艺中的键合强度,提出了一种键合强度在线检测方法,并基于MEMS叉指式器件工艺介绍了一种新型键合强度检测结构;借助于材料力学的相关知识,推导出了键合强度计算公式,经过工艺实验,获得了键合强度检测数据;对获得的不同键合面积的键合强度加以对比,指出这些数据的较小差异,是由刻度盘最小刻度误差和尺度效应造成的。结合叉指式器件的工作环境,认为这种方法获得的键合强度更接近实际的工作情况。     

Increasing bondability and bonding strength of gold stud bumps onto copper pads with a deposited titanium barrier layer

A flip-chip assembly is an attractive scheme for use in high performance and miniaturized microelectronics packaging. Wafer bumping is essential before chips can be flip-bonded to a substrate. Wafer bumping can be used for mechanical-single point stud bump bonding (SBB), and is based on conventional thermosonic wire bonding. This work proposes depositing a titanium barrier layer between the copper film and the silver bonding layer to achieve perfect bondability and sufficiently strong thermosonic bonding between a stud bump and the copper pad.A titanium layer was deposited on the copper pads to prevent copper atoms from out-diffusing during thermosonic stud bump bonding. A silver film was then deposited on the surface of the titanium film as a bonding layer to increase the bondability and bonding strength for stud bumps onto copper pads. The integration of the silver bonding layer with a diffusion barrier layer of titanium on the copper pads yielded 100% bondability between the stud bump and pads. The strength of bonding between the gold bumps on the copper pads significantly exceeds the minimum average values in JEDEC specifications. The diffusion barrier layer of titanium effectively prevents copper atoms from out-diffusing to the silver bonding layer surface during thermosonic bonding, which fact can be interpreted with reference to the experimental results of energy dispersive spectrometry (EDS) and analyses of Auger depth profiles. This diffusion barrier layer of titanium efficiently provides perfect bondability and sufficiently strong bonding between a stud bump and copper pads with a silver bonding layer.     

基于Al2O3中间层的InP/SOI晶片键合技术研究

研究了基于Al2O3中间层的InP/SOI晶片键合技术.该方案利用原子层沉积技术在SOI晶片表面形成Al2O3作为InP/SOI键合中间层,同时采用氧等离子体工艺对晶片表面进行活化处理.原子力显微镜和接触角测试结果表明,氧等离子体处理使得晶片的表面特性更适于实现键合.透射电子显微镜和X射线能谱仪测试结果证实,采用Al2O3中间层可以实现InP晶片与SOI晶片的可靠键合.     

High-quality crystalline layer transfer from a silicon-on-insulator substrate onto a sapphire substrate using wafer bonding

We demonstrate layer transfer of 150 nm of Si from a 200-mm, silicon-on-insulator (SOI) substrate onto a sapphire substrate using low-temperature wafer bonding (T=150°C). The crystalline quality and the thermal stability of the transferred Si layer were characterized by x-ray diffraction (XRD). A broadening of the (004) Si peak is observed only for anneal temperatures T_A≥800°C, indicating some degradation of the crystalline quality of the transferred Si film above these temperatures. The measured electron Hall mobility in the bonded Si layer is comparable to bulk silicon for T_A≤800°C, indicating excellent material quality.     

Thermal and mechanical separations of silicon layers from hydrogen pattern-implanted wafers

A silicon layer was successfully transferred from a hydrogen pattern-implanted wafer to another by a thermal or mechanical cleavage process. The first wafer was masked with various patterns of 2.3 micron-thick poly-silicon, and was implanted at a hydrogen dose of 4,5, or 8 10¹⁶ cm⁻² with an energy of 150 keV or 180 KeV. After etching off the implantation mask, the wafer was bonded to a thermally grown oxide wafer face-to-face by low-temperature direct bonding. The bonded pair was then either heated (thermally) or bent (mechanically) until hydrogen-induced silicon layer cleavage occurred, resulting in the silicon layer transfer from the implanted wafer to the other. In this experiment, it was demonstrated that mechanical cleavage can overcome the fractional implantation area limination of thermal cleavage.     

Gold Stud Bumps Flip-Chip Bonded onto Copper Electrodes with Titanium and Silver Layers

The purpose of this study was to develop the thermosonic flip-chip bonding process for gold stud bumps bonded onto copper electrodes on an alumina substrate. Copper electrodes were deposited with silver as the bonding layer and with titanium as the diffusion barrier layer. Deposition of these layers on copper electrodes improves the bonding quality between the gold stud bumps and copper electrodes. With appropriate bonding parameters, 100% bondability was achieved. Bonding strength between the gold stud bumps and copper electrodes was much higher than the value converted from the standards of the Joint Electron Device Engineering Council (JEDEC). The effects of process parameters, including bonding force, ultrasonic power, and bonding time, on bonding strength were also investigated. Experimental results indicate that bonding strength increased as bonding force and ultrasonic power increased and did not deteriorate after prolonged storage at elevated temperatures. Thus, the reliability of the high-temperature storage (HTS) test for gold stud bumps flip-chip bonded onto a silver bonding layer and titanium diffusion barrier layer is not a concern. Deposition of these two layers on copper electrodes is an effective and direct method for thermosonic flip-chip bonding of gold stud bumps to a substrate, and ensures excellent bond quality. Applications such as flip-chip bonding of chips with low pin counts or light-emitting diode (LED) packaging are appropriate.     

硅/玻璃紫外固化中间层键合

利用玻璃的透光特性和紫外固化的成熟技术,研究了一种使用紫外固化胶作为中间层的玻璃/硅室温键合工艺.通过选择一定波段的紫外固化胶,旋涂紫外胶后使用365nm光刻机作为紫外光源控制紫外固化,从而实现了硅/玻璃的中间层键合.分析测试结果表明,紫外固化辅助的中间层键合可以成功应用于硅/玻璃键合,中间层厚5～6μm,键合强度达到26MPa.该工艺只需室温条件,简单高效,成本低廉,无需额外的压力或电场,对于硅/玻璃低温键合封装具有潜在的应用价值.     

Silicon layer transfer using wafer bonding and debonding

Two experiments were performed that demonstrate an extension of the ion-cut layer transfer technique where a polymer is used for planarization and bonding. In the first experiment hydrogen-implanted silicon wafers were deposited with two to four microns low-temperature plasma-enhanced tetraethoxysilane (TEOS). The wafers were then bonded to a second wafer, which had been coated with a spin-on polymer. The bonded pairs were heated to the ion-cut temperature resulting in the transfer of a 400 nm layer silicon. The polymer enabled the bonding of an unprocessed silicon wafer to the as-deposited TEOS with a microsurface roughness larger than 10 nm, while the TEOS provided sufficient stiffness for ion cut. In the second experiment, an intermediate transfer wafer was patterned and vias were etched through the wafer using a 25% tetramethylammonium hydroxide (TMAH) solution and nitride as masking material. The nitride was then stripped using dilute hydrofluoric acid (HF). The transfer wafer was then bonded to an oxidized (100 nm) hydrogen-implanted silicon wafer. After ion-cut annealing a silicon-on-insulator (SOI) wafer was produced on the transfer wafer. The thin silicon layer of the SOI structure was then bonded to a third wafer using a spin-on polymer as the bonding material. The sacrificial oxide layer was then etched away in HF, freeing the thin silicon from the transfer wafer. The result produced a thin silicon-on-polymer structure bonded to the third wafer. These results demonstrate the feasibility of transferring a silicon layer from a wafer to a second intermediate “transfer” or “universal” reusable substrate. The second transfer step allows the thin silicon layer to be subsequently bonded to a potential third device wafer followed by debonding of the transfer wafer creating stacked three-dimensional structures.     

具有非平面埋氧层的新型SOI材料的制备

提出一种基于SDB技术的非平面埋氧层SOI材料制备方法.其关键技术包括:通过干法刻蚀、高压氧化和淀积二氧化硅获得高质量非平面埋氧层;通过化学气相淀积多晶硅来形成键合缓冲层,并运用回刻光刻胶和化学机械抛光来实现键合面的局部和全局平坦化;通过室温真空贴合、中温预键合和高温加固键合来进行有源片和衬底片的牢固键合.基于该技术研制了有源层厚度为21μm、埋氧层厚度为0.943μm、顶面槽和底面槽槽高均为0.9μm的具有双面绝缘槽结构的非平面埋氧层新型SOI材料.测试结果表明该材料具有结合强度高、界面质量好、电学性能优良等优点.     

Improvement of heteroepitaxial growth by the use of twist-bonded compliant substrate: Role of the surface plasticity

In a first step, we have investigated the structure and the mechanical behavior of twist-bonded GaAs-compliant substrates. For a twist angle lower than 15°, the bonded interface was observed to contain a dense network of pure screw dislocations. For a larger twist angle, no dislocations were observed at the bonding interface. The mechanical behavior of these compliant substructures were investigated using nanoindentation, and the results were compared to those obtained on standard bulk GaAs. It appears that the nature of the interface has a great influence on the mechanical properties of these compliant substrates. In a second step, InGaAs alloys were grown on such compliant structures, and their quality was compared to that of layers grown on standard substrates. A promising improvement was observed on compliant structures.     

一种新型半绝缘键合SOI结构

报道了一种新型半绝缘键合SOI结构,采用化学气相淀积加外延生长键合过渡多晶硅层的方法实现了该结构.研制出的这种新结构,完整率大于85%,Si-Si键合界面接触比电阻小于5×10-4Ω·cm2.这种新结构可以广泛用于高低压功率集成电路、高可靠集成电路、MEMS、硅基光电集成等新器件和电路中.