High-voltage (3 kV) UMOSFETs in 4H-SiC

Vertical trench-gate metal-oxide-semiconductor field-effect transistors (UMOSFETs) in 4H-SiC having both trench oxide protection and junction termination extension (JTE) are reported for the first time. Devices are fabricated with and without counter-doped channels. Blocking voltages and specific on-resistances are 3360 V and 199 mΩ-cm² for doped-channel FETs and 3055 V and 121 mΩ-cm² for FETs without doped channels. These blocking voltages are the highest reported to date for UMOSFETs in SiC     

A new on-chip ESD protection circuit with dual parasitic SCRstructures for CMOS VLSI

A new CMOS on-chip electrostatic discharge (ESD) protection circuit which consists of dual parasitic SCR structures is proposed and investigated. Experimental results show that with a small layout area of 8800 μ², the protection circuit can successfully perform negative and positive ESD protection with failure thresholds greater than ±1 and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. The low ESD trigger voltages in both SCRs can be readily achieved through proper circuit design and without involving device or junction breakdown. The input capacitance of the proposed protection circuit is very low and no diffusion resistor between I/O pad and internal circuits is required, so it is suitable for high-speed applications. Moreover, this ESD protection circuit is fully process compatible with CMOS technologies     

Low-temperature growth of silicon-boron layer as solid diffusionsource for polysilicon contacted p+-n shallow junction

A new material, Si-B, is proposed as a solid diffusion source for fabrication of poly-Si contacted p⁺-n shallow junctions. The junction depth of the Si-B source diode has been measured and compared with that of a BF₂⁺-implanted poly-Si source diode. It was found that the Si-B source diode had a much shallower junction and was less sensitive to thermal budget than the BF₂⁺ source diode. This was attributed to the smaller surface concentration and diffusivity of boron in the silicon in Si-B source diodes. Regarding electrical characteristics of diodes with a junction depth over 500 Å, a forward ideality factor of better than 1.01 over 8 decades and a reverse-current density lower than 0.5 nA/cm² at -5 V were obtained. As the junction depth shrank to 300 Å, the ideality factor and reverse current density of diodes increased slightly to 1.05 and 1.16 nA/cm², respectively. These results demonstrated that a uniform ultrashallow p⁺-n junction can be obtained by using a thin Si-B layer as a diffusion source     

Computer calculation of silicon avalanche diodes

The efficiency η and output power P per unit area were computed for silicon p-n-n⁺avalanche diodes having an active region of 5 microns. The condition for making both η andPmaximum is that the field at the n-n⁺interface generated by impurity and bias voltage is about one fourth of that at the junction under oscillation conditions. The maximum η andPwere calculated to be about 20.5 per cent and 53 kW/cm². Dc current density J0for maximumPwas about 4200 A/cm². On the other hand, J0for maximum η was calculated to be about 800 A/cm². It was found that a diode having an abrupt type junction is the best. The condition under which a diode is represented by use of a diode with abrupt type junction is that the region of a homogeneous field near the junction is less than one fifth of the space-charge region.     

Process limitation and device design tradeoffs of self-aligned TiSi2 junction formation in submicrometer CMOS devices

Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive metallization scheme to solve many CMOS scaling problems. However, to achieve a shallow junction with a salicide structure requires careful optimization for device design tradeoffs. Several proposed techniques to form shallow titanium silicide junctions are critically examined. Boron, BF₂, arsenic, and phosphorus dopants were used to study the process parameters for low-leakage TiSi ₂ p⁺/n and n⁺/p junctions in submicrometer CMOS applications. It is concluded that the dopant drive-out (DDO) from the TiSi₂ layer to form a shallow junction scheme is not an efficient method for titanium salicide structure; poor device performance and unacceptably leaky junctions are obtained by this scheme. The conventional post junction salicide (PJS) scheme can produce shallow n⁺/p and p⁺/n junctions with junction depths of 0.12 to 0.20 μm below the TiSi₂. Deep submicrometer CMOS devices with channel length of 0.40 to 0.45 μm can be fabricated with such junctions     

Electrical characterization of ultra-shallow junctions formed bydiffusion from a CoSi2 layer

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800-900°C). A thin layer (50 nm) of CoSi₂ was implanted with As or with BF₂ and subsequently annealed at different temperatures and times to form two ultra-shallow junctions with a distance between the silicide/silicon interface and the junction of 14 and 20 nm, respectively. These diodes were investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. The reverse leakage currents for the SADS diodes were as low as 9×10 ^-10 A/cm² for p⁺/n and 2.7×10^-9 A/cm² for n⁺/p, respectively. The temperature dependence of the reverse current in the p ⁺/n diode is characterized by a unique activation energy (1.1 eV) over all the investigated range, while in the n⁺/p diode an activation energy of about 0.42 eV is obtained at 330 K. The analysis of the forward characteristic of the diodes indicate that the p⁺ /n junctions have an ideal behavior, while the n⁺/p junctions have an ideality factor greater than one for all the temperature range of the measurements. TEM delineation results confirm that, in the case of As diffusion from CoSi₂, the junction depth is not uniform and in some regions a Schottky diode is observed in parallel to the n⁺/p junction. Finally, from the C-V measurements, an increase of the diodes area of about a factor two is measured, and it is associated with the silicide/silicon interface roughness     

Dramatic increases in latchup holding voltage for sub-0.5 μmCMOS using shallow S/D junctions

Large increases in the latchup holding voltage are demonstrated with the use of shallow source-drain junctions in a sub-0.5 μm CMOS process. Holding voltages well above the supply voltage for 2 μm n ⁺/p⁺ spacings are demonstrated without the use of complex processes such as retrograde wells or buried layers. SIMS data is presented to verify the reduction in junction depths to 0.15 μm for the p⁺/n-well and 0.14 μm for the n⁺/p-well junction. The improvement in holding voltage is attributed to reductions in parasitic bipolar transistor gains, due to the increase in base width. Well behaved transistor characteristics are presented using the shallow junction technology     

Reliability of AlInAs/GaInAs heterojunction bipolar transistors

The reliability of high-performance AlInAs/GaInAs heterojunction bipolar transistors (HBTs) grown by molecular beam epitaxy (MBE) is discussed. Devices with a base Be doping level of 5×10¹⁹ cm^-3 and a base thickness of approximately 50 nm displayed no sign of Be diffusion under applied bias. Excellent stability in DC current gain, device turn-on voltage, and base-emitter junction characteristics was observed. Accelerated life-test experiments were performed under an applied constant collector current density of 7×10⁴ A/cm² at ambient temperatures of 193, 208, and 328°C. Junction temperature and device thermal resistance were determined experimentally. Degradation of the base-collector junction was used as failure criterion to project a mean time to failure in excess of 10⁷ h at 125°C junction temperature with an associated activation energy of 1.92 eV     

Formation of cobalt silicided shallow junction using implantinto/through silicide technology and low temperature furnace annealing

This work investigates the shallow CoSi₂ contacted junctions formed by BF₂⁺ and As⁺ implantation, respectively, into/through cobalt silicide followed by low temperature furnace annealing. For p⁺n junctions fabricated by 20 keV BF₂⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 2 nA/cm² at 5 V reverse bias can be achieved by a 700°C/60 min annealing. This diode has a junction depth less than 0.08 μm measured from the original silicon surface. For n⁺p junctions fabricated by 40 keV As⁺ implantation to a dose of 5×10¹⁵ cm^-2, diodes with a leakage current density less than 5 nA/cm² at 5 V reverse bias can be achieved by a 700°C/90 min annealing; the junction depth is about 0.1 μm measured from the original silicon surface. Since the As⁺ implanted silicide film exhibited degraded characteristics, an additional fluorine implantation was conducted to improve the stability of the thin silicide film. The fluorine implantation can improve the silicide/silicon interface morphology, but it also introduces extra defects. Thus, one should determine a tradeoff between junction characteristics, silicide film resistivity, and annealing temperature     

Some reactive effects in forward biased junctions

The small-signal equivalent parallel capacity of forward-biased semiconductor junctions is strongly dependent on the current. At very low currents (less than 10 µa for a junction area of 1 mm²) the capacity appears to be chiefly due to space charge effects. For currents up to approximately 100 µa, the capacity complies with Shockley's predicted low-level theory. For larger currents, however, there is a definite deviation from the low-level diffusion predominance and capacity reaches a maximum after which it decreases through zero and then goes to large inductive values. The latter phenomena is explained, qualitatively, by considering an inductance in series with the diffusion capacity. The capacity increases linearly with current but the inductance (due to conductivity modulation) increases faster. The result is that a change from an equivalent RC circuit to an equivalent RL circuit is made at high enough currents (5 ma is a typical value for the 1 mm²junction area). Measurements were made on abrupt silicon junction diodes with junction areas of about 7 × 10^-4, 10^-2, 10^-1cm²and on the emitter junction (about 5 × 10^-5cm²) of a diffused base silicon transistor.     

基于石墨烯的肖特基结辐射伏特同位素电池

从传统肖特基结辐射伏特同位素电池金属电极存在的对放射源衰变粒子的阻挡及导电性不理想的问题出发,借鉴石墨烯肖特基结太阳电池结构,将石墨烯/硅肖特基结引入辐射伏特同位素电池中,在63Ni放射源的照射下验证石墨烯/硅肖特基结换能单元在辐射伏特同位素电池中应用的可行性.研究结果发现,基于硝酸掺杂,当少层(3?5层)石墨烯经过4...     

Nitrogen-implanted SiC diodes using high-temperature implantation

6H-SiC diodes fabricated using high-temperature nitrogen implantation up to 1000°C are reported. Diodes were formed by RIE etching a 0.8-μm-deep mesa across the N⁺/P junction using NF₃/O₂ with an aluminum transfer mask. The junction was passivated with a deposited SiO₂ layer 0.6 μm thick. Contacts were made to N⁺ and P regions with thin nickel and aluminum layers, respectively, followed by a short anneal between 900 and 1000°C. These diodes have reverse-bias leakage at 25°C as low as 5×10^-11 A/cm² at 10 V     

Characterization of reverse leakage components for ultrashallowp+/n diodes fabricated using gas immersion laser doping

In this letter we report on fabrication of p⁺/n diodes with junction depths less than 60 nm using gas immersion laser doping (GILD). Statistics for diodes with junction depths of 39 nm and 50 nm, surface concentrations exceeding 10²⁰ atoms/cm³, and sheet resistances less than 160 Ω/□ are presented. Values for area, perimeter, and corner leakage currents are measured at less than 1.6 nA/cm², 2.5 fA/μm and 10 fA/corner respectively, at 3.4 V reverse bias. These characteristics demonstrate that the laser doping process is viable for source/drain doping in 0.18 μm CMOS technology     

STI stress-induced increase in reverse bias junction capacitance

A new contribution to reverse-biased junction capacitance is reported. This component arises from trench isolation stress-induced bandgap narrowing that changes the built-in potential. Experimental junction capacitance measurements show good correlation to simulated oxidation stresses. The reported data agrees well with the predicted values from basic device equations. Stress induced capacitance increase of 12% (7.5%) at 3.3 V reverse bias for p⁺/n (n⁺/ p) junctions, respectively is observed. In addition, well-understood reverse junction leakage relation to stress is also reported. This phenomenon will become increasingly important as trenches become shallower and more tightly spaced     

The effect of Co incorporation on electrical characteristics of n+/p shallow junction formed by dopant implantation into CoSi2 and anneal

The impact of Co incorporation on the electrical characteristics has been investigated in n⁺/p junction formed by dopant implantation into CoSi₂ and drive-in anneal. The junctions were formed by As⁺ (30 or 40 keV, 1×10¹⁶ cm ^-2) implantation into 35 nm-thick CoSi₂ followed by drive-in annealing at 900°C for 30 s in an N₂ ambient. Deeper junction implanted by As⁺ at 40 keV was not influenced by the Co incorporation. However, for shallower junction implanted by As ⁺ at 30 keV, incorporation of Co atoms increased its leakage current, which were supposed to be dissociated from the CoSi₂ layer by silicide agglomeration during annealing. The mechanism of such a high leakage current was found to be Poole-Frenkel barrier lowering induced by high density of Co traps     

Small offset-voltage In0.49Ga0.51P/GaAsdouble-barrier bipolar transistor

In_0.49Ga_0.51P/GaAs double-barrier bipolar transistors (DBBTs) grown by gas-source molecular beam epitaxy (GSMBE) have been fabricated and measured. This structure has two InGaP barrier layers (100 Å in thickness): one is inserted between the emitter-base (e-b) junction and the other between the base-collector (b-c) junction. An offset voltage of 26 mV and a differential current gain of 120 at room temperature were obtained with a heavily doped p⁺ (2×10¹⁹ cm^-3) base (500 Å in thickness). The small offset voltage was attributed to the similar structure of the e-b and b-c junctions and to the suppression of the hole injection current into the collector by the InGaP hole barrier at the b-c junction     

Fully-planar AlGaAs/GaAs HBT's achieved by selective CBE regrowth

This paper describes a novel fully planar AlGaAs/GaAs heterojunction bipolar transistor (HBT) technology using selective chemical beam epitaxy (CBE). Planarization is achieved by a selective regrowth of the base and collector contact layers. This process allows the simultaneous metallization of the emitter, base and collector on top of the device. For the devices with an emitter-base junction area of 2×6 μm² and a base-collector junction area of 14×6 μm², a current gain cut off frequency of 50 GHz and a maximum oscillation frequency of 30 GHz are achieved. The common emitter current gain h_FE is 25 for a collector current density J_c of 2×10⁴ A/cm²     

Improvement of tunnel compensated quantum well infrared detector

To reduce the difficulty of the epitaxy caused by multiple quantum well infrared photodetector (QWIP) with tunnel compensation structure, an improved structure is proposed. In the new structure, the superlattices are located between the tunnel junction and the barrier as the infrared absorption region, eliminating the effect of doping concentration on the well width in the original structure. Theoretical analysis and experimental verification of the new structure are carried out. The experimental sample is a two-cycle device, each cycle contains a tunnel junction, a superlattice infrared absorption region and a thick barrier. The photosurface of the detector is 200 × 200 μm² and the light is optically coupled by 45° oblique incidence. The results show that the optimal operating voltage of the sample is –1.1 V, the dark current is 2.99 × 10^–8 A, and the blackbody detectivity is 1.352 × 10⁸ cm·Hz^1/2·W^–1 at 77 K. Our experiments show that the new structure can work normally.     

Electrical characteristics of 4.5 kV implanted anode 4H-SiC p-i-njunction rectifiers

4500 V 4H-SiC p-i-n junction rectifiers with low on-state voltage drop (3.3-4.2 V), low reverse leakage current (3×10^-6 A/cm²), and fast switching (30-70 ns) have been fabricated and characterized. Forward current-voltage measurements indicate a minimum ideality factor of 1.2 which confirms a recombination process involving multiple energy levels. Reverse leakage current exhibits a square root dependence on voltage below the punchthrough voltage where leakage currents of less than 3×10^-6 A/cm² are measured. Reverse recovery measurements are presented which indicate the presence of recombination at the junction perimeter where a surface recombination velocity of 2-8×10⁵ cm/s is found. These measurements also indicate drift layer bulk carrier lifetimes ranging from 74 ns at room temperature to 580 ns at 250°C     

Method for simultaneous measurement of diffusivity lifetime, anddiffusion length, with application to heavily doped silicon

A novel experimental method is presented and demonstrated that allows simultaneous determination of minority-carrier diffusivity, lifetime, and diffusion length in semiconductors. This method is based on the lateral collection of photogenerated carriers by a semi-infinite junction. The semi-infinite nature of the problem makes possible the use of closed-form expressions that greatly simplify the analysis of the experimental results. The main advantages of this method are its analytical simplicity and the self-consistency test provided by the simultaneous measurement of all three transport parameters. The effects of the lifetime and the diffusion coefficient are separated by varying the distance between the illumination edge and the collecting junction. Results of measurements for heavily doped n⁺ silicon with doping density of 2.4×10¹⁹ cm^-3 are demonstrated