Simulink-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation

As a solution for dealing with the design complexity of multiprocessor SoC architectures, we present a joint Simulink-SystemC design flow that enables mixed hardware/software refinement and simulation in the early design process. First, we introduce the Simulink combined algorithm/architecture model (CAAM) unifying the algorithm and the abstract target architecture. From the Simulink CAAM, a hardware architecture generator produces architecture models at three different abstract levels, enabling a trade-off between simulation time and accuracy. A multithread code generator produces memory-efficient multithreaded programs to be executed on the architecture models. To show the applicability of the proposed design flow, we present experimental results on two real video applications.     

An application-specific architecture for the RBN-coder with efficient memory organization

The number of document compression algorithms is increasing due to the expanded information exchange in our society and due to the increasing quality demands for color documents. For these purposes, high quality and complex compression algorithms are needed, in order to keep the memory size and channel capacity within realistic bounds. In addition, these algorithms must be executed within a certain real-time specification, in order to reduce the user wait times. In this article, an optimized RBN-algorithm for coding true color documents will be used as a test vehicle. Unfortunately, the typical properties of such high-throughput algorithms restricts the possible real-time realizations. We believe that an application-specific design approach supported with powerful CAD-tools is the most efficient implementation for these type of applications when a reasonable time-to-market needs to be achieved. An efficient dedicated architecture is proposed, based on a lowly multiplexed co-operating data-path style. As for most complex video applications, the cost minimization and performance optimization are highly dependent on the memory organization. Hence the latter is the most important topic of this article. The architectural design process has been traversed mostly manually with use of some prototype synthesis tools from the merging CATHEDRAL-3 synthesis environment.     

Synthesis of synchronous communication hardware in a multiprocessor architecture

ESPA is a high level synthesis tool targeted at the design of synchronous communication hardware in a multiprocessor architecture. IO communication can also be handled. It makes use of a new memory based architectural model which allows ESPA to generate efficient solutions for audio, speech and telecom applications. This will be shown using a complex example taken from a compact disc application.     

CoWare—A design environment for heterogeneous hardware/software systems

This paper addresses CoWare: an environment for design of heterogeneous systems on chip. These systems are heterogeneous both in terms of specification and implementation. CoWare is based on a communicating processes data-model which supports encapsulation and refinement and makes a strict separation between functional and communication behaviour. Encapsulation enables the reuse of existing specification and design environments (languages, simulators, compilers). Refinement provides for a consistent and integrated path from specification to implementation. The design steps that will be addressed include: system specification, simulation at various abstraction levels, data path synthesis, communication refinement and hardware/software co-design. A spread-spectrum based pager system serves to illuminate the design process in the CoWare environment.     

一种适合硬件实现的高效算术编码

本文提出了利用表查找来实现二值算术编码,避免乘除法运算,可以简化硬件设计。该算法具有较小的概率逼近误差,因此性能退化较小。     

SpecSyn: an environment supporting the specify-explore-refineparadigm for hardware/software system design

System-level design issues are gaining increasing attention, as behavioral synthesis tools and methodologies mature. We present the SpecSyn system-level design environment, which supports the new specify-explore-refine (SER) design paradigm. This three-step approach to design includes precise specification of system functionality, rapid exploration of numerous system-level design options, and refinement of the specification into one reflecting the chosen option. A system-level design option consists of an allocation of system components, such as standard and custom processors, memories, and buses, and a partitioning of functionality among those components. After refinement, the functionality assigned to each component can then he synthesized to hardware or compiled to software. We describe the issues and approaches for each part of the SpecSyn environment. The new paradigm and environment are expected to lead to a more than ten times reduction in design time, and our experiments support this expectation     

Multilevel design and verification of hardware/software systems

It is pointed out that most real systems in information technology are based on cooperating hardware and software, and the hardware is more than a single chip. System design can be viewed as a massively multidimensional optimization problem for which the solution set is only partially known. Experimental exploration of the design space is the only available approach. A number of projects carried out at Lund University demonstrate that a dramatic increase in system performance and design productivity can be gained. The approach includes a new attitude to the design process, a new role for the designer, new design methodology, and new concepts. It has been shown that, by making extensive use of modern tools, the designer can develop and evaluate a set of hierarchical functional models of the entire system during the design process and establish well-defined relationships between the models     

On hardware/software trade-offs in computer system design

The communication path between the computer users and the computer manufacturer is not a very effective one, but it is the vehicle whereby hardware/software trade-offs are realized. The purpose of this paper is to discuss the concept of hardware/software trade-offs from the perspective of the hardware designer. Primarily, the paper will examine software oriented functions/goals/requirements and discuss considerations in determining the kind of hardware support which would be involved in implementing the particular concept.     

A software/reconfigurable hardware SAT solver

This paper introduces a novel approach for solving the Boolean satisfiability (SAT) problem by combining software and configurable hardware. The suggested technique avoids instance-specific hardware compilation and, as a result, allows the total problem solving time to be reduced compared to other approaches that have been proposed. Moreover, the technique permits problems that exceed the resources of the available reconfigurable hardware to be solved. The paper presents the results obtained with some of the DIMACS benchmarks and a comparison of our implementation with other available SAT solvers based on reconfigurable hardware. The hardware part of the satisfier was realized on Virtex XCV812E FPGA, which has a large volume of embedded memory blocks that provide direct support for the proposed approach.     

A multiprocessor architecture for Viterbi decoders with linearspeedup

A family of multiprocessor architectures implementing the Viterbi algorithm is presented. The family of architectures is shown to be capable of achieving an increase in throughput that is directly proportional to the number of processors when the number of processors is smaller than the constraint length v of the code. The hardware utilization and the depth of the pipelining available inside each processor are also shown. An architecture with v-1 processors is found to be particularly advantageous, since it results in the maximum speedup and simplest interconnection structure     

Using a software reliability model to design a telecommunicationssoftware architecture

The author proposes a software reliability model for a large real-time telecommunications software architecture. Some simple examples of the critical components of the software architecture and their dependencies are described. The component dependencies permit the propagation of faults from the component in which the fault originates to the other components. This propagation can cause failures in the chain (or in the tree) of components. Detection and failures depends on the tests executed or on the number and type of customer requests. An error can occur in any component. This error can be caused by a fault that propagated from another component or it can be a fault that originates in that component. The error can be traced through the component-dependency chain (or tree) to repair all the faults that are associated with that error. The software reliability model guides the design of the software architecture     

基于虚拟原型机的软/硬件协同验证中高效调试手段的实现

针对基于虚拟原型机的软件/硬件协同验证环境中软件调试困难的缺点,通过在原协同验证环境中增加虚拟监视控制单元(VMCU)、外部工具等部件,实现了高效的调试手段.借助这些调试手段,开发人员可以快速定位并排除错误,从根本上提高了协同验证中调试的效率和准确性.     

Fast algorithm and efficient hardware architecture of half-pixel interpolation unit for H.264/AVC

A fast half-pixel motion estimation algorithm and its corresponding hardware architecture are presented. Unlike three steps are needed in typical half-pixel motion estimation algorithm, the presented algorithm needs only two steps to obtain all the interpolated pixels of an entire 8′8 block. The proposed architecture works in a parallel way and is simulated by Modelsim 6.5 SE, synthesized to the Xilinx Virtex4 XC4VLX15 Field Programmable Gate Array(FPGA) device, and verified by hardware platform. The implementation results show that this architecture can achieve 190 MHz and 11 clock cycles are reduced to complete the entire interpolation process in comparison with typical half-pixel interpolation, which meets the requirements of real-time application for very high defination videos.     

可重构计算平台的硬件结构设计

针对现有可重构计算硬件平台配置时间长、灵活性受限的缺陷问题,介绍了一种基于PC机的FPGA可重构硬件平台结构的设计方法,该结构允许PCI总线快速重构,整个系统的硬件设计可以按以下两个部分进行设计:固定部分和可重构部分。最后在FPGA资源上的验证结果表明该设计能够有效实现FPGA的硬件重构,而且其物理硬件设计简单。     

Using method interception for hardware/software co-development

In many embedded systems, the computational power of an instruction set processor is combined with hardware accelerators. Building such combined systems implies co-design of the software that runs on the processor and the hardware that accelerates the embedded application. During the co-design process, the application is partitioned into a software part (running on the processor) and a hardware part (running on the accelerator). In order to ease the iterative process of partitioning, we introduce a novel design methodology. In our methodology, the interface between hardware and software is transparent to the software designer, and is based on dynamic method interception. Because the interface is transparent and generated automatically, the initial all-software prototype of the system can more easily be refined and partitioned. We show that method interception is inexpensive, and we demonstrate method interception in a real-life application. Using our methodology, embedded systems can be designed fast, reducing time-to-market, while still achieving a high run-time performance.     

Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed

This paper presents a layout-conscious approach for hardware/software codesign of systems-on-chip (SoCs) optimized for latency, including an original algorithm for bus architecture synthesis. Compared to similar work, the method addresses layout related issues that affect system optimization, such as the dependency of task communication speed on interconnect parasitic. The codesign flow executes three consecutive steps: 1) combined partitioning and scheduling: besides partitioning and scheduling, this step also identifies the minimum speed constraints for each data link; 2) IP core placement, bus architecture synthesis, and routing: IP cores are placed using a hierarchical cluster growth algorithm; bus architecture synthesis identifies a set of possible building blocks and then assembles them for minimizing bus length and complexity; poor solutions are pruned using a special table structure and select-eliminated method; and 3) rescheduling for the best bus architecture. This paper offers extensive experiments for the proposed codesign method, including bus architecture synthesis for a network processor and a JPEG SoC.     

New advances of high-level synthesis for efficient and reliable hardware design

The spectacular CMOS technology scaling will continue to evolve and dominate the semiconductor industry. This will lead to tens of billions of transistors integrated on a single chip by the year 2020. However, one significant problem is that the design productivity for complex designs has been lagging behind. In addition to several proposed techniques for dealing with the widening productivity gap, e.g., IP reuse and integration, virtual platform modeling, formal verification and others, high-level synthesis (HLS) has been touted as an important solution as it can significantly reduce the number of man-hours required for a design by raising the level of design abstraction. However, existing HLS solutions have limitations, and studies show that the design quality of HLS can be inferior compared to that of manual RTL design. In this paper, we will present a set of new techniques developed recently to drastically improve HLS solutions, which not only improve the traditional design metrics such as circuit performance and energy efficiency but also emerging metrics such as hardware security and robustness. We will also discuss how HLS can collaborate with other techniques to provide a holistic design methodology that can enable the delivery of high-quality designs with much less design cost and much faster time-to-market.     

A contribution towards model-based design of application-specific MEMS

The design process of heterogeneous systems containing electro-mechanical components and electronic circuits involves expert knowledge, methods, and tools from different engineering domains. Cost-efficient research and development of such heterogeneous systems requires a systematic design flow without gaps. A contribution towards this global goal is presented in this article. A development and synthesis tool for one-dimensional accelerometer MEMS has been implemented, calculating sensor solutions and generating the models and layouts required for a hierarchical design flow in an automatic, module-based approach. Utilizing this flow, different accelerometers have been designed, manufactured, and characterized. A dedicated readout ASIC was developed to validate their dynamic behaviour.     

A pipelined, multiprocessor architecture for a connectionlessserver for broadband ISDN

The direct provision of connectionless service in BISDN calls for servers that are connected to or are part of an ATM network to provide the routing function at input speeds up to 622 Mb/s. Routing is achieved in such a server by changing the VCI/VPI headers in the ATM cells; actual switching is done by existing switches in the ATM network. The paper presents an architecture capable of executing all the functions of a server at input speeds up to 622 Mb/s, scalable to multiple inputs at that speed, making use of processors and special hardware that are available today. To avoid storing large quantities of data, the architecture routes data packets by examining routing information in the initial cell of the packet and routing subsequent cells as they arrive rather than waiting until the complete packet has arrived. It is capable of handling packets that have been multiplexed at the SAR sublayer using AAL Type 3/4 and, with minor modifications, could also handle Type 5 traffic. Arguments are also presented for the use of AAL Type 5 for the direct connectionless service     

Hardware/software co-design of the Stanford FLASH multiprocessor

Hardware/software co-design is a methodology for solving design problems in systems with processors or embedded controllers where the design requirements mandate a functionality and performance level for the system, independent of the hardware and software boundary. In addition to the challenges of functional correctness and total system performance, design time is often a critical factor. To design MAGIC, the programmable memory and communication controller for the Stanford FLASH multiprocessor, the authors employed a hardware/software co-design methodology. This methodology allowed them to concurrently design the hardware and software thereby reducing design time while simultaneously ensuring that the design would meet ambitious performance goals. Serializing the hardware and software design would have lengthened the design time and significantly increased the amount of redesign when the tradeoffs between the hardware and software implementations became clear late in the design process. The co-design approach led them to build a series of hierarchical simulators that allowed them to begin design verification early and to reduce the level of effort required to ensure a functional design