CMOS current steering logic for low-voltage mixed-signal integratedcircuits

A quiet logic family-complementary metal-oxide-semiconductor (CMOS) current steering logic (CSL)-has been developed for use in low-voltage mixed-signal integrated circuits. Compared to a CMOS static logic gate with its output range of ΔV_logic≈V_dd , a CSL gate swings only ΔV_logic≈V_T+0.25 V because the constant current supplied by the PMOS load device is steered to ground through either an NMOS diode-connected device or switching network. Owing to the constant current, digital switching noise is 100× smaller than in static logic. Another useful feature which can be used to calibrate CSL speed against process, temperature, and voltage variations is propagation delay that is approximately constant versus supply voltage and linear with bias current. Several CSL circuits have been fabricated using 0.8 and 1.2 μm high-V_T n-well CMOS processes. Two self-loaded 39-stage ring oscillators fabricated using the 1.2 μm process (1.2 V power supply) exhibited power-delay products of 12 and 70 fJ with average propagation delays of 0.4 and 0.7 ns, respectively. High-V_T and low-V_T CSL ALU's were operational at V _dd≈=0.70 V and V_dd≈0.40 V, respectively     

High-performance 0.10-μm CMOS devices operating at roomtemperature

The authors have fabricated 0.10-μm gate-length CMOS devices that operate with high speed at room temperature. Electron-beam lithography was used to define 0.10-μm polysilicon gate patterns. Surface-channel type p- and n-channel MOSFETs were fabricated using an LDD structure combined with a self-aligned TiSi₂ process. Channel doping was optimized so as to suppress punchthrough as well as to realize high transconductance and low drain junction capacitance. The fabricated 0.10-μm CMOS devices have exhibited high transconductance as well as a well-suppressed band-to-band tunneling current, although the short-channel effect occurred somewhat. The operation of a 0.10-μm gate-length CMOS ring oscillator has been demonstrated. The operation speed was 27.7 ps/gate for 2.5 V at room temperature, which is the fastest CMOS switching ever reported     

U-grooved SIT CMOS technology with 3 fJ and 49 ps (7 mW, 350 fJ)operation

Static induction transistor (SIT) CMOS is analyzed by a circuit simulation method. According to the results, the propagation delay time of the SIT CMOS could be represented as the ratio of the load capacitance to the transconductance. The U-grooved structure plays an important role in the fabrication of MOS SIT with large transconductance and small parasitic capacitance. U-grooved SIT CMOS has been fabricated by anisotropic plasma etching, and its switching speed has been evaluated by a 31-stage ring oscillator. A minimum ρ-τ product of 3 fJ/gate has been obtained for a design rule of 1-μm channel length. A minimum propagation delay time of 49 ps/gate has also been obtained at a dissipation power of 7 mW/gate, which corresponds to a ρ-τ product of 350 fJ/gate     

A high performance super self-aligned 3 V/5 V BiCMOS technologywith extremely low parasitics for low-power mixed-signal applications

A high performance BiCMOS technology, BEST2 (Bipolar Enhanced super Self-aligned Technology) designed for supporting low-power multiGHz mixed-signal applications is presented. Process modules to produce low parasitic device structures are described. The developed BiCMOS process implemented with 1 μm design rules (0.5 μm as one nesting tolerance) has achieved f_l and f_max for npn bipolar (A_e=1×2 μm²) of 23 GHz and 24 GHz at V_ce=3 V, respectively, with BV_ceo⩾5.5 volts, and βV_A product of 2400. Typical measured ECL gate delay is 48 ps/37 ps per stage (A_e=1×2 μm² ; 500 mV swing) at 0.6 mA/2.1 mA switching currents, and CMOS gate delay (gate oxide=125 Å, L_eff=0.6 μm; V_th,nch =0.45 V; V_th,pch=-0.45 V) 70 ps/stage. A BiCMOS phase-locked-loop (emitter width=1 μm; gate L_eff=0.7 μm) has achieved 6 GHz operation at 2 V power supply with total power consumption of 60 mW     

0.25 μm gate length CMOS devices for cryogenic operation

Under cryogenic operation, a low V_th realizes a high speed performance at a greatly reduced power-supply voltage, which is the most attractive feature of Cryo-CMOS. It is very important in sub-0.25 μm Cryo-CMOS devices to reconcile the miniaturization and the low V_th. Double implanted MOSFET's technology was employed to achieve the low V_th while maintaining the short channel effects immunity. We have investigated both the DC characteristics and the speed performance of 0.25 μm gate length CMOS devices for cryogenic operation. The measured transconductances in the saturation region were 600 mS/mm for 0.2 μm gate length n-MOSFET's and 310 mS/mm for 0.25 μm gate length p-MOSFET's at 80 K. The propagation delay time in the fastest CMOS ring oscillator was 22.8 ps at V_dd=1 V at 80 K. The high speed performance at extremely low power-supply voltages has been experimentally demonstrated. The speed analysis suggests that the sub-l0 ps switching of Cryo-CMOS devices will be realized by reducing the parasitic capacitances and through further miniaturization down to 0.1 μm gate length or below     

The design and characterization of nonoverlapping superself-aligned BiCMOS technology

An optimal device structure for integrating bipolar and CMOS is described. Process design and device performance are discussed. Both the vertical n-p-n and MOS devices have non-overlapping super self-aligned (NOVA) structures. The base-collector and source/drain junction capacitances are significantly reduced. This structure allows complete silicidation of active polysilicon electrodes, cutting down the parasitic resistances of source, drain, and extrinsic base. The critical gate and emitter regions are protected from direct reactive ion etching exposure and damage. All shallow junctions are contacted by polysilicon electrodes which suppress silicide-induced leakage. An arsenic buried layer minimizes collector resistance and collector-substrate capacitance. A novel selective epitaxy capping technique suppresses lateral autodoping from the arsenic buried layer. Fully recessed oxide with polysilicon buffer layer is used to achieve a low defect density device isolation. CMOS with L_eff=1.1 μm and W _n/W_p=10 μm/10 μm exhibits averaged ring oscillator delay of 128 ps/stage. An n-p-n transistor with f_T, of 14 GHz and low-power emitter-coupled logic ring oscillator with a delay of 97 ps/stage have been fabricated     

Cutoff frequency and propagation delay time of 1.5-nm gate oxideCMOS

The high-frequency AC characteristics of 1.5-nm direct-tunneling gate SiO₂ CMOS are described. Very high cutoff frequencies of 170 GHz and 235 GHz were obtained for 0.08-μm and 0.06-μm gate length nMOSFETs at room temperature. Cutoff frequency of 65 GHz was obtained for 0.15-μm gate length pMOSFETs using 1.5-nm gate SiO₂ for the first time. The normal oscillations of the 1.5-nm gate SiO₂ CMOS ring oscillators were also confirmed. In addition, this paper investigates the cutoff frequency and propagation delay time in recent small-geometry CMOS and discusses the effect of gate oxide thinning. The importance of reducing the gate oxide thickness in the direct-tunneling regime is discussed for sub-0.1-μm gate length CMOS in terms of high-frequency, high-speed operation     

A 4.2-ps ECL ring-oscillator in a 285-GHz fMAX SiGetechnology

This letter reports on the room temperature operation of a conventional SiGe bipolar ECL ring oscillator with a minimum stage delay of 4.2 ps for ~250 mV single ended voltage swing. To our knowledge, this is the lowest reported delay for a gate fabricated using transistor devices. The circuit uses 0.12 × 2 μm² emitter size SiGe n-p-n transistors with a room temperature f_T of 207 GHz and f_MAX (unilateral gain extrapolation) of 285 GHz. The ring oscillator was studied as a function of various device and circuit parameters and it was found that minimum delay is more dependent on the parasitic resistance and capacitance in the n-p-n device than on pure transit time across the device     

Process integration and device performance of a submicrometerBiCMOS with 16-GHz ft double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n⁺ buried layer, and n-channel MOSFETs were built in a p-well on a p⁺ buried layer. Deep trenches with depths of 4 μm and widths of 1 μm isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C_L=0 pF and 300 ps for C_L=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 μm were maintained at almost the same ratio     

Deep-submicrometer CMOS technology with reoxidized or annealednitrided-oxide gate dielectrics prepared by rapid thermalprocessing

Deep submicrometer CMOSFETs with re-annealed nitride-oxide gate dielectrics have been demonstrated to satisfy 3.3-V operation, unlike conventional oxide FETs. The 1/4-μm re-annealed nitrided-oxide CMOS devices achieve (1) an improved saturation transconductance g _m of ~250 μS/μm for n-FETs together with acceptably small degradation in p-FET g_m resulting in a CMOS gate delay time of 55 ps/stage comparable or superior to the device/circuit performance of oxide FETs, and (2) device lifetimes improved by ~100 times to exceed 10 years with respect to both ON- and OFF-state hot-carrier reliability for n-FETs as well as gate-dielectric integrity together with unchanged p-FET hot-carrier reliability, all at 3.3-V operation. To achieve these CMOS performance/reliability improvements, both a light nitridation and subsequent re-annealing in O ₂ (reoxidation) or in N₂ (inert-annealing) are found to be crucial     

On the SiO2-based gate-dielectric scaling limit forlow-standby power applications in the context of a 0.13 μm CMOS logictechnology

This paper describes a leading-edge 0.13 μm low-leakage CMOS logic technology. To achieve competitive off-state leakage current (I _off) and gate delay (T_d) performance at operating voltages (V_cc) of 1.5 V and 1.2 V, devices with 0.11 μm nominal gate length (L_g-nom) and various gate-oxide thicknesses (T_ox) were fabricated and studied. The results show that low power and memory applications are limited to oxides not thinner than 21.4 Å in order to keep acceptable off-state power consumption at V_cc=1.2 V. Specifically, two different device designs are introduced here. One design named LP (T_ox=26 Å) is targeted for V_cc=1.5 V with worst case I_off <10 pA/μm and nominal gate delay 24 ps/gate. Another design, named LP1 (T_ox=22 Å) is targeted for V_cc =1.2 V with worst case I_off<20 pA/μm and nominal gate delay 27 ps/gate. This work demonstrates n/pMOSFETs with excellent 520/210 and 390/160 μA/μm nominal drive currents at V_cc for LP and LP1, respectively. Process capability for low-power applications is demonstrated using a CMOS 6T-SRAM with 2.43 μm² cell size. In addition, intrinsic gate-oxide TDDB tests of LP1 (T _ox=22 Å) demonstrate that gate oxide reliability far exceeding 10 years is achieved for both n/pMOSFETs at T=125°C and V _cc=1.5 V     

High-speed BiCMOS technology with a buried twin well structure

A buried twin well and polysilicon emitter structure is developed for high-speed BiCMOS VLSI's. A bipolar transistor of high cutoff frequency (fT= 4 GHz) and small size (500 µm²) has been fabricated on the same chip with a standard 2-µm CMOS, without degrading the device characteristics of the MOSFET. Latchup immunity is improved due to the low well resistance of the buried layer. The well triggering current is a 0.5-1.0 order of magnitude higher than that of a standard n-well CMOS. To evaluate the utility of this technology, a 15-stage ring oscillator of the 2NAND BiCMOS gate is fabricated. The gate has a 0.71-ns propagation delay time and 0.25-mW power dissipation at 0.85-pF loading capacitance and 4-MHz operation. Drive ability is 0.24 ns/pF, which is 2.5 times larger than that of the equal-area CMOS gate.     

High-performance dual-gate CMOS utilizing a novel self-alignedpocket implantation (SPI) technology

A self-aligned pocket implantation (SPI) technology is discussed. This technology features a localized pocket implantation using the gate and drain electrodes (TiSi₂ film) as well as self-aligned masks. The gate polysilicon is patterned by KrF excimer laser lithography. The measured minimum gate length L_g (the physical gate length) is 0.21 μm for both N- and P-MOSFETs. A newly developed photoresist was used to achieve less than quarter-micrometer patterns. This process provides high punchthrough resistance and high current driving capability even in such a short channel length. The subthreshold slope of the 0.21-μm gate length is 76 mV/dec for N-MOSFETs and 83 mV/dec for P-MOSFETs. The SPI technology maintains a low impurity concentration in the well (less than 5×10 ¹⁶ cm^-3). The drain junction capacitance is decreased by 36% for N-MOSFETs and by 41% for P-MOSFETs, compared to conventional LDD devices, which results in high-speed circuit operation. The delay time per stage of a 51-stage dual-gate CMOS ring oscillator is 50 ps with a supply voltage of 3.3 V and a gate length of 0.36 μm, and 40 ps with a supply voltage of 2.5 V and a gate length of 0.21 μm     

TFSOI complementary BiCMOS technology for low power applications

A Thin-Film-Silicon-On-Insulator Complementary BiCMOS (TFSOI CBiCMOS) technology has been developed for low power applications. The technology is based on a manufacturable, near-fully-depleted 0.5 μm CMOS process with the lateral bipolar devices integrated as drop-in modules for CBiCMOS circuits. The near-fully-depleted CMOS device design minimizes sensitivity to silicon thickness variation while maintaining the benefits of SOI devices. The bipolar device structure emphasizes use of a silicided polysilicon base contact to reduce base resistance and minimize current crowding effects. A split-oxide spacer integration allows independent control of the bipolar base width and emitter contact spacing. Excellent low power performance is demonstrated through low current ECL and low voltage, low power CMOS circuits. A 70 ps ECL gate delay at a gate current of 20 μA is achieved. This represents a factor of 3 improvement over bulk trench-isolated double-polysilicon self-aligned bipolar circuits. Similarly, CMOS gate delay shows a factor of 2 improvement over bulk silicon at a power supply voltage of 3.3 V. Finally, a 460 μW 1 GHz prescaler circuit is demonstrated using this technology     

Current drive enhancement by using high-permittivity gate insulatorin SOI MOSFET's and its limitation

Speed enhancement effects by using a high-permittivity gate insulator in SOI MOSFETs and its limitation were investigated by a two-dimensional device simulator and circuit simulator. The SOI structure is suitable to have excellent current drive by using a high-permittivity gate insulator. Although the gate capacitance increases as a function of its dielectric constant, the current drive does not increase proportionally due to the inversion capacitance. According to the simulation results of the delay time, when the pulse waveforms driven by a CMOS inverter are propagated through 1 mm-long interconnects, the delay time significantly reduces at a dielectric constant value of around 25 (Ta₂O₅). Thus, it is worthwhile using Ta₂O₅ for gate insulator to achieve high-speed operation. Furthermore, the reduction of source parasitic series resistance is a key issue to realize the highest current drive by using a high-permittivity gate insulator in SOI MOSFET     

A new model of switching operation in fully depleted ultrathin-filmCMOS/SIMOX

An analysis is made of the switching performances of fabricated ultrathin-film submicrometer-gate CMOS/SIMOX ring oscillators. A time-dependent gate capacitance model is proposed to explain the switching operation mechanism. It is found that reducing the gate capacitance by full depletion of the body silicon dramatically improves the propagation delay time of CMOS/SIMOX     

Experimental confirmation of an accurate CMOS gate delay model forgate oxide and voltage scaling

MOSFET's and CMOS ring oscillators with gate oxide thicknesses from 2.58 nm to 5.7 nm and effective channel lengths down to 0.21 μm have been studied at voltages from 1.5 V to 3.3 V. Physical and electrical measurement of gate oxide thicknesses are compared. Ring oscillators' load capacitance is characterized through dynamic current measurement. An accurate model of CMOS gate delay is compared with measurement data. It shows that the dependence of gate propagation delay on gate oxide, channel length, and voltage scaling can be predicted     

Fully depleted CMOS/SOI device design guidelines for low-powerapplications

We report the fully depleted (FD) CMOS/SOI device design guidelines for low-power applications. Optimal technology, device and circuit parameters are derived and compared with bulk CMOS based design. The differences and similarities are summarized. Device design guidelines using devices with L=0.1 μm for FDSOI low-power applications are presented using an empirical drain saturation current model fitted to experimental data. The model is verified in the deep-submicron regime by two-dimensional (2-D) simulation. For L=0.1 μm FDSOI low-power technology, optimum speed and lower-power occurs at V_dd=3V_th and V_dd=1.5 V_th, respectively. Optimum buried oxide thickness is found to be between 300 and 400 nm for low-power applications. Optimum transistor sizing is when the driver device capacitance is 0.3 times the total load capacitance. Similarly optimum gate oxide thickness is when the driver device gate capacitance is 0.2-0.6 times the total load capacitance for performance and 0.1-0.2 for low-power, respectively. Finally optimum stage ratio for driving large loads is around 2-4 for both high-performance and low-power     

Experimental high performance sub-0.1 μm channel nMOSFET's

Very high performance sub-0.1 μm channel nMOSFET's are fabricated with 35 Å gate oxide and shallow source-drain extensions. An 8.8-ps/stage delay at V_dd=1.5 V is recorded from a 0.08 μm channel nMOS ring oscillator at 85 K. The room temperature delay is 11.3 ps/stage. These are the fastest switching speeds reported to date for any silicon devices at these temperatures. Cutoff frequencies (f_T) of a 0.08 μm channel device are 93 GHz at 300 K, and 119 GHz at 85 K, respectively. Record saturation transconductances, 740 mS/mm at 300 K and 1040 mS/mm at 85 K, are obtained from a 0.05 μm channel device. Good subthreshold characteristics are achieved for 0.09 μm channel devices with a source-drain halo process     

0.10 μm graded InGaAs channel InP HEMT with 305 GHzfT and 340 GHz fmax

We report here 305 GHz f_T, 340 GHz f_max, and 1550 mS/mm extrinsic g_m from a 0.10 μm In_xGa _1-xAs/In_0.62Al_0.48As/InP HEMT with x graded from 0.60 to 0.80. This device has the highest f_T yet reported for a 0.10 μm gate length and the highest combination of f _T and f_max reported for any three-terminal device. This performance is achieved by using a graded-channel design which simultaneously increases the effective indium composition of the channel while optimizing channel thickness