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随着半导体工艺的发展,片上系统(System-on-Chip, SoC)内部集成的不同功能IP(Intellectual Property)核越来越多。各IP核通过总线方式连接,多核同时抢占总线很大地制约了片上系统的性能。高效的总线仲裁器可以解决多核抢占总线引起的冲突和竞争问题,提升片上系统性能。该文提出一种改进的高速彩票总线仲裁器。使用4相双轨协议代替时钟实现彩票抽取机制以防止彩票丢弃,采用异步流水线交叉并行的工作方式以提升工作速度。在NINP(NonIdling and NonPreemptive)模型下通过65 nm CMOS工艺的Xilinx Virtex5板级验证,相比经典彩票仲裁器和动态自适应彩票仲裁器,具有更好的带宽分配功能,有效避免撑死和饿死现象,工作速度提高49.2%以上,具有一定的功耗优势,适用于有速度要求的多核片上系统。 相似文献
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ATM信元总线交换技术及其应用的研究 总被引:1,自引:0,他引:1
文章分析了信元总线型ATM交换技术的特点与应用范围,研究了这一交换方式的工作机制以及总线争用仲裁、总线寻址、交换路由控制等关键技术等问题。最后给出了一种信元总线交换的典型应用。 相似文献
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为了满足基于嵌入式内核的MCU芯片对于内部总线系统的设计需求,分析了嵌入式内核的对外的AHB总线接口特性,提出一种兼顾效率和可复用性的MCU芯片内部总线架构。该架构符合AHB总线规范,支持多个主控器同时访问不同的从设备。采用灵活的仲裁机制解决访问冲突。本文设计MCU总线架构应用于一款工业控制类MCU芯片,完成了FPGA原型验证、流片和样片测试。 相似文献
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高效能,低功耗DDR2控制器的硬件实现 总被引:1,自引:0,他引:1
随着SoC芯片内部总线带宽的需求增加,内存控制器的吞吐性能受到诸多挑战。针对提升带宽性能的问题,可以从两个方面考虑,一个办法是将内存控制器直接跟芯片内部几个主要占用带宽的模块连接,还要能够对多个通道进行智能仲裁,让他们的沟通不必经过内部的AMBA总线,甚至设计者可以利用高效能的AXI总线来加快SoC的模块之间的数据传输。另一个办法就是分析DDR2SDRAM的特性后设计出带有命令调度能力的控制器来减少读写次数,自然就能够降低SoC芯片的功耗,为了节能的考虑还要设计自动省电机制。本文为研究DDR2SDRAM控制器性能的提升提供良好的思路。 相似文献
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基于Verilog HDL语言的CAN总线控制器设计及验证 总被引:2,自引:2,他引:0
在此利用Verilog HDL设计了一款CAN总线控制器,首先根据协议把整个CAN总线控制器划分为接口逻辑管理、寄存器逻辑和CAN核心模块3个模块,然后用Verilog HDL硬件描述语言设计了各个功能模块,并使用Modelsim软件对各个模块的功能进行了仿真,最后使用FPGA芯片对设计的CAN总线控制器验证,并连接了一个包含该FPGA CAN总线控制器的4节点CAN总线网络。测试结果表明所设计的CAN总线控制器能够完成设定的功能。 相似文献
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Young-Hee Kim Jae-Yoon Sim Hong June Park Jae-Ik Doh Kun-Woo Park Hyun-Woong Chung Jong-Hoon Oh Choon-Sik Oh Seung-Han Ahn 《Solid-State Circuits, IEEE Journal of》1997,32(1):79-85
The occasional power-on latch-up phenomenon of DRAM modules with a data bus shared by multiple DRAM chips on different modules was investigated and the circuit techniques for latch-up prevention were presented. Through HSPICE simulations and measurements, the latch-up triggering source was identified-to be the excessive voltage drop at the n-well pick-up of the CMOS transmission gate of read data latch circuit due to the short-circuit current which flows when the bus contention occurs during power-on. By extracting the HSPICE Gummel-Poon model parameters of the parasitic bipolar transistors of DRAM chips from the measured I-V and C-V data, HSPICE simulations were performed for the power-on latch-up phenomenon of DRAM chips. Good agreements were achieved between measured and simulated voltage waveforms. In order to prevent the power-on latch-up even when the control signals (RAS, GAS) do not track with the power supply, two circuit techniques were presented to solve the problem. One is to replace the CMOS transmission gate by a CMOS tristate inverter in the DRAM chip design and the other is to start the CAS-BEPORE-RAS (CBR) refresh cycle during power-on and thus disable all the Dout buffers of DRAM chips during the initial power-on period 相似文献
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基于C8051F040的高性能CAN总线节点模块设计 总被引:2,自引:0,他引:2
经过分析CAN总线节点的功能,提出了CAN总线节点模块设计方案,介绍了典型C8051F040的CAN总线网络结构和CAN控制器结构,在硬件电路设计部分中,对模块实现原理及设计要点进行了详细的介绍,软件部分阐述了CAN总线节点模块的固件程序。给出了以此芯片为核心的CAN总线节点模块的应用层软件。设计的CAN总线节点模块功能强、性能高效,目前已经运用于工业现场使用的测量系统中。 相似文献
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Chao H.J. Byeong-Seog Choe Jin-Soo Park Uzun N. 《Selected Areas in Communications, IEEE Journal on》1997,15(5):830-843
Describes a new architecture for a multicast ATM switch scalable from a few tens to a few thousands of input ports. The switch, called the Abacus switch, has a nonblocking switch fabric followed by small switch modules at the output ports. It has buffers at input and output ports. Cell replication, cell routing, output contention resolution, and cell addressing are all performed in a distributed way so that it can be scaled up to thousands of input and output ports. A novel algorithm has been proposed to resolve output port contention while achieving input buffers sharing, fairness among the input ports, and call splitting for multicasting. The channel-grouping mechanism is also adopted in the switch to reduce the hardware complexity and improve the switch's throughput, while the cell sequence integrity is preserved. The switch can also handle multiple priority traffic by routing cells according to their priority levels. The performance study of the Abacus switch in throughput, average cell delay, and cell loss rate is presented. A key ASIC chip for building the Abacus switch, called the ARC (ATM routing and concentration) chip, contains a two-dimensional array (32×32) of switch elements that are arranged in a crossbar structure. It provides the flexibility of configuring the chip into different group sizes to accommodate different ATM switch sizes. The ARC chip has been designed and fabricated using 0.8 μm CMOS technology and tested to operate correctly at 240 MHz 相似文献
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给出了一种以8032微处理器为核、配备了FPGA(现场可编程门阵列)的双核芯片E5CSoC(可配置系统芯片)实现HDLC(高级数据链路控制)逻辑的方法,该方法利用片上的CSL(可配置系统逻辑)实现HDLC的帧结构和相关控制模块,并利用片内总线和片内集成的DMA(直接存储器存取)通道实现CSL和MCU(单片机)的数据交换,从而完成整个HDLC功能。该方法相对于专用芯片或FPGA实现表现出突出的灵活性、高效性,且集成度高、功耗小。 相似文献
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介绍一种基于PCI总线的高速信号处理器系统,讨论PCI总线控制器9054的性能及与TMSC6203B芯片扩展总线的接口,最后给出该系统的一个应用实例. 相似文献