一种基于CPLD的可编程FV变换电路

文章介绍了一种可编程的频率电压变换电路(F/V),将频率信号通过复杂可编程逻辑器件(CPLD)变换为与频率成正比的脉宽信号,脉宽信号控制模拟开关对基准电压信号进行斩波,斩波信号经低通滤波后输出直流电压信号。     

采用GaN HEMT的可调窄脉冲激光器驱动电路

为实现纳秒级的输出光脉宽,使用GaN HEMT作为激光器放电回路的开关管。由于GaN HMET的栅极总电荷小,提出使用小尺寸的GaN HEMT建立驱动电路的输入级,响应控制信号,控制放电回路开关管。搭建电路驱动860 nm激光器,并进行测试。放电回路电源电压为12 V,测试结果显示,最大输出光脉宽8.8 ns对应大于8 W的峰值功率,输出最小光脉宽为4 ns。为实现更大的脉宽可调范围,设计另一款电路并测试。该电路实现输出光脉宽大于8.4 ns可调,在电源电压20 V、输入信号脉宽100 ns的条件下,输出光峰值功率可达46 W。电路尺寸分别为10 mm×6 mm和13 mm×11 mm,为实现进一步小型化,对设计的电路提出了集成方法。提出的电路结构简单、容易实现集成且成本低,为窄脉冲激光器驱动电路的设计提供了新的思路。     

新颖的电压型有源箝位正激控制IC-LM5027

LM5027脉宽调制器包含了很多新的技术特色,除去基本的有源箝位正激电路的常规功能之外,增加了三个输出信号之间的时间延迟调节,从而可以更好地实现低EMI、高效率的功率变换,经验证明具有很好的实用性。     

TS-10B中波发射机脉宽调试电位器故障3例

上海市广播科学研究所生产的TS - 10B全固态中波广播发射机 ,采用脉冲宽度调制。此机性能优越 ,故障率极低 ,在我台使用了 6年 ,从未出现过大的故障 ,但是由于脉宽调试电位器质量问题出现 3次故障 ,在这里介绍如下。1　脉宽调试电路工作原理脉宽调试电路如图 1所示。图 1　脉宽调试电路脉宽调试电路由脉冲宽度调节电路和功率状态显示电路组成。正常功率状态时 ,带开关电位器R147的开关处于断开状态 ,+ 15V电压经R68、R147的中心点加到VD12的负端 ,使VD12截止 ,脉冲宽度调节电路不起作用 ,满功率输出 ,同时 +15V电压经R147的下端、R60…     

一种简易电压时间变换器

本文介绍一种简易的将电压变换成时间间隔,再转换成数字量的实用电路,它可以用于各种数字式仪表中. 电路原理框图如图1所示,其中由两级单稳电路组成电压时间变换器的变换电路.但这里的单稳电路和通常的单稳电路有所不同,通常的单稳电路的脉宽T是由时间常数RC决定的,而这里的单稳电路的脉     

固态LTD的脉宽叠加技术仿真

针对脉冲电磁场生物医学应用中所需求的高电压大电流宽范围脉冲问题,文中采用脉冲叠加的方案设计了一种长脉宽固态直线型变压器驱动源(Linear Transformer Driver, LTD)。该LTD脉冲发生器为了突破脉冲变压器伏秒积限制下的脉宽范围,采用并联叠加的方式增加输出脉宽。设计了脉冲变压器的复位电路,提高了LTD输出脉冲占空比,能够实现最少支路LTD的多次脉冲叠加。通过Pspice搭建仿真电路模型进行仿真实验,结果表明在单匝脉冲变压器伏秒积为146 V·ms的情况下,实现单级电压为300 V,脉宽为1.6μs的脉冲输出,为其原伏秒积的3倍,且所提方案能够通过增加叠加脉冲个数来实现更宽范围的脉冲延长。     

简单实用的湿度监控仪

通常用的湿度传感器都是电压、电流输出类型,因此对湿度的检测一般都需要先通过毫伏放大器,将微弱输入信号给予放大,然后经过模数转换芯片,将模拟信号转换为数字信号,再送给计算机去进行处理。本文介绍一种阻抗输出薄膜式湿度传感器的湿度监控仪,是利用湿度传感器、电容、与非门构成单稳态电路,将湿度的变化所相应的阻抗值变化变换为单稳态电路输出的脉宽变化,然后由单片微机对脉宽进行计数,变换成了数字量的变化。这种湿度监控仪具有简单、经济的特点。由于它将单片微型计算机MCS-51的8031作为控制部件,这就使本仪器具有抗干扰能力强、可靠性高、体积小等特点。因此本仪器具有一定的推广使用价值。我们使用的湿度传感器是广泛应用于气象部门,放于气球中测量室外大气中空气湿度的肠衣薄膜式湿     

QKD系统中相位调制器驱动电路设计

相位调制器是量子密钥分发系统中不可缺少的调制器件,其输出调制信号的脉宽影响量子比特误码率.本文提出一种利用高速高频模拟开关实现相位调制器驱动电路的设计方法,仿真结果显示驱动电路输出电压脉冲脉宽可低于10ns,并能很好地应用到量子密钥分发实验系统中,从理论及实验上对实验方案的可行性及可靠性进行了验证.     

夏普7P CK1机芯选台电路 下

(四)调谐电压的产生微处理器IX0933CE内设有调谐电压数据数/模(D/A)转换电路。它将中央运算器最后运算所得的数字信号通过D/A电路转换成脉宽调制信号。通过积分变换电路输出高频调谐器所需的模拟调谐电压。 D/A转换电路由一个14位锁存器和一个14位脉宽调制器等单元组成,它是一组系数乘法器。在一定的周期内,输出的脉冲数等于锁存的二进制数。14位D/A变换电路用作分频时,最大分频系数为2~(14)(16384),分频系数的大小受14位数码的控制。作为D/A变换器的系数乘法器,既可以分频,也可以将分频后的各脉冲进行叠加。IC1002脚33、34     

脉冲宽度调制（PWM）器件的测试

PWM器件概述 1.PWM器件的出现 PWM器件是随着开关电源的发展和半导体集成技术的发展而出现的。 开关电源是一种高频电源变换电路,它采用开关器件来控制未经稳压的直流输入电源,配合相应的滤波线路,产生稳定的直流输出。输出直流电压的高低取决于开关器件工作的脉冲占空比。在早期,人们根据开关电源的工作原理,利用分立器件设计开关电源中的脉宽调     

Toward nonlinear wave digital filters

The wave digital filter (WDF) theory provides us with a systematic methodology for building digital models of analog filters through the discretization of their individual circuit components. In some situations, WDF principles can also be successfully used for modeling circuits in which a nonlinear circuit element is present under mild conditions on its characteristic. We propose an extension of the classic WDF principles, which allows us to considerably extend the class of nonlinear elements that can be modeled in the wave digital domain. The method we propose is based on a new class of waves that can be chosen in such a may that incorporates the intrinsic dynamics of a nonlinear element into a new class of dynamic multiport adaptors. This family of junctions represents a generalization of the concept of “mutator” in the analog nonlinear circuit theory because it allows us to treat a nonlinear dynamic element as if it were instantaneous (resistive)     

Investigations on the correlation between IC-conducted emission and chip-level power supply current

This work deals with the control by design of digital integrated circuits conducted emission. In particular, it describes a technique to correlate the conducted emission of a digital integrated circuit (IC) with the power supply currents absorbed by its building blocks. Such a correlation allows one to derive the maximum allowable limits of current spectra at chip level in order to fulfill IC-conducted emission specifications.     

CMOS power retriever for UHF RFID tags

A power retrieving circuit for a UHF RFID passive tag is proposed. The circuit is implemented with a 0.18 mum standard digital technology, and allows the empowering of the tag at more than 5 m from a 500 mW ERP interrogator.     

Analogue VLSI morphological image processing circuit

An analogue VLSI circuit that performs morphological image processing operations on the focal plane is presented. The circuit has been fabricated using a standard digital CMOS process. We exploit the parallelism of morphological image processing operations by using the massively parallel architecture of analogue VLSI arrays, achieving both high-speed and low-power computation. The analogue circuit presented computes the grey-scale morphological operation of dilation. This system also allows for programmability of the structuring element used in the dilation operation     

10 /spl Omega/ 370 V high voltage switches for line circuit application

The authors describe the integration of 8 high-voltage switches together with their low-voltage polygate CMOS control logic in an 18-pin package, the HVX chip. This custom IC is intended to be used as a switching cross-point between the subscriber line and circuit equipment in digital telephony. The high-voltage DMOS is processed in a dielectrically isolated substrate, and allows the switches to have both terminals floating with respect to the low-voltage circuitry. A novel control circuit guarantees that the switch status will be defined under all circumstances.     

Static logic state analysis by TLS on powered logic circuits: Three case studies for suspected stuck-at failure modes

Thermal Laser Stimulation (TLS) for static logic state analysis is applied to failure analysis. Three case studies of analyses of the digital logic in an automotive Application Specific Integrated Circuit (ASIC) are discussed. By analyzing the logic states of the circuit we were able to identify the mechanism and localize the site of irregular behavior non-destructively, both for a stuck-at fault and two weak interconnects. The approach measures the power supply current while applying TLS to the device back side. This allows an extremely high analysis coverage, because every transistor is connected to the power supply, making this method a universal tool for every digital circuit failure analysis (FA) workflow, because the gained understanding of the fault allows to replace multiple steps of alternative FA techniques by only a single technique, reducing time and cost for successful FA.     

Frequency and Phase Estimation for Coherent QPSK Transmission With Unlocked DFB Lasers

This letter presents a hardware-efficient frequency estimator and an advanced phase estimation algorithm capable of tracking the phase noise of a 10-GBaud optical quadrature phase-shift-keying transmission system with standard distributed- feedback lasers in the presence of a frequency mismatch up to 1.2 GHz. This algorithm allows us to implement a digital coherent receiver without an analog frequency control circuit.      

Undergraduate digital laboratories

Digital circuits are rapidly replacing analog circuits in many areas of electrical engineering. The undergraduate curriculum in electrical engineering has reflected these changes by including more course work in the digital area. The availability of low cost integrated circuit logic elements and minicomputers has made it possible to provide a digital system laboratory program that allows the student to undertake the design of realistic digital systems. This paper discusses the organization of such a laboratory program and the facilities needed to carry out this program.     

A 1200 Bit/s QPSK full duplex modem

An NMOS integrated circuit is described that provides all the modulation, demodulation-filtering, and data-buffering functions for a 1200-b/s full-duplex voice-band modem. This modem is compatible with the Bell 212A modem, the Racal-Vadic 2400 modem, and the CCITT V.22 recommendation. All of the modems, options, and alternatives supported by these modems are also supported by the integrated circuit. The integrated circuit uses switched-capacitor signal processing circuit technology. This technique uses charge storage on-ratioed capacitors and allows the design of filters, amplifiers, automatic gain control elements, voltage-controlled oscillators, Hilbert filters, phase-locked loops, and a fully adaptive equalizer to be implemented on the same integrated circuit as the digital functions, which include the clock generation circuits and the transmit and receive buffers. Performance measurements show that the IC meets the bit error rate standard at 12-dB signal-to-noise ratio.     

A 24-b 50-ns digital image signal processor

A 50-ns digital image signal processor (DISP)-an image/video application-specific VLSI chip-is discussed. This chip integrates 538 K transistors and dissipates 1.4 W at a 40-MHz clock. It is based on a 24-b fixed-point architecture with a five-stage pipeline. The DISP features a real-time processing capability realized by an enhanced parallel architecture, video-oriented data processing functions, and an instruction cycle time that is typically 35 ns, and 50 ns at worst. This 50-ns cycle time allows the DISP to execute mor than 60-million operations per second (MOPS). High-density 1.0-μm CMOS technology allows numerous on-chip features, including specified resources optimized for image processing. This allows a flexible hardware implementation of various algorithms for picture coding. Several circuit design techniques that are intended to attain a fast instruction cycle are reviewed, including distributed instruction decoding and a hierarchical clocking circuit. The LSI has been designed by the extensive use of a cell-based design method. The processor incorporates a sophisticated testing function compatible with a cell-based design environment