A lateral silicon-on-insulator bipolar transistor with a self-aligned base contact

A novel lateral bipolar transistor structure in silicon-on-insulator (SOI) is presented. The structure allows for a minimum geometry base width yet still provides for a metal contact to the entire base region. Fabricated transistors exhibit a base resistance of less than 20 Ω.     

Latch-back-free self-aligned power MOSFET structure with silicidedsource and body contact

A self-aligned vertical double-diffused power MOSFET structure with a very small source region formed by outdiffusion of phosphorous from the sidewall phosphosilicate glass (PSG) is proposed. The proposed structure eliminates the latch-back phenomena and also reduces the chip area. The first experimental results of the proposed structure fabricated with the mask set for a conventional device show latch-back-free I-V characteristics     

A DRAM compatible Cu contact using self-aligned Ta-silicide and Ta-barrier

As an alternative to W contacts currently used in MOSFETs for DRAM, Cu contacts using self-aligned Ta-silicide and Ta-based barrier were studied experimentally. The silicidation of PVD Ta layers was studied first on 300 mm blanket Si wafers. The developed method was applied to patterned wafers in the contacts, that land on poly gate and active areas of NMOS, with a sequence including the PVD of Ta, a silicidation annealing, a Ta-based Cu diffusion barrier and a Cu seed for plating the Cu plug. X-ray diffraction (XRD), X-ray reflection (XRR) and sheet resistance tests of the blanket wafers show that a Ta layer of about 10 nm reacts with Si substrate and forms TaSi₂ at 650 °C in a reducing ambient. Cross-sectional SEM observation reveals that the selected processing flow fills the 90 nm contacts. Top-view SEM observation on the samples after 420 °C sintering demonstrates that the Cu diffusion barrier is effective. I_on-I_off curves of the devices show a performance for NMOS comparable to the reference samples which use Ni(Pt)Si and the same barrier and Cu contacts, indicating that the stack of the barrier/TaSi₂/p-type Si has a contact resistance comparable to the barrier/Ni(Pt)Si/p-type Si.     

High yielding self-aligned contact process for a 0.150-μm DRAMtechnology

This paper describes improvements in the self-aligned contact process for 0.150 μm and 0.175 μm technology generations. Using a dynamic random access memory cell layout, we show that self-aligned contacts can be formed at 0.175 μm ground rules and beyond by using a C₄F₈-CH₂F₂ chemistry. With the improved etch selectivity, gate cap nitride thickness can be reduced, resulting in a smaller aspect ratio for the gate etch, borophosphosilicate glass fill, and contact etch. With a rectangular contact, the area can be increased and the process windows for lithography and etch are improved. The process window for lithography increases by up to 40%, the aspect ratio for the etch and the contact fill is less, and the sensitivity to misalignment is reduced. The combination of rectangular contacts and C₄F₈-CH ₂F₂ chemistry greatly enhances the product yield     

Source—Drain contact resistance in CMOS with self-aligned TiSi2

The contact resistance between TiSi2and n⁺-p⁺source-drain in CMOS is studied for a variety of junction profiles and silicide thicknesses. It is shown that the measured contact resistance is consistent with the transmission-line model for electrically long contacts. The contact contribution to the total device series resistance can be significant if excessive silicon is consumed during silicide formation. Contact resistivities of 3 × 10^-7and 1 × 10^-6Ω . cm²can be obtained for 0.15-0.20-µm-deep arsenic and boron junctions, respectively, if the interface doping concentration is kept at 1 × 10²⁰/cm³. Furthermore, low-temperature measurements show that the contact resistivity is nearly constant from 300 to 77 K, as would be expected from a tunneling-dominated current transport at the TiSi2-n⁺and TiSi2-P⁺interfaces.     

Bipolar integrated Kelvin test structure for contact resistancemeasurement of self-aligned implantations

A Kelvin contact resistance test structure has been developed for accurate measurement of highly-doped, shallow n⁺ and p⁺ implantations, which are self-aligned to the contact window. Here the structure has been integrated, without additional processing, in a 30 GHz washed-emitter-base n-p-n bipolar process, for the purpose of monitoring the emitter contact resistance. Diffusion taps to the emitter have been made with the phosphorus collector-plug implantation. Phosphorus evaporation from the contact window during the anneal step and the low sheet resistance of the collector-plug implantation, together with the overall design of the test structure, assure a very accurate determination of the emitter contact resistance even in situations where complete junction isolation of the diffusion taps is not directly possible. Results are presented for the optimization of the emitter anneal cycle with respect to the emitter contact resistance     

A self-aligned CoSi2interconnection and contact technology for VLSI applications

Cobalt silicide is investigated in view of possible application in a self-aligned technology. Extremely smooth, highly conductive CoSi2films are obtained using rapid thermal processing for silicide formation starting from deposited cobalt layers (on Si). The phase formation is studied by XRD and RBS. No lateral silicide formation is observed at contact edges. The influence of Si consumption and dopant behavior on diode performance is studied. Shallow arsenic (0.15 µm deep) and boron (0.3 µm deep) junctions are successfully silicided. Very low contact resistances are obtained between the silicide and n+ and p+ regions. MOS transistors were fabricated with CoSi2on the source, drain, and gate. An increase in current driving capability is noticed while no degradation of other electrical parameters due to the silicide processing steps is observed. At some critical points, comparison is made with the TiSi2process.     

An all-implanted, self-aligned, GaAs JFET with a nonalloyedW/p+-GaAs ohmic gate contact

We describe a self-aligned, refractory metal gate contact, enhancement mode, GaAs junction field effect transistor (JFET) where all impurity doping was done by ion implantation. Processing conditions are presented for realizing a high gate turn-on voltage (~1.0 V at 1 mA/mm of gate current) relative to GaAs MESFET's. The high gate turn-on voltage is the result of optimizing the p⁺-gate implant and anneal to achieve a nonalloyed ohmic contact between the implanted p⁺-GaAs and the sputter deposited tungsten gate contact. Initial nominally 1.0 μm×50 μm n-JFET's have a transconductance of 85 mS/mm and f_t of 11.4 GHz     

Fully self-aligned tri-layer a-Si:H thin-film transistors withdeposited doped contact layer

We demonstrate a new self-aligned TFT process for hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs). Two backside exposure photolithography steps are used to fabricate fully self-aligned tri-layer TFTs with deposited n⁺ contacts. Since no critical data alignment is required, this simple process is well suited to fabrication of short channel TFTs. We have fabricated fully self-aligned tri-layer a-Si:H TFTs with excellent device performance, and contact overlaps <1 μm. For a 20-μm channel length TFT with an a-Si:H thickness of 13 nm, the linear region (V_DS=0.1 V) and saturation region (V_DS=25 V) extrinsic mobility values are both 1.2 cm²/V-s, the off currents are <1 pA, and the on/off current ratio is >10⁷     

Single-spatial-mode semiconductor VCSELs with a nonplanar upper dielectric DBR

Single-spatial-mode semiconductor vertical-cavity surface-emitting lasers (VCSELs) with a non-planar upper (output) dielectric distributed Bragg reflector (DBR) for the 850 nm spectral region are fabricated. The suggested design provides stable single-mode generation in the entire range of working currents, limited by overheating of the active region. Devices with intracavity contacts and a comparatively large current-aperture diameter (5–6 μm) exhibit single-mode lasing at a wavelength of 840–845 nm in the continuous-wave mode at room temperature with threshold currents of 1.2–1.3 mA, a differential efficiency of 0.5–0.55 mW mA^?1, and anoutput power of up to 2 mW.     

Suppression of the floating-body effect in poly-Si thin-film transistors with self-aligned Schottky barrier source and ohmic body contact structure

In this letter, we developed a new self-aligned Schottky barrier source and ohmic body contact (SSOB) method that can effectively suppress the floating-body effect in poly-Si thin-film transistors (TFTs). Experimental results show that the SSOB-TFTs give higher output resistance, less threshold voltage variation, improved subthreshold characteristics, and larger breakdown voltage compared with conventional TFTs. The characteristics of the SSOB-TFTs are suitable for high-performance driving TFTs with a high output resistance and large breakdown voltage.     

微结构垂直腔面发射激光器的设计

具有高功率、单横模工作特性的垂直腔激光器(VCSEL)将会极大地扩展VCSEL激光器的应用领域,具备此性能的VCSEL激光器除了能增强它在短距离通信及光存储网络的应用之外,还将成为长距离光通信以及光传感系统里重要的器件.然而对于传统的VCSEL激光器,高功率和单横模工作特性很难同时获得,这是因为高功率输出通常将会增大输出孔径,大的输出孔径则会带来多横模振荡.文中通过在P-DBR层中引入纳米微结构,设计了一种能同时提供高功率、单横模输出的VCSEL激光器.这种新型的VCSEL激光器通过采用光子带隙的波导结构,使得设计的激光器在大输出孔径(直径达12 μm)时仍然保持单横模工作.     

Charge-coupled structures with self-aligned submicron gaps

A technique for fabricating charge-coupled devices with submicron gaps is described. The method relies on a "shadowing" effect produced by oblique deposition of the metal in an otherwise standard vacuum evaporation process. The biggest advantage of the technique is its extreme simplicity, particularly for one-dimensional CCD structures. The feasibility of the technique has been demonstrated for two-and three-phase devices; the two-phase structure was a 32-bit shift register which has been operated at up to 10 MHz. With some additional processing, the technique can be used to make bidirectional CCD arrays as required in area imagers and serpentine shift registers.     

Laser removal of molded flashes from a leadframe heatsink surface

Epoxy residues on a leadframe heatsink surface of a molded integrated circuit package are a major concern for the subsequent solder plating process. Studies using a pulsed green laser to remove the epoxy residues from precoated copper-based leadframes were carried out. Effects of the laser beam mode profile and process variables on the effectiveness of residue removal and surface morphology of the heatsink were investigated. Ring marks that appeared on the laser-irradiated area were analyzed by secondary ion mass spectroscopy to determine the depth profiles of the layered structures. Calculations were carried out to estimate the temperature rise in the surface due to the laser irradiation. It is concluded that laser deflashing can be a process suitable for production uses.     

A novel SOI lateral-power MOSFET with a self-aligned drift region

In this letter, a novel drift-region self-aligned SOI lateral-power MOSFET using a partial exposure technique is proposed and demonstrated for RF power amplifier applications. The drift self-aligned structure was achieved using a simple process and without the need of an additional mask. Furthermore, the drift length can be controlled conveniently using different layout designs. The fabricated SOI power device has a breakdown voltage of over 20 V. Using a 0.7-/spl mu/m nonsilicide technology, the cutoff frequency (f/sub t/) and maximum oscillation frequency (f/sub max/) of the device are 10.1 and 13.7 GHz, respectively.     

Inverted thin-film transistors with a simple self-aligned lightlydoped drain structure

The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L_ch. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L_ch, L_LDD, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of ~1.25 μA at 5 V and a leakage current of ~0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is ~7×10⁶     

Design and evaluation of fundamental-mode and polarization-stabilized VCSELs with a subwavelength surface grating

We demonstrate 850-nm oxide-confined vertical-cavity surface-emitting lasers (VCSELs) with a locally etched subwavelength surface grating that are single-mode and polarization stable from threshold up to thermal roll-over, reaching /spl sim/4 mW of output power. The side-mode suppression ratio (SMSR) is >30 dB and the orthogonal polarization suppression ratio (OPSR) is /spl sim/20 dB. Moreover, no distortion of the far-field beam profile is observed as a result of the surface grating. Our numerical calculations show that a carefully designed VCSEL can have a high simultaneous mode and polarization selectivity without a significant increase in loss for the favored fundamental mode with polarization state perpendicular to the grating lines. This indicates characteristics such as threshold current and resonance frequency will not be notably degraded. The calculations also show a low sensitivity to variations in grating etch depth and duty cycle, which relaxes fabrication tolerances. In our experimental parametric study, where the oxide aperture diameter, surface grating diameter, and grating duty cycle were varied, the combined mode and polarization selection was investigated. For an optimum combination of oxide aperture and surface grating diameters of 4.5 and 2.5 /spl mu/m, respectively, the device is found to be single-mode and polarization stable for a broad range of grating duty cycles, from 55% to 75%, with only a small variation in other laser performances, which is in line with theory.     

Bipolar transistor with self-aligned lateral profile

This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-poly-refractory metal emitter stack to reduce the emitter resistance, a high-performance and potentially high-yield device structure can be obtained. The device structure can be adapted to a CMOS or merged bipolar-CMOS process and can also be easily optimized for analog applications.     

Stripe-geometry laser with in-situ ohmic contact and self-aligned native surface oxide mask for current isolation prepared by molecular beam epitaxy

A simple stripe-geometry laser is prepared by molecular beam epitaxy with an in-situ ohmic contact stripe and self-aligned native surface oxide mask for current isolation. The thresholds are about 70 mA for 5 ?m-wide and 380 ?m-long stripes. The light/current characteristics are linear up to ?8?10 mW/mirror with a spontaneous emission level at threshold of ?0.3 mW/mirror. The temperature coefficient T0 measured for one wafer is as high as 255 K.