A 5‐GHz energy‐efficient tunable pulse generator for ultra‐wideband applications using a variable attenuator for pulse shaping

A new energy‐efficient tunable pulse generator is presented in this paper using 0.13‐µm CMOS technology for short‐range high‐data‐rate 3.1–10.6 GHz ultra‐wideband applications. A ring oscillator consisting of current‐starved CMOS inverters is quickly switched on and off for the duration of the pulse, and the amplitude envelope is shaped with a variable passive CMOS attenuator. The variable passive attenuator is controlled using an impulse that is created by a low‐power glitch generator (CMOS NOR gate). The glitch generator combines the falling edge of the clock and its delayed inverse, allowing the duration of the impulse to be changed over a wide range (500–900 ps) by varying the delay between the edges. The pulses generated with this technique can provide a sharp frequency roll off with high out‐of‐band rejection to help meet the Federal Communications Commission mask. The entire circuit operates in switched mode with a low average power consumption of less than 3.8 mW at 910 MHz pulse repetition frequency or below 4.2 pJ of energy per pulse. It occupies a total area of 725 × 600 µm² including bonding pads and decoupling capacitors, and the active circuit area is only 360 × 200 µm². Copyright © 2011 John Wiley & Sons, Ltd.     

A proposal for high‐performance CCII‐based analogue CMOS design

A novel fully differential CMOS second‐generation current conveyor (CCII) topology is presented. It can be considered as a universal fully differential programmable active element. The circuit operates in moderate inversion region, and features high linearity over a wide input range. Current gain between terminals X and Z can be continuously tuned in a wide range. These features are essential to extend the utilization of CCII‐based circuits to high‐performance VLSI applications. Analogue design based on this new cell is illustrated by various examples. The proposed CCII has been fabricated in a 0.5‐µm CMOS technology and its main performance characteristics have been measured. They are in good agreement with theory and demonstrate that operation in moderate inversion can lead to distortion levels much lower than those achieved in strong inversion. Experimental results for a Tow–Thomas biquadratic filter fabricated on the same chip are also presented, showing continuous frequency tuning in more than a decade. Copyright © 2005 John Wiley & Sons, Ltd.     

A 1–6 GHz analog radio frequency power driver in 90 nm complementary metal‐oxide semiconductor technology for wireless applications

One of the most challenging subsystems for integrated radio frequency (RF) complementary metal‐oxide semiconductor (CMOS) solutions is the power amplifier. A 1–6 GHz RF power driver (RFPD) in 90 nm CMOS technology is presented, which receives signals from on‐chip RF signal chain components at ?12 dBm power levels and produces a 0 dBm signal to on‐chip or off‐chip 50 Ω loads. A unique unit cell design is developed for the RFPD to offset issues associated with very wide multi‐fingered transistors. The RF driver was fabricated as a stand‐alone sub‐circuit on a 90 nm CMOS die with other sub‐circuits. Experimental tests confirmed that the on‐chip RFPD operates up to 6 GHz and is able to drive 50 Ω loads to the desired 0 dBm power level. Spur free dynamic range exceeded 70 dB. The measured power gain was 11.6 dB at 3 GHz. The measured 1 dB compression point and input third‐order intercept point (IIP3) were ?4.7 dBm and ?0.5 dBm, respectively. Also, included are modeling, simulation, and measured results addressing issues associated with interfacing the die to a package with pinouts and the package to a printed circuit test fixture. The simulations were made through direct current (DC), alternating current (AC), and transient analysis with Cadence Analog Design Environment. The stability was also verified on the basis of phase margin simulations from extracted circuit net‐lists. Copyright © 2013 John Wiley & Sons, Ltd.     

A study of parallel tuner with voltage‐dependent capacitance

A study of varactor tuned LC circuits is presented. Nonlinear time domain circuit differential equation is rewritten in terms of phase plane variables, which can then be solved in closed form. General expressions are derived, which are applicable to any capacitance–voltage relationship. Two types of circuit structures, namely single‐ended and balanced, with MOS diodes as the variable capacitance elements, are specifically considered. The nature of the voltage waveforms across the two circuits is determined by phase plane plots. Variation of voltage with time is calculated numerically. It is shown that the voltage waveform for the single‐ended circuit is asymmetric, with higher harmonics present. Furthermore, the fundamental resonant frequency is dependent on amplitude of oscillation and could decrease to 94% of its small signal value for large voltage swings. Near 34% control over frequency is calculated, for a bias voltage range of 8 to 1. On the other hand, the balanced structure results in symmetric voltage waveform, with negligible harmonic content. Dependence of frequency on amplitude is weak, only decreasing to 98% of its small signal value, for the largest swings. The tuning range is marginally improved by the balanced structure. The results are compared with those obtained from Fourier‐based calculations and experimental data in literature, and good agreement is obtained. Copyright © 2011 John Wiley & Sons, Ltd.     

A 0.75‐V, 4‐μW, 15‐ppm/°C, 190 °C temperature range,voltage reference

A low‐voltage, low‐power, low‐area, wide‐temperature‐range CMOS voltage reference is presented. The proposed reference circuit achieves a measured temperature drift of 15 ppm/°C for an extremely wide temperature range of 190 °C (?60 to 130 °C) while consuming only 4 μW at 0.75 V. It performs a high‐order curvature correction of the reference voltage while consisting of only CMOS transistors operating in subthreshold and polysilicon resistors, without utilizing any diodes or external components such as compensating capacitors. A trade‐off of this circuit topology, in its current form, is the high line sensitivity. The design was fabricated using TowerJazz semiconductor's 0.18‐µm standard CMOS technology and occupies an area of 0.039 mm². The proposed reference circuit is suitable for high‐precision, low‐energy‐budget applications, such as mobile systems, wearable electronics, and energy harvesting systems. Copyright © 2015 John Wiley & Sons, Ltd.     

A 5‐MHz AT‐cut quartz crystal oscillating circuit functioning in 350 nA

An oscillating circuit functioning at ultra low power (350 nA) for a 5‐MHz AT‐cut quartz crystal oscillator was investigated. This circuit has a resistance between the power terminal of the CMOS‐IC and the power supply, and another between the earth terminal of the CMOS‐IC and the ground (GND). These resistances discourage an inrush of current, and set a gain (g_m) necessary for oscillating the circuit at minimum. The developed circuit is quite simple, but enables driving at once‐unthinkable, low power (below 1 µA). © 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A CCII‐based wide frequency range square waveform generator

In this paper, we propose a novel current‐mode solution suitable for the square waveform generation. The designed oscillator, which utilizes only two positive second‐generation current conveyors as active blocks, six resistors and a capacitor, is based on a current differentiation, instead of voltage integration, typical of developed solutions both in voltage‐mode and in current‐mode approaches, so avoiding circuit limitations due to the node saturation effects. The proposed circuit has been designed, as an integrated solution at transistor level, in a standard CMOS technology, with low‐voltage (± 1V) and low‐power (430µW) characteristics. Simulation results have confirmed the good circuit behaviour, also for working temperature drifts, showing good linearity in a wide oscillation frequency range, which can be independently adjusted through either capacitive (in the range pF ? µF) or resistive (in the range M Ω–G Ω) external passive components. Waiting for the chip fabrication, preliminary measurements have been performed using a laboratory breadboard employing the CCII with AD844 commercial component and sample capacitors and resistors. The experimental results have shown good agreement with both simulations and theoretical expectations. Copyright © 2011 John Wiley & Sons, Ltd.     

Bandwidth extension,linearity enhancement,and cost reduction techniques for continuous‐time channel‐select filters

Achieving a wide bandwidth in a conventional active‐RC filter requires large power consumption and is often accompanied by significant performance degradation. In this paper, a new structure to implement active‐RC continuous‐time filters and also a new frequency compensation scheme for the operational amplifiers that are the main building blocks of active‐RC filters are proposed. Exploiting these techniques increases the maximum possible bandwidth with lower power consumption in comparison with the conventional architectures, reduces die area, and enhances the dynamic range. The effectiveness of these methods has been verified by analysis and simulation of the conventional and proposed filters under identical conditions. Both the analytical investigations and extensive simulation results prove that the adopted techniques improve the performance of continuous‐time filters considerably in terms of bandwidth and linearity while reducing the die area. Simulations have been carried out in a standard 90‐nm CMOS process by using Advanced Design System (ADS), and the proposed filter features 11.08‐dB spurious‐free dynamic range improvement and 5.9 times bandwidth enhancement. Also, the total on‐chip capacitance is made 2.4 times smaller by using the new biquad structure. Copyright © 2016 John Wiley & Sons, Ltd.     

LC‐active VCO for CMOS RF transceivers

A novel fully integrated CMOS LC tank VCO is presented. The LC tanks are implemented by exploiting the active circuit ‘boot‐strapped inductor’ (BSI), which behaves like a high‐quality factor inductor. Particularly, the LC tanks have been implemented by introducing a new version of the CMOS BSI circuit, which provides better versatility and design reliability. In order to verify the effectiveness of such an approach, a case study for 5–6 GHz direct‐conversion multi‐standard WLAN transceivers is presented. The VCO has been designed in a 0.35µm standard CMOS technology. The new BSI exhibits a high‐quality factor (higher than 25 over the all frequency range) and provides a high selectivity without introducing a relevant excess of noise, for a better spectral purity and a lower phase noise (PN) of the VCO. The overall VCO circuit consumes 9 mW. The VCO produces an oscillation in the tuning range from 4.91 to 5.93 GHz (nearly equal to 19%). The circuit exhibits a PN of ?129dBc/Hz at 1 MHz of frequency offset from the central frequency (5.4 GHz) and a FOM equal to 189.5 dBc/Hz at 100 kHz and 194.1 dBc/Hz at 1 MHz of frequency offset, respectively. Copyright © 2009 John Wiley & Sons, Ltd.     

CMOS high‐precision loser‐take‐all circuit

This paper presents a new current‐mode CMOS loser‐take‐all circuit. The proposed circuit consists of a basic cell that allows implementation of a multi‐input configuration by repeating the cell for each additional input. A high‐speed feedback structure is employed to determine the minimum current among the applied inputs. The significant feature of the circuit is its high accuracy and high‐speed operation. Additionally, the input dynamic range of the circuit can be efficiently controlled via the biasing current. HSPICE simulation results are presented to verify the performance of the circuit, where under a supply voltage of 2.5 V, bias current of 100 µA, and frequency of 10 MHz, the input dynamic range increases within 0–100 µA and the corresponding error remains as low as 0.4%. © 2014 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

一种单片高稳振荡器芯片设计

针对传统Pierce振荡器改进了振荡器的起振电路结构,采用负阻起振理论基于0.35μm CMOS工艺设计了一种单片高稳振荡器芯片。芯片主要包含起振电路、缓冲器电路、驱动电路、使能电路及分频器电路,输出频率范围为4 MHz^30 MHz可调,应用cohesion及Hspice软件完成了电路设计与仿真,使用Cadence软件进行了芯片的版图设计,LVS验证后完成了芯片的后仿真工作,仿真结果表明在设定的6种晶体参数下,电路在800μs时完成了起振且在tt、ff、ss 3种模式下输出平稳,该芯片能适用于无线收发信机中。     

Design and analysis of power‐CMOS‐gate‐based switched‐capacitor DC–DC converter with step‐down and step‐up modes

A unified multi‐stage power‐CMOS‐transmission‐gate‐based quasi‐switched‐capacitor (QSC) DC–DC converter is proposed to integrate both step‐down and step‐up modes all in one circuit configuration for low‐power applications. In this paper, by using power‐CMOS‐transmission‐gate as a bi‐directional switch, the various topologies for step‐down and step‐up modes can be integrated in the same circuit configuration, and the configuration does not require any inductive elements, so the IC fabrication is promising for realization. In addition, both large‐signal state‐space equation and small‐signal transfer function are derived by state‐space averaging technique, and expressed all in one unified formulation for both modes. Based on the unified model, it is all presented for control design and theoretical analysis, including steady‐state output and power, power efficiency, maximum voltage conversion ratio, maximum power efficiency, maximum output power, output voltage ripple percentage, capacitance selection, closed‐loop control and stability, etc. Finally, a multi‐stage QSC DC–DC converter with step‐down and step‐up modes is made in circuit layout by PSPICE tool, and some topics are discussed, including (1) voltage conversion, output ripple percentage, and power efficiency, (2) output robustness against source noises and (3) regulation capability of converter with loading variation. The simulated results are illustrated to show the efficacy of the unified configuration proposed. Copyright © 2003 John Wiley & Sons, Ltd.     

RF transmitter using the dual‐pulse position modulation method for low‐power smart micro‐sensing chip

This paper presents a low‐power radio frequency (RF) transmitter using dual‐pulse position modulation (DPPM) for a smart micro‐sensing chip (SMSC) with sensors and large scale integrated circuit (LSI) on the same chip. The DPPM method is presented by a fixed pulse and a variable pulse within the same time frame. The distance between the fixed pulse and the variable pulse describes the amplitude of the input signal. A modulator and a ring oscillator were designed for the RF transmitter using the DPPM method. In the modulator, the pulse width modulation (PWM) signal is generated by the intersective method, and narrow pulses are extracted at the rising and falling positions of the generated PWM signal. The designed oscillator has the function of an oscillation controller. The RF transmitter was fabricated with sensors for an SMSC by complementary metal–oxide–semiconductor (CMOS) technology. The power consumption of the fabricated modulator was 4.5 mW. The power consumption of the proposed RF transmitter was measured as 7.0–7.3 mW at an input signal of 0.8–2.5 V. The RF transmitter using the DPPM method was able to reduce the power consumption by a maximum of 50.3% compared to a transmitter using the PWM method, because in the latter the dissipated power was 8.4–14.5 mW at the same input signal. © 2012 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A 40 M–1000 MHz 77.2‐dB spurious free dynamic range CMOS RF variable gain amplifier for digital TV tuner ICs

In this paper, a 40 M–1000 MHz 77.2‐dB spurious free dynamic range (SFDR) CMOS RF variable gain amplifier (VGA) has been presented for digital TV tuner applications. The proposed RFVGA adopts a wideband operational‐amplifier‐based VGA and a wideband buffer with differential multiple gated transistor linearization method for wideband operation and high linearity. The SFDR of the proposed RFVGA is also analyzed in detail. Fabricated in a 0.13‐µm CMOS process, the RFVGA provides 31‐dB gain range with 1‐dB gain step, a minimum noise figure of 7.5 dB at a maximum gain of 27 dB, and maximum in‐band output‐referred third‐order intercept point of 27.7 dBm, while drawing an average current of 27.8 mA with a supply voltage of 3.3 V. The chip core area is 0.54 mm × 0.4 mm. Copyright © 2014 John Wiley & Sons, Ltd.     

Design criterion for high‐speed low‐power SC circuits

The settling behavior of switched‐capacitor (SC) circuits is investigated in this paper. The analysis is performed for typical SC circuits employing two‐stage Miller‐compensated operational amplifiers (op‐amps). It aims to evaluate the real effectiveness of the conventional design approach for the optimization of op‐amp settling performances. It is demonstrated that the classical strategy is quite inaccurate in typical situations in which the load capacitance to be driven by the SC circuit is small. The presented study allows a new settling optimization strategy based on an advanced circuit model to be defined. As shown by design examples in a commercial 0.35‐ µm CMOS technology, the proposed approach guarantees a significant settling time reduction with respect to the existing settling optimization strategy, especially in the presence of small capacitive loads to be driven by the SC circuit. Copyright © 2010 John Wiley & Sons, Ltd.     

一种具有高转换速率的轨对轨运算放大器

为了驱动液晶显示器背板形成不同的灰阶,设计了一种利用齐纳二极管的稳压原理,实现恒定跨导用于TFT-LCD液晶显示的片内运算放大器。采用互补差分输入级,实现了Rail-to-Rail的共模电压输入范围;一种新颖的转换速率增强结构,加快了运算放大器的响应速度;输出级采用Class AB类控制电路,并将其嵌入到求和电路中,以保证较低的噪声和失调。直流增益为101dB,单位增益带宽为13MHz,相位裕度为64°。仿真结果证明该运算放大器工作良好,其面积为500μm×380μm。     

The frequency tuning characteristics of transistor voltage‐controlled oscillators with distributed parameters

The frequency varactor tuning characteristics of voltage‐controlled oscillators (VCO) on elements with distributed parameters are analysed and presented in a generalized form. The recommendations on the choice of transmission line type, circuit and varactor parameters for the purposes of widening and linearization of the voltage frequency tuning characteristics are given. Large amounts of numerical and experimental results are performed to illustrate the theoretical assumptions. Copyright © 1999 John Wiley & Sons, Ltd.     

900 MHZ radio‐frequency identification rectifier with optimization and reusing of electro‐static discharges protections in 180 nm digital CMOS technology

Sensitivity and electro‐static discharges (ESD) protection level are crucial parameters for any Ultra High‐Frequency (UHF) power rectifier–harvester designed for radio‐frequency identification (RFID) devices. While sensitivity limits the reading range of the interrogator‐to‐tag communication link, the requirement for an adequate protection against ESD is enforced in commercial devices connected to a printed antenna. Both resistive and capacitive parasitics of the protection circuits severely affect RF performance of the device. In the paper, a rectifier for UHF RFID embedding an ESD protection for 2 kV human‐body discharge model (HBM) level is proposed. The target of a low added parasitic capacitance is achieved by adapting the protection circuit to the RFID rectifier and reusing the ESD clamp for additional functions being mandatory in a UHF RFID front end. The layout of the ESD clamp has been optimized for minimum parasitic resistance without sacrificing the protection level. Two UHF harvesters were implemented in a 180 nm digital complementary metal‐oxide semiconductor (CMOS) technology, featuring a minimum sensitivity of ?15.5 dBm with an ESD protection level of 2 kV HBM. Copyright © 2014 John Wiley & Sons, Ltd.     

Stability analysis of wideband linear bipolar varactor‐controlled oscillator with two‐coupled resonant circuits

Theoretical analysis of the stability conditions of the steady‐state operation modes and tuning bandwidth characteristics of bipolar self‐biased varactor‐controlled oscillator (VCO) with two‐coupled resonant circuits are presented. The recommendations at the choice of the circuit and varactor parameters for a linearization of the wideband tuning frequency characteristics under free‐running stable oscillation conditions are given. Highly linear octave‐band tuning operation was found to be possible using hyper‐abrupt varactors in two‐coupled resonant circuits VCO. Numerical and experimental results verify the validity of the design approach described. Copyright © 1999 John Wiley & Sons, Ltd.     

Development of radio frequency transmitters including on‐chip antenna for intelligent human sensing systems

This paper presents the essentials of the development of an integrated smart microsensor system that has been developed to monitor the motion and vital signs of humans in various environments. Integration of RF transmitter technology with complementary metal‐oxide‐semiconductor/micro electro mechanical systems (CMOS/MEMS) microsensors is required to realize wireless smart microsensors for the monitoring system. Sensors for the measurement of body temperature, perspiration, heart rate (pressure sensor), and motion (accelerometers) are candidates for integration on the wireless smart microsensor system. In this paper, the development of radio frequency transmitter (RF) that will be integrated on wireless smart microsensors is presented. A voltage controlled RF‐CMOS oscillator (VCO) has been fabricated for the 300‐MHz frequency band applications. Also, spiral inductors for an LC resonator and an integrated antenna have been realized with a CMOS‐compatible metallization process. The essential RF components have been fabricated and evaluated experimentally. The fabricated CMOS VCO showed a conversion factor from voltage to frequency of about 81 MHz/V. After matching the characteristic impedance (50 Ω) of the on‐chip integrated antenna and the VCO output, more than 5 m signal transmission from the microchip antenna has been observed. The transmitter showed remarkable improvement in transmission power efficiency by correct matching with the microchip antenna. Essential technologies of the RF transmitter for the wireless smart microsensors have been successfully developed. Also, for the 300‐MHz band application, the integrated RF transmitter, with the CMOS oscillator and the on‐chip antenna, has been successfully demonstrated for the first time. Copyright © 2007 Institute of Electrical Engineers of Japan© 2007 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.