一种基于0.18μm的同步开关输出噪声模型和仿真方法

0．18μm下,同步开关输出噪声是影响信号完整性的主要噪声之一,较大的噪声有可能导致数字系统中元件的误动。本文首先简要介绍了同步开关输出噪声的产生和特点,然后给出了一种建立仿真模型和仿真的方法,这种方法快速简便而且结果精确。最后根据仿真的结果得到了一些减小同步开关输出噪声的方案。     

分段式电流舵 D/A转换器抗di/dt噪声设计

设计了一个8位50MHzD/A转换器(DAC),采用5+3分段式电流舵差分输出结构,其中高5位采用温度计码方式译码,低3位采用二进制译码方式;从各电路模块设计结构上提高DAC抗di/dt噪声的能力;设计了一个低交叉点开关驱动电路,有效地降低了输出毛刺,减小了数字电路di/dt噪声的影响。采用VIS0.35μmCMOS工艺进行仿真,结果表明,微分非线性(DNL)和积分非线性(INL)均小于0.15LSB。     

提高晶闸管器件对di/dt的耐受能力的途径

介绍了晶闸管器件的通态电流上升率di/dt参数及其损坏晶闸管器件的机理，并进一步介绍了提高晶闸管器件的通态di/dt耐量的设计和工艺方法，及应用过程中限制晶闸管阳极电路的电流上升率，保护晶闸管器件的方法。     

kT/C Noise: Covariance Matrix Calculation of Instationary Noise in Time-Varying Systems

The voltage variance at a capacitance C with a noisy resistance in parallel is kT/C, even if the resistance is infinite. This so-called kT/C noise may dominate in switched-capacitor circuits. In this paper kT/C noise is treated analytically, using explicit and implicit notations of differential equations. The resulting algorithms can be implemented in any circuit simulator with transient analysis, including cases where there are capacitor islands without capacitive paths to ground. The general approach allows to take into account high amplifier bandwidth, slow switching and other methods to mediate kT/C noise. A numerical example shows that an extremely high amplifier bandwidth is needed to reduce kT/C noise.     

高速大功率半导体开关RSD的di/dt耐量极限值

文章由等离子体双极漂移方程和临界预充电荷条件出发,得出高速大功率半导体开关RSD的di/dt耐量表达式。从外电路和器件结构本身两方面分析了RSD的di/dt耐量的影响因素,并提出了改善di/dt耐量的措施,测试结果证明了理论分析的正确性。     

Enhanced ground bounce noise reduction in a low-leakage CMOS multiplier

In this paper, various parameters are used to reduce leakage power, leakage current and noise margin of circuits to enhance their performance. A multiplier is proposed with low-leakage current and low ground bounce noise for the microprocessor, digital signal processors (DSP) and graphics engines. The ground bounce noise problem appears when a conventional power-gating circuit transits from sleep-to-active mode. This paper discusses a reduction in leakage current in the stacking power-gating technique by three modes – sleep, active and sleep-to-active. The simulation results are performed on a 4 × 4 carry-save multiplier for leakage current, active power, leakage power and ground bounce noise, and comparison made for different nanoscales. Ground bounce noise is limited to 90%. The leakage current of the circuit is decimated up to 80% and the active power is reduced to 31%. We performed simulations using cadence virtuoso 180 and 45 nm at room temperature at various supply voltages.     

基于电源树分布RLC模型估计同步切换噪声

在超深亚微米 ( VDSM)工艺下 ,器件频繁的同步切换可在电源 /地分配网络上形成大开关电流 ,影响VLSI的可靠性和信号完整性。文中提出一种估计电源树同步切换噪声的解析方法 :利用事件驱动机制、节点重组及参数重编号技术建立切换电流传播路径 ,以二极点模型近似切换电流非线性传递过程 ,简化噪声提取程序。仿真实例表明该方法的可行性和有效性     

高水平抗辐射CMOS/SOS集成电路

本工作采用先进的全离子注入低温工艺,研制成八个高水平4000系列小规模CMOS/SOS集成电路品种,它们是SC_(4001)、SC_(4002)、SC_(4011)、SC_(4012)、SC_(4013)、SC_(4030)、SC_(4066)及SC_(4069)。这些电路除了电学参数满足相应体硅CMOS电路以外,还具有优良的抗辐照特性,其抗γ总剂量达1×10~7rad(Si),抗γ瞬态剂量率达5×10~(10)rad(Si)/s以上。 本文简要介绍CMOS/SOS器件抗γ总剂量辐照及抗γ瞬态辐照的基本考虑以及辐照实验的结果。     

CMOS射频集成电路中器件模型的研究

采用硅材料CMOS工艺制造的射频集成电路具有低功耗、低成本和容易集成的优点.文章讨论了CMOS射频集成电路设计和制造中起关键作用的MOSFET高频模型和螺旋电感模型.为了验证模型,介绍了射频集成电路中的核心模块-低噪声放大器(LNA)-的设计实例.测试结果表明,该模型具有高效、实用的特点.     

混合信号衬底耦合噪声的传播及抑制方法

介绍了衬底噪声耦合效应在不同工艺衬底中的传播,应用medici模拟了不同衬底中,噪声发生端和噪声接收端噪声在不同间距下噪声传播的情况,并从工艺和电路设计两个方面介绍了一系列抑制衬底噪声的方法。     

改进时频域混合方法分析电源分配网络同步开关噪声

对时频域混合方法加以改进用于分析电源分配网络同步开关噪声.引入修正Gram-Schmidt正交化方法实现矩阵的正交三角分解,以解决有理函数逼近构建时域宏模型中存在的病态条件数问题;同时提出一种结构简单的等效电路模型用于HSPICE电路仿真.计算实例验证了该方法的有效性.     

The total dose effects on the 1/f noise of deep submicron CMOS transistors

Using 0.18 μm CMOS transistors, the total dose effects on the 1/f noise of deep-submicron CMOS transistors are studied for the first time in mainland China. From the experimental results and the theoretic analysis, we realize that total dose radiation causes a lot of trapped positive charges in STI （shallow trench isolation） SiO2 layers, which induces a current leakage passage, increasing the 1/f noise power of CMOS transistors. In addition, we design some radiation-hardness structures on the CMOS transistors and the experimental results show that, until the total dose achieves 750 krad, the 1/f noise power of the radiation-hardness CMOS transistors remains unchanged, which proves our conclusion.     

混合集成双频段低噪声放大器的设计

本文主要讨论双频段微波低噪声放大器的设计技术,介绍实现双频段的设计方法及工艺和制作方法.利用这些方法,我们在850±120MHz和3000±120MHz二个频段上实现了低噪声放大.其主要技术指标如下:增益40dB±1dB,噪声系数N_F<1.5,输入驻波比ρ≤2.0,输出驻波比ρ≤1.5.     

一种混合信号集成电路衬底耦合噪声分析方法

讨论分析了混合信号集成电路衬底噪声耦合的机理,及对模拟电路性能的影响。提出了一种混合信号集成电路衬底耦合噪声分析方法,基于TSMC 0.35μm 2P4M CMOS工艺,以14位高速电流舵D/A转换器为例,给出了混合信号集成电路衬底耦合噪声分析方法的仿真结果,并与实际测试结果进行比较,证实了分析方法的可信性。     

Noise Attributes of LWIR HDVIP HgCdTe Detectors

Time series and Fourier-transform data on high-density vertically integrated photodiodes (HDVIP) at 0 and 50 mV reverse bias in the dark have been studied. The detectors have a cutoff wavelength λ _c (60 K) of 10.5 μm. Examination of the detector current time series and Fourier-transform curves of these devices reveals a variety of interesting characteristics: (i) time series displaying switching between four states characteristic of random telegraph signal (RTS) noise, the noise current power spectrum having Lorentzian or double Lorentzian type characteristics, (ii) time series data exhibiting wave-like characteristics with the noise current power spectrum being 1/f ²-like at low frequencies, (iii) time series having a mean value independent of time with the noise current power spectrum being white, and (iv) time series nearly independent of time with the noise current power spectrum having 1/f characteristics. Although from a single array, the excess noise characteristics at low (mHz) frequencies were varied, most of the detectors measured fell into one of these four categories. The predominance of detectors examined had minimal excess low-frequency noise down to ~ 10 mHz. Detectors that displayed RTS noise in reverse bias were repeatable under subsequent measurement. However, when measured at zero bias, the same detectors exhibited no RTS noise, the noise current power spectrum being white in nature.     

CMOS读出电路中的噪声及抑制

CMOS读出电路中的噪声严重地制约了读出电路的动态范围,进而影响到焦平面阵列甚至成像系统的性能.文章对读出电路中KTC噪声、1/f噪声以及固定图形噪声的成因及抑制技术进行了分析和讨论,并给出了仿真结果.     

Placement of Substrate Contacts to Minimize Substrate Noise in Mixed-Signal Integrated Circuits

The placement of substrate contacts in epi and non-epi technologies is analyzed in order to control and reduce the substrate noise amplitude and spreading. The choice of small or large substrate contacts or rings for each of the two major technologies is highlighted. Design guidelines for placing substrate contacts so as to improve the noise immunity of digital circuits in mixed-signal smart-power systems are also presented.     

多层封装基板中同步开关噪声研究

文章以栅格阵列封装(land grid array,LGA)模型为研究对象,分析了多层封装基板中的同步开关噪声(simultaneous switching noise,SSN)问题。首先利用频域仿真工具PowerSI得到了键合线和信号布线的S参数模型。然后通过在电路仿真工具HSPICE中加载封装结构的S参数模型和驱动器模型来仿真同步开关噪声。最后在设计中选取在多层基板上添加去耦电容的方式来减小同步开关噪声。仿真结果表明,通过在本LGA多层基板设计中添加110pF容值的去耦电容,可以较好地减少同步开关噪声,满足设计要求。     

深亚微米薄膜CMOS／SOI电路的集成器件线路模拟

开发了适用于薄膜亚微米、深亚微米ＣＭＯＳ／ＳＯＩ电路的集成器件线路模拟软件，该模拟软件采用集成数值模型，将薄膜ＳＯＩ器件的数值模拟与电路模拟有机地结合在一起，实现了薄膜亚微米、深亚微米ＣＭＯＳ／ＳＯＩ电路的精确数值模拟，利用这一软件较为详细地分析了硅层厚度为５０￣４００ｎｍ、沟道长度为０．１５￣１．０ｕｍ的ＣＭＯＳ／ＳＯＩ环形振荡器电路，使我们对深亚微米薄膜ＣＭＯＳ／ＳＯＩ环振的特性及工作机理了较     

基于可靠性及噪声约束的电源/地线优化设计

电源 /地线 ( P/G)拓扑结构的优化设计是超大规模集成电路 ( VLSI)中直接影响芯片性能的一个非常重要的问题 .通过对考虑可靠性及噪声的各项约束条件的分析 ,提出了一种时间复杂度为 O( N2m)基于最小代价生成树 ( MST)和改进的 Prim算法的快速构造算法 .实验结果表明 ,该算法在满足同样的性能约束条件下能有效地减小布线面积