一种低复杂度的Log-MAP译码器结构

根据实际中Turbo译码器硬件实现的重要性,提出了一种适合于并行计算的改进Log-MAP译码算法,即在其译码计算中间参数的过程中,将具有n个输入变量的最大近似算法max*运算简化为取最大值的max运算和相关函数的计算,减少了存储量,有效实现了低复杂度的Turbo译码器的硬件结构。将此改进的算法应用于CCSDS标准和Wi MAX标准中,仿真结果表明,所提出的简化的近似算法与传统的Log-MAP算法对比,有效降低了译码复杂度和时延,而且纠错性能接近Log-MAP算法,便于实际工程应用。     

Low complexity decision-aided decoder for turbo DPSK

A new decision-aided soft a posteriori probability (APP) algorithm for iterative differential phase-shift keying (DPSK) signal demodulation/decoding in a Rayleigh flat-fading channel is presented. Compared with conventional APP algorithms for iterative DPSK, the new algorithm results in considerably lower decoding cost yet can achieve nearly the same performance     

时变信道下低复杂度解码器设计

针对组分层空时结构(GLST)提出了一种适用于时变信道的低复杂度解码器设计方案。通过“正交对”矩阵的构造,首先去除所有分组内的符号干扰,再运用递推降维矩阵求逆算法,基于组检测技术获得所有分组反射符号。与已有传统解码方案相比,新设计解码器使计算复杂度大大降低。仿真结果同时表明,不同信道时变程度及发射天线分组情况时,两类解码器在最小接收天线数配置下获得几乎一致的性能;但随信道时变或分组数目增大,两类解码器性能恶化,均可通过提高接收天线数得到补偿。     

A low complexity block turbo decoder architecture - [transactions letters]

In this letter we present a low-complexity architecture designed for the decoding of block turbo codes. In particular we simplify the implementation of Pyndiah?s algorithm by not storing any of the concurrent codewords generated by the list decoder.     

Non-core based shared tree architecture for IP multicasting

The core-based tree (CBT) has three main limitations. The selection of the core node is difficult and the traffic is concentrated near the core router. Also the CBT does not consider an optimisation of network resource utilisation. In the proposed non-core based tree (NCBT), an on-tree node is assigned to each incoming member for multicasting such that the maximum end-to-end delay and the tree costs are jointly minimised.     

可重用AVS芯片结构软硬件协同设计

根据软硬件设计思想设计一个结构划分合理的可重用的AVS视频解码器结构.通过ARM平台软件移植,然后使用ARM ESL工具对系统模块性能进行整体评估,然后根据评估结果以及硬件实现复杂度进行软硬件结构的划分,定制软硬件模块接口,从硬件扩展考虑把硬件部分设计为与H.264解码器兼容并用SystemC模拟,最后在SOC Designer 平台做协同验证及仿真.     

High-speed VLSI architecture for parallel Reed-Solomon decoder

This paper presents high-speed parallel Reed-Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber optic systems. Pipelining and parallelizing allow inputs to be received at very high fiber-optic rates and outputs to be delivered at correspondingly high rates with minimum delay. A parallel processing architecture results in speed-ups of as much as or more than 10 Gb, since the maximum achievable clock frequency is generally bounded by the critical path of the modified Euclidean algorithm block. The parallel RS decoders have been designed and implemented with the 0.13-/spl mu/m CMOS standard cell technology in a supply voltage of 1.1 V. It is suggested that a parallel RS decoder, which can keep up with optical transmission rates, i.e., 10 Gb/s and beyond, could be implemented. The proposed channel = 4 parallel RS decoder operates at a clock frequency of 770 MHz and has a data processing rate of 26.6 Gb/s.     

一种基于半闪速结构的动态比较器

模数转换器的核心是比较器,本文讨论了比较器的性能和动态比较器的工作原理、引起电荷注入、时钟馈通的原因以及如何消除,然后通过仿真图观察动态比较器的工作状态、传输时延及精度等特性。     

A new architecture for the Viterbi decoder for code rate k/n

A novel VLSI architecture is proposed for implementing a long constraint length Viterbi decoder (VD) for code rate k/n. This architecture is based on the encoding structure where k input bits are shifted into k shift registers in each cycle. The architecture is designed in a hierarchical manner by breaking the system into several levels and designing each level independently. The tasks in the design of each level range from determining the number of computation units, and the interconnection between the units, to the allocation and scheduling of operations. Additional design issues such as in-place storage of accumulated path metrics and trace back implementation of the survivor memory have also been addressed. The resulting architecture is regular, has a foldable global topology and is very flexible. It also achieves a better than linear trade-off between hardware complexity and computation time     

Low-complex processing element architecture for successive cancellation decoder

A low-complexity design architecture for implementing the Successive Cancellation (SC) decoding algorithm for polar codes is presented. Hardware design of polar decoders is accomplished using SC decoding due to the reduced intricacy of the algorithm. Merged processing element (MPE) block is the primary area occupying factor of the SC decoder as it incorporates numerous sign and magnitude conversions. Two’s complement method is typically used in the MPE block of SC decoder. In this paper, a low-complex MPE architecture with minimal two’s complement conversion is proposed. A reformulation is also applied to the merged processing elements at the final stage of SC decoder to generate two output bits at a time. The proposed merged processing element thereby reduces the hardware complexity of the SC decoder and also reduces latency by an average of 64%. An SC decoder with code length 1024 and code rate 1/2 was designed and synthesized using 45-nm CMOS technology. The implementation results of the proposed decoder display significant improvement in the Technology Scaled Normalized Throughput (TSNT) value and an average 48% reduction in hardware complexity compared to the prevalent SC decoder architectures. Compared to the conventional SC decoder, the presented method displayed a 23% reduction in area.     

On the performance/complexity tradeoff in block turbo decoder design

In this letter, tradeoffs between very large scale integration implementation complexity and performance of block turbo decoders are explored. We address low-complexity design strategies on choosing the scaling factor of the log extrinsic information and on reducing the number of hard-decision decodings during a Chase search.     

一种基于时域处理的低复杂度HACO-OFDM系统

针对计算复杂度高和误码率(BER)受限幅噪声估计精度影响的问题,提出一种低复杂度的混合非对称限幅光正交频分复用(HAC0-0FDM)系统及基于时域处理的接收解调方法,详细介绍了HAC0-0FDM系统的组成及其时域信号的结构特点,通过简单的时域信号处理实现限幅噪声消除.实验结果表明:该方案显著降低了计算复杂度;当限幅噪声...     

基于FPGA的汉明码编译码系统

讨论了汉明码编译码基本原理,并在FPGA中对汉明码编译码原理进行验证仿真,在此基础上提出扩展汉明码的概念并进行仿真。这两种设计均下载至FPGA中实现,结果证明,本设计达到了纠错检错的要求,具有一定的实践指导意义。     

Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications

This paper presents a novel multi-Gb/s multi-mode LDPC decoder architecture and efficient design techniques for gigabit wireless communications. An efficient dynamic and fixed column-shifting scheme is presented for multi-mode architectures. A novel low-complexity local switch is proposed to implement the dynamic and fixed column-shifting scheme. Furthermore, an efficient quantization method and the usage of a one׳s-complement scheme instead of a two׳s-complement scheme are explored. The proposed decoder achieves very high throughput with minimal area overhead. Post layout results using TSMC 65-nm CMOS technology shows much better throughput, as well as better area- and energy-efficiency, compared to other multi-mode LDPC decoders.     

H.264/AVC entropy decoder complexity analysis and its applications

Context-based adaptive variable length coding (CAVLC) and universal variable length coding (UVLC) are two entropy coding tools that are supported in all profiles of H.264/AVC coders. In this paper, we investigate the relationship between the bit rate and the CAVLC/UVLC decoding complexity. This relationship can help the encoder choose the best coding parameter to yield the best tradeoff between the rate, distortion, and the decoding complexity performance. A practical application of CAVLC/UVLC decoding complexity reduction is also discussed.     

Low complexity image interpolation method based on path selection

Image interpolation, the problem of producing a sequence of intermediate frames between two input images, is of significant interest. The application of image interpolation is numerous, including animation of still images, view interpolation and temporal interpolation. In this paper, we achieve an improved path-based interpolation method based on the original path-based framework, by introducing two innovative improvements. On one hand, we use optical flow to decide the direction of path, to constraint the path length and to maintain the global path coherency, which improves the efficiency significantly. On the other hand, we introduce the pixel interlacing model to obtain more accurate optical flows so that the accuracy of path selection will be improved a lot. Our improved path-based method performs as well as the original method in various interpolation applications in image quality and surpass the original method by a large scale in efficiency.     

基于噪声预测的低复杂度判决反馈均衡

针对散射通信系统多径效应严重,常用的频域非线性均衡算法复杂度过高的情况,提出了一种基于噪声预测的低复杂度判决反馈均衡方法。根据常用散射通信多径信道模型,在时延功率谱呈指数衰减的情况下,通过曲线拟合的方法预测非线性判决反馈均衡器的部分系数,从而达到降低算法复杂度的目的。仿真结果表明,所提方法不仅具有较低的复杂度,也具备良好的误码性能,在合适的阈值下,与原有算法的性能损失可控制在0.1 dB以内。     

基于频谱形状的低复杂度雷达信号分类

为解决雷达信号调制识别中存在的计算复杂度高、低信噪比环境识别准确率低和仿真数据真实度低等问题,提出了基于频谱形状的低复杂度雷达信号分类算法。对信号频谱进行归一化,按频谱采样的方法提取特征参数,训练机器学习分类模型。雷达信号源生成数据的测试结果表明,本算法对Barker码、Frank码、LFM、BPSK、QPSK调制和常规雷达信号的分类准确率大于90%(SNR≥3 dB),计算复杂度低,能适应信号参数变化,具有很好的泛化性。     

一种自适应协方差的低复杂度图像放大方法

对于图像放大技术而言,重要的就是要权衡到图像质量以及计算复杂度.传统的基于线性或三次样条插值的方法会带来图像模糊和锯齿边缘等失真,为了解决这一问题,人们提出一种基于迭代和学习的算法,但是这种方法带来了很高的计算复杂度.综合以上几点本文提出了一种基于自适应协方差的图像放大方法(adaptive covariance-based edge diffusion,ACED).该方法能很好地权衡图像放大性能和复杂度之间的关系.在这种方法中,提出了一种联合边缘判别准则,并自适应选择扩散模板来估计局部协方差系数,以高效的减少图像放大带来的失真.实验结果表明,所提出的方法在主观质量和客观质量上都有很大的提升,同时也具有较低的计算复杂度.     

低复杂度的基于迭代译码的LDPC编码方法

基于迭代译码的LDPC编码方法,是一种分两个阶段编码的方法,然而对校验矩阵的列交换以及添加新行都会增加编码所需的存储资源.文中着力于寻找低复杂度实现该编码算法的校验矩阵,首先研究了重复累积(RA)码的基于迭代译码的编码实现,然后针对802.11n[1]和802.16e[2]中一种类RA码的LDPC码,提出了另一形式的分阶段编码,可以降低编码复杂度.