A high-resolution time-to-digital converter using a three-level resolution

In this article, a three-level resolution Vernier delay line time-to-digital converter (TDC) was proposed. The proposed TDC core was based on the pseudo-differential digital architecture that made it insensitive to nMOS and pMOS transistor mismatches. It also employed a Vernier delay line (VDL) in conjunction with an asynchronous read-out circuitry. The time interval resolution was equal to the difference of delay between buffers of upper and lower chains. Then, via the extra chain included in the lower delay line, resolution was controlled and power consumption was reduced. This method led to high resolution and low power consumption. The measurement results of TDC showed a resolution of 4.5 ps, 12-bit output dynamic range, and integral nonlinearity of 1.5 least significant bits. This TDC achieved the consumption of 68.43 µW from 1.1-V supply.     

10bit 200MHz采样率具有梯度误差补偿的CMOS视频D/A转换器实现

提出了一种10bit 200MHz采样率具有梯度误差补偿的CMOS视频D/A转换器实现电路。采用分段式结构,利用层次式对称开关序列消除由热分布不均所引起的对称误差。该DAC集成在一款视频自适应均衡芯片中,整个芯片采用Charted 3.3V电压、0.35μm CMOS工艺生产制造。DAC的面积为1.26mm×0.78mm,工作在4Fsc(14.318MHz)采样频率时,其有效数据比特为9.3个,其积分非线性误差和微分非线性误差均小于±0.5LSB。     

毫米波脉冲调制功率放大器设计与实现

脉冲调制功率放大器是脉冲雷达系统的一个重要组成部分.分析了因储能电容、功放稳定电容和金丝键合组装工艺等引入的寄生参数对毫米波漏极脉冲调制功率放大器输出波形的影响,并根据分析和仿真结果设计了工程实物.测量结果表明:研制的脉冲调制功率放大器脉冲调制波形实测上升沿、下降沿均小于60 ns,最大脉冲宽度下,脉冲顶降小于10％,脉冲输出功率大于33 dBm,满足雷达系统的典型应用需求.     

DCM,FSM,dead time and width controllers for a high frequency high efficiency buck DC-DC converter over a wide load range

This paper presents a width controller,a dead time controller,a discontinuous current mode(DCM) controller and a frequency skipping modulation(FSM) controller for a high frequency high efficiency buck DC-DC converter. To improve the efficiency over a wide load range,especially at high switching frequency,the dead time controller and width controller are applied to enhance the high load efficiency,while the DCM controller and FSM controller are proposed to increase the light load efficiency.The proposed D...     

一种单端10-bit SAR ADC IP核的设计

本设计通过采用分割电容阵列对DAC进行优化,在减小了D/A转换开关消耗的能量、提高速度的基础上,实现了一款采样速度为1 MS/s的10-bit单端逐次逼近型模数转换器。使用cadence spectre工具进行仿真,仿真结果表明,设计的D/A转换器和比较器等电路满足10-bit A/D转换的要求,逐次逼近A/D转换器可以正常工作。     

10位逐次逼近型A/D转换器的芯片设计

介绍了一种10位、3M sample/s逐次逼近型A/D转换器的设计,描述了具有可变时钟电路结构的有效工作方式.该模数转换器在0.6 μ m双多晶硅、双金属层CMOS工艺上实现,芯片总面积为3.2mm2.转换器采用单5V电源供电,功耗仅为3 5mW.     

一种基于降压DC-DC转换器的高性能误差放大器设计

基于降压型DC-DC转换器的工作原理,从系统需要出发,提出一种高性能的误差放大器。该误差放大器的输入级采用偏置电流消除结构,避免其输入对基准电压产生影响;核心电路采用对称性的差分运放结构,引入正反馈结构和负反馈电阻以提高其性能,电路结构采用CSMC 0.5μm BCD工艺。仿真结果表明该误差放大器跨导为1.5 mS,共模下限可以从0开始,共模抑制比为106 dB,失调电压为208.3μV,功耗约为100μW,验证了该放大器的良好性能。     

Design and analysis of a high efficiency linear power amplifier

A high efficiency linear power amplifier is introduced based on the idea of Switch-Linear Hybrid (SLH) power conversion. The SLH power amplifier developed from the conventional class B power amplifier, while the class B configuration power unit in the SLH power amplifier is fed by a dynamic switching power supply, not the usual constant DC power supply. Thus, the efficiency of the class B configuration power unit in SLH power amplifier can be greatly improved. By combining linear power amplifier with switching power supply, the SLH power amplifier has synthetic performance of high fidelity, high efficiency and excellent dynamic characteristics. In this article, analysis of SLH power amplifier is performed, especially focusing on its linear power unit which is the core of SLH power amplifier. Design considerations are also presented parallel with the analysis. Both the theoretical analysis and experimental results verify the validity of SLH power amplifier.     

基于高摆率误差放大器的无片外电容LDO设计

为了解决无片外电容低压差线性稳压器(LDO)的瞬态响应性能较差的问题,采用跨导提高技术设计了一种高摆率的误差放大器.在误差放大器的基础上,通过电容将LDO的输出端耦合至电流镜构建瞬态增强电路,提升LDO的瞬态响应能力,且瞬态增强电路可以引入两个左半平面零点,改善环路的稳定性.同时,误差放大器采用动态偏置结构,进一步减小...     

高速A/D转换器AD7654与单片机接口电路设计

介绍了16位A/D转换器AD7654的主要特点、工作原理和工作时序,设计了AD7654与单片机的接口电路,并结合实际给出软件流程和相应的汇编源程序.     

一种带有增益提高技术的高速CMOS运算放大器设计

设计了一种用于高速ADC中的高速高增益的全差分CMOS运算放大器。主运放采用带开关电容共模反馈的折叠式共源共栅结构,利用增益提高和三支路电流基准技术实现一个可用于12~14 bit精度,100 MS/s采样频率的高速流水线（Pipelined）ADC的运放。设计基于SMIC 0.25μm CMOS工艺,在Cadence环境下对电路进行Spectre仿真。仿真结果表明,在2.5 V单电源电压下驱动2 pF负载时,运放的直流增益可达到124 dB,单位增益带宽720 MHz,转换速率高达885 V/μs,达到0.1%的稳定精度的建立时间只需4 ns,共模抑制比153 dB。     

一款小型化S频段高谐波抑制功率放大器的设计

为了确保卫星系统电磁兼容性满足要求,设计了一款应用于卫星测控通信系统的小型化S频段高谐波抑制功率放大器。通过在功放输出端设置谐波抑制网络改善了电路的谐波抑制性能。采用集总与分布参数元件相结合匹配形式,实现了电路的小型化设计。电路尺寸38.5 mm×28.2 mm。通过对功放腔体结构进行细化建模仿真,确保了功放电路的稳定性。实测结果表明,当工作频率为2.52 GHz时,功放1 dB压缩点大于31 dBm,谐波抑制度大于61 dBc,功率附加效率高于35%,1 dB带宽大于320 MHz。与国内外同类产品相比,该功放在谐波抑制性能等方面具有明显优势。     

12 bit 200 MS/s时间交织流水线A/D转换器的设计

介绍了一款应用于无线收发系统的12 bit 200 MS/s的A/D转换器(ADC).流水线型模数转换器是从中频采样到高频采样并且具有高精度的典型结构,多个流水线型模数转换器利用时间交织技术合并成一个模数转换器的构想则是复杂结构和能量利用率之间的折中选择.采用了时间交织、流水线和运算放大器共享等技术,既提高了速度和精度,也节省了功耗.同时为了减小时序失配对时间交织流水线ADC性能的影响,提出了一种对时序扭曲不敏感的采样保持电路.采用SMIC 0.13 μm CMOS工艺进行了电路设计,核心电路面积为1.6 mm×1.3 mm.测试结果表明,在采样速率为200 MS/s、模拟输入信号频率为1 MHz时,无杂散动态范围(SFDR)可以达到67.8 dB,信噪失真比(SNDR)为55.7 dB,ADC的品质因子(FoM)为1.07 pJ/conv.,而功耗为107 mW.     

单激光源布里渊光学时域放大系统的光路结构

提出了一种单激光源的布里渊光学时域放大(BOTDA)系统的光路结构,只需用到1台激光器,且扫频范围由高频微波频率(约11 GHz)降为中短波频率(MHz),节省了成本.建立了相应的实验系统,将传感光纤置于温控箱中进行实验,获取了布里渊散射信号随温度变化的实验数据.推导出传感光纤两端入射光频差恒定时布里渊散射信号与温度间...     

一种10bit双通道流水线SAR ADC设计

为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型（SAR）模数转换器（ADC）。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提出的处于第二阶段的SAR ADC由1 bit FLASH ADC和6 bit SAR ADC组成。提出的ADC由45 nm CMOS工艺制作而成,面积为0.16 mm2。ADC的微分非线性和积分非线性分别小于0.36 最低有效位（LSB）和0.67 LSB。当电源为1.1 V时,ADC的最大运行频率为260 MS/s。运行频率为230 MS/s和260 MS/s的ADC的功率消耗分别为13.9 mW和17.8 mW。     

Ka频段10 W自适应射频预失真线性化固态功放研制

射频功率放大器的特性会随信道切换、环境温度、工作状态等多种因素发生变化,为了保证功率放大器的优良工作特性,具有自适应性能的预失真系统就显得非常重要。提出了一种自适应反馈检测方法,以减小放大器输出信号的幅度失真和相位失真作为系统自适应的优化目标,采用多方向搜索优化算法对预失真系统进行优化调整,使系统始终处于最优工作状态。研制了工作于Ka频段10 W自适应射频预失真线性化固态功放原理样机,当工作温度为-40℃~+60℃时,在3 GHz的工作带宽内,三阶交调指标优于-32 dBc。测试结果表明该功放具有工作频带宽、温度适应性广等特点。     

一种低噪声高增益零中频放大器的设计与实现

文中介绍了一种低噪声的零中频放大器的设计与实现,通过选用合适的集成运算放大器芯片,完成低噪声、高增益并具备滤波效果的零中频放大器的设计.阐述了运放芯片的选择依据,电路的工作原理并使用Cadence制板软件完成了电路板的设计.实际测试结果表明,该电路工作稳定,噪声、增益、滤波特性等效果均很好.     

Design of a high performance memory using a novel architecture of double bit CAM and SRAM

A high-speed low-power novel architecture of Dual Bit Content Addressable Memory (DB-CAM) is reported in this article. A low leakage, low power and high-speed memory has been developed using the novel architecture of DB-CAM that can store 2 bits in a single CAM block and Static Random Access Memory (SRAM). Data search operation is done by using CAM cells and SRAMs are used as data storage cells. The output of SRAM cells depend on the search result of CAM cells. To make the search operation more precise a priority detector circuit has been proposed. The new architecture of DB-CAM block reduces the power consumption, transistor count and the area on chip enormously. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre (CADENCE) using standard 90?nm CMOS technology.     

Design and analysis of a flat gain and linear low noise amplifier using modified current reused structure with feedforward structure

In this paper, a Low Noise Amplifier (LNA) with the current reused topology is proposed for wideband applications. To increase input impedance matching common source with inductive degeneration and RC shunt feedback structure is used. To extend the bandwidth, inductive series peaking technique is utilized. In the next stage, two parallel structure is hired to have a high voltage gain with low power consumption in addition to improve linearity. Also, by using the self-forward-body-bias (SFBB) technique, supply voltage is reduced and as a result power consumption is decreased further. The proposed LNA exhibits the high and flat gain of 14.7–15.4 ​dB, input return loss of less than −11 ​dB and noise figure range of 2.3–4.4 ​dB from 1 ​GHz up to 8 ​GHz. It consumes 5.4 ​mW from a 1.2 ​V power supply. The achieved IIP3 range for the proposed LNA is 0 ​dBm up to +2.7 ​dBm. The proposed LNA occupies 0.45 ​mm² in 0.18-μm CMOS technology.