Laser thermal processing of amorphous silicon gates to reduce poly-depletion in CMOS devices

One major challenge in advanced CMOS technology is to have adequate dopant activation at the polycrystalline silicon (poly-Si) gate/gate oxide interface to minimize the poly-Si depletion effect. In this paper, laser thermal processing (LTP) was employed to fabricate single or dual-layer poly-Si-gated MOS capacitors with ultrathin gate oxides. Capacitance-voltage data show that the carrier concentration at the poly-Si gate/gate oxide interface increases substantially when the devices are subjected to LTP prior to a rapid thermal anneal (RTA). Thus, LTP readily reduces the poly-depletion thickness in MOS devices. For p/sup +/-gated capacitors, this is achieved with boron penetration that is equivalent to the control sample with 1000/spl deg/C, 5 s RTA (without LTP). In addition, results from secondary ion mass spectrometry indicate that the concentration of dopants near the critical gate/gate oxide interface increases significantly after a post-LTP anneal, in good agreement with the electrical data. Time-dependent dielectric breakdown studies show that the gate oxide reliability is not degraded even after LTP at high fluences.     

Suppression of boron penetration through thin gate oxides by nitrogen implantation into the gate electrode of PMOS devices

PMOS devices with different amounts of nitrogen implanted into the gate electrode before doping with BF₂ implantation and implant anneal were manufactured. The thicknesses of the gate oxides grown in dry oxygen by RTP were 4.1 down to 2.8 nm. The implant anneal was also performed by RTP. The influence of the nitrogen on the penetration of boron ions through the ultra-thin gate oxides into the channel region was investigated by electrical and SIMS measurements. Boron was effectively prevented from diffusion by high nitrogen concentrations at the polysilicon/gate oxide interface without degrading the reliability. In return, increased sheet resistivities and gate depletion have to be taken into account by high nitrogen concentrations within the polysilicon gate electrode.     

优化了栅电极溅射工艺的难熔金属栅MOS电容的性能

论述了通过优化难熔金属栅电极的溅射工艺及采用适当的退火温度修复损伤来提高3nm栅氧W/TiN叠层栅MOS电容的性能.实验选取了合适的TiN厚度来减小应力,以较小的TiN溅射率避免溅射过程对栅介质的损伤,并采用了较高的N2/Ar比率在TiN溅射过程中进一步氮化了栅介质.实验得到了高质量的C-V曲线,并成功地把Nss(表面态密度)降低到了8×1010/cm2以下,达到了与多晶硅栅MOS电容相当的水平.     

High-quality deposited gate oxide MOSFET's and the importance ofsurface preparation

The fabrication and electrical characteristics of MOSFETs incorporating thin gate oxides deposited by a modified plasma-enhanced chemical-vapor-deposition (PECVD) process are reported. The gate oxide deposition and all subsequent steps were carried out at or below 400°C. These results represent the first demonstration of near-thermal-gate oxide quality. MOSFETs fabricated using a low-temperature PECVD gate oxide process without requiring a high-temperature anneal. The ultimate performance of the deposited oxide devices is shown to be critically dependent on the degree of process induced microroughness of the starting silicon surface. Low-temperature effective mobility measurements are used to compare inversion-layer scattering mechanisms in these devices     

FGA effects on plasma-induced damage: beyond the appearances

Indispensable for manufacturing of modern CMOS technologies, plasma processes result in charging of dielectric surfaces, thus damaging the gate oxide. A forming gas annealing (FGA) step is usually done at the end of the process to passivate and/or recover this damage. We investigated this problem on thin (3.5 nm) gate oxides by using a series of stress-anneal-stress steps on devices with different level of latent damage. Our results confirm that FGA actually reduces the number of traps responsible for stress-induced leakage current (SILC) or for microbreakdown in ultrathin gate oxides, but also put in evidence that defects induced by plasma treatments and those generated by way of electrical stress feature different anneal kinetics. Further, we have identified two categories of dielectric breakdown events, whose characteristics are strongly modified by the FGA step.     

Gate oxide reliability concerns in gate-metal sputtering deposition process: an effect of low-energy large-mass ion bombardment

The effects of ion species/ion bombardment energy in sputtering deposition process on gate oxide reliability have been experimentally investigated. The use of xenon (Xe) plasma instead of argon (Ar) plasma in tantalum (Ta) film sputtering deposition for gate electrode formation makes it possible to minimize the plasma-induced gate oxide damage. The Xe plasma process exhibits 1.5 times higher breakdown field and five times higher 50%-charge-to-breakdown (Q_BD). In the gate-metal sputtering deposition process, the physical bombardment of energetic ion causes to generate hole traps in gate oxide, resulting in the lower gate oxide reliability. The simplified model providing a better understanding of the empirical relation between the gate oxide damage and the ion-bombardment energy to gate oxide in gate-metal sputtering deposition process is also presented.     

Reduction of RIE-damage by N2O-anneal of thermal gateoxide

We have investigated RIE-induced damage in MOS devices with thermal oxide as well as N₂O-annealed oxide as gate dielectrics. A systematic improvement in robustness against RIE-induced damage is seen when N₂O flow rate and/or N₂O anneal temperature are increased. We have demonstrated a N₂O anneal process at 900°C, which provides a robust SiO₂/Si interface against plasma damage and hot carrier stress     

Reduction of carrier depletion in p/sup +/ polysilicon gates using laser thermal processing

A novel laser thermal processing (LTP) technique was used to fabricate p/sup +/-gated MOS capacitors with ultrathin gate oxides. It is found that the introduction of LTP prior to the gate activation anneal increases the carrier concentration at the poly-Si gate/gate oxide interface substantially, as compared to rapid thermal anneal (RTA) alone. Thus, LTP readily reduces the poly-depletion effect in p/sup +/-poly-Si gates. This is achieved without observable gate oxide degradation or boron penetration. Secondary ion mass spectrometry analyzes show that the boron concentration near the gate/gate oxide interface increases significantly after the post-LTP anneal. A possible mechanism for this increase in carrier concentration is the diffusion of boron atoms toward the gate oxide by a complex process known as explosive crystallization.     

Evaluation of MOS devices as mechanical stress sensors

The influence of mechanical stress on metal-oxide-semiconductor (MOS) devices has been studied and analyzed for their applicability as in-situ sensors that are capable of measuring packaging induced and/or externally applied stress. Either compressive or tensile stress would alter the electrical characteristics of MOS devices in a regular pattern and that can be explained by substrate piezoresistivity. The regularity of electrical parameter variation of MOSFETs and the high sensitivity in correspondence with mechanical stress have made them very attractive as stress sensors since they may provide accurate and localized stress-state measurements. Through careful analysis, appropriate MOSFET-based sensors may be designed for proper on-site stress measurement in packaging and other stress detection applications. In addition, the mechanical stress also cause MOS devices to exhibit shorter lifetime that can be attributed to the occurrence of stress-induced charge-trapping sites in gate oxide. For MOSFETs utilized as stress sensors, the reliability issue related to mechanical stress has to be accounted and certain modification of stress-state extraction procedure will be needed to maintain valid stress measurement.     

Engineering of nitrogen profile in an ultrathin gate insulator to improve transistor performance and NBTI

During evaluation of negative bias temperature instability (NBTI) in short-channel devices, we found that using an optimized nitrogen depth profile is important in suppressing NBTI when scaling down CMOS devices. Performing the NO anneal process before oxidation yeilds good transistor performance, suppressing NBTI by 25%. When using more nitrogen to moderate gate leakage and boron penetration, in addition to the amount of nitrogen, it is important to control the depth profile of the nitrogen on the gate insulator, as our research shows that the interface peak concentration of nitrogen enhances NBTI degradation.     

Anomalous junction leakage current induced by STI dislocations andits impact on dynamic random access memory devices

As the density of dynamic random access memory (DRAM) increases up to giga-bit regime, one of the important problems is the control of the process-induced defects and damage. Although the shallow trench isolation (STI) is widely used for deep submicron devices, it has a great possibility of generating STI dislocations due to its inherently large mechanical stress and damage. When STI dislocations are located within the depletion region of pn junction, anomalous junction leakage current could flow. This junction leakage current degrades the memory cell data retention time and the standby current of DRAM. We resolved the problems from STI dislocations as follows; the crystal defects and the mechanical stress were reduced by optimizing the implantation condition and the densification temperature of trench filled high-density plasma (HDP) oxide, respectively. In addition, the residual mechanical stress before source/drain implantation was relieved through rapid thermal nitridation (RTN). By using these methods, STI dislocations were successfully clamped outside the depletion region of pn junction     

A comprehensive study of indium implantation-induced damage in deep submicrometer nMOSFET: device characterization and damage assessment

The impact of indium channel implantation on the current-voltage characteristics, gate oxide breakdown and hot-carrier reliability of deep submicrometer nMOSFETs is studied in detail. A significantly faster oxide wear-out during ramped-voltage testing and a distinctly enhanced drain current degradation during hot-carrier stressing are observed in devices with implant dose ranging from 1-2 /spl times/ 10/sup 13/ cm/sup -2/. An important generation leakage is also measured in the long-channel MOSFET, although such irregularity is normally not detected in short-channel devices owing to predominant subthreshold current. The loss in device reliability may be attributed to the generation of local amorphous regions in the channel when the implant dose exceeds 10/sup 13/ cm/sup -2/. The limited thermal budget of the subsequent gate oxidation step is generally unable to anneal out these defects, which in turn lead to the formation of local weak spots and strained Si-H bonds in the gate oxide, and dislocation loops in the channel region. This finding raises an important concern on the use of indium implantation in retrograde channel engineering, since implant doses on the order of 10/sup 13/ cm/sup -2/ are often needed for effective suppression of short-channel effects. In order to minimize the loss in device reliability, the damaged lattice would need to be restored using a dedicated thermal annealing cycle prior to gate oxidation. A good correlation between the hot-carrier stress data and the DC current-voltage (DCIV) measurement data is also presented. This makes the DCIV technique a precise, nondestructive monitor for implantation-induced damage in deep submicrometer MOSFET, via a direct measurement of the process-residue interface traps.     

Oxynitride gate dielectric grown in nitric oxide (NO): the effectof reoxidation on dielectric reliability of the active edge

Reoxidation of an oxynitride gate dielectric grown by NO anneal of thermal oxide has been studied. This process has demonstrated ~3-5X improvement of Q_BD of active edge intensive capacitors in comparison to thermal oxide, N₂O and NO oxynitride. This improvement is believed to be due to the reduction of local thinning of the gate dielectric at the field oxide edge which also reduces local build-up of positive charge near the gate electrode at the isolation edges     

Recovery and stress dynamics in bipolar transistors and MOS devices

Stress and recovery dynamics of bipolar transistors and ultra thin oxide MOS devices have been investigated. We have found that these devices can exhibit similarities in the stress dynamics. The recovery during heat treatment was also investigated and it was found that both the dynamics and the temperature dependence of the recovery were very similar for both bipolar and MOS devices. These findings indicate that the defects might be similar where bipolar current gain degradation and MOS gate oxide charging are concerned.     

Recoiled-oxygen-free processing for 1.5 nm SiON gate-dielectric insub-100-nm CMOS technology

We have developed high-quality 1.5-nm-SiON gate dielectrics using recoiled-oxygen-free processing. We found that oxygen recoiling from a sacrificial oxide during ion implantation or defects induced by recoiled oxygen change the growth mechanism of SiON gate dielectrics of less than 2 nm and degrade the controllability of film thickness, film quality, and device electrical characteristics. PMOSFETs using the recoiled-oxygen-free process and As-implantation for the channel have better controllability of gate dielectric thickness, up to one-third less gate leakage current, a hundred times more reliable TDDB characteristics, and a 20% improvement in drain current compared to the conventional process. Thus, an Si substrate without recoiled oxygen is essential in forming high-quality SiON gate dielectrics of less than 1.5 nm. In addition, we will show that anneal before SiON gate dielectric formation removes the recoiled oxygen from the Si substrate and improves controllability of the gate SiON gate dielectric thickness     

The electrical properties of HfO/sub 2/ dielectric on germanium and the substrate doping effect

MOS devices built on various germanium substrates, with chemical vapor deposited (CVD) or physical vapor deposited (PVD) HfO/sub 2/ high-/spl kappa/ dielectric and TaN gate electrode, were fabricated. The electrical properties of these devices, including the capacitance equivalent thickness (CET), gate leakage current density (J/sub g/), slow trap density (D/sub st/), breakdown voltage (V/sub bd/), capacitance-voltage (C-V) frequency dispersion, and thermal stability, are investigated. The process conditions such as surface nitridation treatment, O/sub 2/ introduction in CVD process and postdeposition anneal temperature in PVD process, exhibit significant impacts on the devices' electrical properties. The devices built on germanium substrates with different dopant types and doping concentrations show remarkable variations in electrical characteristics, revealing the role of the substrate doping in the reactions occurring at the dielectric/Ge interface, which can significantly affect the interfacial layer formation and Ge updiffusion. A possible mechanism is suggested that two competing processes (oxide growth and desorption) take place at the interface, which govern the formation of the interfacial layer. Doped p-type (Ga) and n-type (Sb) impurities may enhance the different process at the interface and cause the variations in the interfacial layer formation and so on in electrical properties. The high diffusivities of impurities and Ge atoms in Ge and the induced structural defects near the substrate surface could be one possible cause for this doping effect. As another behavior of the substrate doping effect, Ge n-MOS and p-MOS stacks show quite different C-V characteristics after high temperature postmetallization anneal treatments, which can be explained by the same mechanism.     

The effect of a post processing thermal anneal on pre-existing and stress induced electrically active defects in ultra-thin SiON dielectric layers

In this work we demonstrate the effects of a post processing high temperature anneal on the reliability of ultra-thin SiON layers fabricated into both nmos and pmos devices in terms of the initial gate leakage current, stress induced leakage current (SILC), and the time dependent dielectric breakdown behaviour. The devices under consideration were annealed at several temperatures up to 500 °C. We show that different mechanisms dominate the leakage behaviour at different temperatures by examining the relative leakage in the low voltage range. In particular for pmos devices, the emptying of electron traps induced by temperature and subsequent annealing of these traps alters the leakage current profiles significantly, dependent on anneal temperature. We show that annealing improves the time dependent dielectric breakdown (TDDB) lifetimes of nmos devices and examine the reasons for this.     

Characteristics of buried-channel pMOS devices with shallowcounter-doped layers fabricated using channel preamorphization

Channel preamorphization, which is a technique used for shallow boron counter doping of pMOSFETs to suppress short-channel effects, improves gate oxide quality in MOS capacitors with the field-edge structure. This indicates that the source of gate oxide quality degradation is located near the field oxide edge, and is eliminated in channel preamorphization process by the gettering effects of defects induced near the original amorphous/crystalline interface. The leakage current of junction diodes, on the other hand, is increased by channel preamorphization. The leakage current increases because the defects near the original amorphous/crystalline interface act as generation centers in the depletion layers. This problem will be overcome by increasing the preamorphization depth. Hot carrier immunity of pMOSFETs is improved by channel preamorphization, especially in short-channel devices     

Effect of low and high temperature anneal on process-induced damageof gate oxide

We have investigated the ability of high and low temperature anneals to repair the gate oxide damage due to simulated electrical stress caused by wafer charging resulting from plasma etching, etc. Even 800°C anneal cannot restore the stability in interface trap generation. Even 900°C anneal cannot repair the deteriorated charge-to-breakdown and oxide charge trapping. As a small consolation, the ineffectiveness of anneal in repairing the process-induced damage allows us to monitor the damages even at the end of the fabrication process     

Scaled CMOS technology using SEG isolation and buried well process

An advanced bulk CMOS technology has been developed using the selective epitaxial growth (SEG) isolation technique and buried n-well process. CMOS devices are fabricated on a selective epitaxial layer, isolated by a thick SiO2insulator over the p⁺substrate. p-channel devices are designed on buried n-wells, formed by introducing a phosphorus ion implantation into the p⁺substrate before the epitaxial growth. The use of an SiO2sidewall and square side direction is effective for defect-free selective epitaxy. The epitaxial autodoping effect from the p⁺substrate and the buried layer is estimated to be within less than 1 µm. A 20-nm-thick gate oxide and 500-nm-thick phosphorus-doped polysilicon gate electrode are used for both channel devices. Submicrometer gate CMOS operation is confirmed using the SEG isolation technique. This isolation structure, combined with the buried well, shows large latchup immunity for scaled CMOS circuits.