包含衬底电流的LDD MOSFET输出I-V特性的经验模型分析

采用双曲正切函数的经验描述方法和器件物理分析方法,建立了适用于亚微米、深亚微米的LDD MOSFET输出I-V特性解析模型,模型中重点考虑了衬底电流的作用.模拟结果与实验有很好的一致性.该解析模型计算简便,对小尺寸器件中的热载流子效应等能够提供较清晰的理论描述,因此适用于器件的优化设计及可靠性分析.     

一个带自热效应的新型LDMOS解析模型

介绍了一个带自热效应的新型LDMOS解析式模型.通过研究以阈值电压为基础的BSIM3v3模型,增加了对漂移区影响的考虑,同时,加入自热效应影响,且不用引入单独的自热网络,有效地提高了计算效率.模型中引入有物理背景的新参数来描述LDMOS特有的准饱和效应和自热效应.在计算实验中,模拟数据很好地吻合实际器件的测量数据,证明该模型适用于LDMOS功率器件在电路中的仿真.     

一个解析的适用于短沟SOIMOSFET's的高频噪声模型

提出了一个新的解析的适用于SOI MOSFET's的高频噪声模型.该模型通过耦合能量平衡方程克服了以往噪声模型所具有的缺点,并对短沟SOI器件的噪声给出精确地描述.同时,利用该模型可以容易地计算出相对于最小噪声值处的优化的栅源电压,为低噪声的电路设计提供优化的设计方向.由于该噪声模型的简单性,可以很方便地将模型植入电路模拟器如SPICE中完成电路设计.     

SiCMESFET的大信号电容解析模型

考虑4H-SiC常温下不完全离化和高饱和电子漂移速度的特点,采用载流子速度饱和理论和电荷控制理论, 结合双曲正切函数的描述方法,导出了适用于4H-SiC MESFET在射频功率应用时的大信号电容解析模型,其模拟结果与实验值有很好的一致性.该模型具有物理概念清晰且算法简单的优点, 非常适合于微波器件结构及电路的设计.     

基于RESURF理论的SOI LDMOS 耐压模型研究

对SOI LDMOS器件的击穿电压进行了研究,建立了适用于该器件的RESURF耐压模型,获得了表面电势和电场分布解析表达式,给出了SOI LDMOS器件漂移区的最优浓度,在此基础上将该模型嵌入半导体工艺模拟以及器件模拟软件(Sentaurus TCAD)中,并对SOI LDMOS器件的表面电场分布、击穿特性和I-V特性...     

SiGe基区异质结晶体管电流和频率特性的解析模型

给出了一个适用于分析SiGe基区异质结晶体管电流和频率特性的解析模型,并利用该模型分析了基区掺杂和组分均级变的SiGe异质结晶体管的电流增益、截止频率、最高振荡频率。模型中考虑了由于基区重掺杂和Ge的掺入引起的禁带窄变效应、载流子速度饱和效应。解析模型的计算结果与实验的对比证实了本模型可适用于器件的优化设计和电路的模拟。     

一个适用于极低温的宽温度范围子电路MOSFET模型

本文描述了一个适用于低温下的MOSFET子电路SPICE模型。其中引入了两个电阻用于描述冻析效应,并开发了这两个电阻的解析的行为模型。该模型在从极低温到常温的较宽的温度范围内均适用。     

InP基HBT GP大信号模型直流参数提取的研究

基于HBT特殊的物理机理及结构,将适用于BJT的GP大信号模型用于InP基HBT的研究中.通过构建误差函数,采取解析法提取了该模型中的13项SPICE直流参数.并设计了参数提取实验装置,最后将研究结果用于发射极为2μm×19μm的InP/InGaAs HBT建模中.通过对比模型仿真和器件实测的数据可以看出,本文采用的HBT GP模型准确度高,可以较好地表征实际HBT器件的直流特性.     

一个用于深亚微米电路模拟的MOSFET解析模型

本文提出了一个新的深亚微米ＭＯＳＦＥＴ模型,它计入了影响深亚微米器件工作的各种二级物理效应．模型采用一个统一的公式描述所有的器件工作区,可以保证无穷阶连续．不仅适用于数字电路,而且可用于模拟电路的设计．模型计算的结果与实测器件的结果十分一致．     

一种新的大信号射频功率器件建模方法

对小信号网络分析而言,单一的S参数已足够描述器件的特性.但对大信号网络分析而言,则需要更多的数学工具来描述器件的特性.本文采用了一个新的适用于描述大信号非线性特性的描述函数——非线性散射函数.利用非线性散射函数可以完成对大信号射频功率器件的精确建模.     

深亚微米MOSFET二维数值模拟的若干结果

对溶亚微米器件，由于工作电压下降，要求重新确定ＬＤＤ和常规ＭＯＳＦＥＴ在ＶＬＳＩ中的作用。本文从基本器件数理方程发出，对深亚微米常规及ＬＤＤ ＭＯＳＦＥＴ的器件特性、热载流子效应及短沟道效应进行了二维稳态数值模拟，指出了常规和ＬＤＤ ＭＯＳＦＥＴ各自的局限性，明确了在深亚微米ＶＬＳＩ中，ＬＤＤ仍然起主要作用。     

亚微米、深亚微米LDD MOSFET的衬底电流模型中特征长度改进的描述

建立了衬底电流模型中特征长度参数的改进描述,该参数的引入使衬底电流模型能够有效地适用于从微米尺寸到亚微米、深亚微米尺寸的LDD MOSFET.在以双曲正切函数描述的I-V特性基础上,该解析模型的运算量远低于基于数值分析的物理模型,其中提取参数的运用也大大提高了模型的精度,模拟结果与实验数据有很好的一致性.     

亚微米、深亚微米LDD MOSFET的衬底电流模型中特征长度改进的描述

建立了衬底电流模型中特征长度参数的改进描述,该参数的引入使衬底电流模型能够有效地适用于从微米尺寸到亚微米、深亚微米尺寸的LDD MOSFET.在以双曲正切函数描述的I-V特性基础上,该解析模型的运算量远低于基于数值分析的物理模型,其中提取参数的运用也大大提高了模型的精度,模拟结果与实验数据有很好的一致性.     

亚微米、深亚微米LDD MOSFET的衬底电流模型中特征长度改进的描述

建立了衬底电流模型中特征长度参数的改进描述,该参数的引入使衬底电流模型能够有效地适用于从微米尺寸到亚微米、深亚微米尺寸的L DD MOSFET.在以双曲正切函数描述的I- V特性基础上,该解析模型的运算量远低于基于数值分析的物理模型,其中提取参数的运用也大大提高了模型的精度,模拟结果与实验数据有很好的一致性.     

Hot carrier reliability improvement by utilizing phosphorus transient enhanced diffusion for input/output devices of deep submicron CMOS technology

This letter presents a deep submicron CMOS process that takes advantage of phosphorus transient enhanced diffusion (TED) to improve the hot carrier reliability of 3.3 V input/output transistors. Arsenic/phosphorus LDD nMOSFETs with and without TED are fabricated. The TED effects on a LDD junction profile, device substrate current and transconductance degradation are evaluated. Substantial substrate current reduction and hot carrier lifetime improvement for the input/output devices are attained due to a more graded n/sup -/ LDD doping profile by taking advantage of phosphorus TED.     

A new approach for characterizing structure-dependent hot-carriereffects in drain-engineered MOSFET's

In this paper, we have demonstrated successfully a new approach for evaluating the hot-carrier reliability in submicron LDD MOSFET with various drain engineering. It was developed based on an efficient charge pumping measurement technique along with a new criterion. This new criterion is based on an understanding of the interface state (N_it ) distribution, instead of substrate current or impact ionization rate, for evaluating the hot-carrier reliability of drain-engineered devices. The position of the peak N_it distribution as well as the electric field distribution is critical to the device hot-carrier reliability. From the characterized N_it spatial distribution, we found that the shape of the interface state distribution is similar to that of the electric field. Also, to suppress the spacer-induced degradation, we should keep the peak values of interface state away from the spacer region. In our studied example, for conventional LDD device, sidewall spacer is the dominant damaged region since the interface state in this region causes an additional series resistance which leads to drain current degradation. LATID device can effectively reduce hot-carrier effect since most of the interface states are generated away from the gate edge toward the channel region such that the spacer-induced resistance effect is weaker than that of LDD devices     

0.8μm LDD CMOS RELIABILITY EXPERIMENTS AND ANALYSIS

The numerical simulation of two dimensional device is conducted to describe the mechanism of the special substrate current and degradation of submicron LDD structure observed in experiments, and finally, the optimum processes for submicron LDD CMOS are proposed.     

0.8μm LDD CMOS reliability experiments and analysis

The numerical simulation of two dimensional device is conducted to describe the mechanism of the special substrate current and degradation of submicron LDD structure observed in experiments, and finally, the optimum processes for submicron LDD CMOS are proposed.     

A new 0.25-μm recessed-channel MOSFET with selectivelyhalo-doped channel and deep graded source/drain

To improve the performance and reliability of deep submicron MOS devices, a gate-recessed MOSFET (GR-MOSFET), which has a selectively halo-doped recessed channel and a deep graded source/drain formed without counterdoping, is proposed. The GR-MOS structure, which adopts a new doping concept, eliminates the tradeoff between drain-induced barrier lowering (DIBL) and hot-carrier effect, which are important to deep submicron device design. It also reduces the V_T lowering effect and the lateral electric field at the drain. A 0.25-μm GR-MOSFET with a 10-nm gate oxide has exhibited 15% higher transconductance and 10% increased saturation current at V_D=V _G=3.3 V, 1 V higher BV_DSS, and six times less substrate current compared with an LDD-MOSFET of the same device dimensions