Fabrication of Schottky barrier MOSFETs using self-assembly CoSi2 nanopatterning and spacer gate technologies

A self-assembly patterning method for generation of epitaxial CoSi₂ nanostructures was used to fabricate 50 nm channel-length MOSFETs. The transistors have either a symmetric structure with Schottky source and drain or an asymmetric structure with n⁺-source and Schottky drain. The patterning technique is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal oxidation. The strain field is generated along the edges of a mask consisting of 20 nm SiO₂ and 300 nm Si₃N₄. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. A poly-Si spacer was used as the gate contact. The asymmetric transistor was fabricated by ion implantation into the unprotected CoSi₂ layer and a subsequent out-diffusion process to form the n⁺-source. I–V characteristics of both the symmetric and asymmetric transistor structures have been investigated.     

Thin films of CoSi2 on Si1−yCy substrate layers

The reaction of Co with epitaxial Si_1−yC_y(001) films is investigated with regard to dependence on annealing temperature and C concentration y. Resistance measurements and RBS analysis reveal a small increase in the disilicide formation temperature. The electrical properties are very similar for thin CoSi₂ films grown at 650°C on Si_0.999C_0.001 and on Si. Whereas the CoSi₂ is fully polycrystalline on Si(001), partially oriented CoSi₂ has been observed on C-containing substrate layers. An increase of the number of epitaxially grown CoSi₂ crystallites has been observed with increasing C concentration.     

Elevated n+/p junctions by implant into CoSi2formed on selective epitaxy for deep submicron MOSFETs

Very shallow elevated n⁺/p junctions formed by arsenic implant into or through cobalt silicide (CoSi₂) formed on selective epitaxial layers and their application to deep submicron n-channel MOSFETs were studied for the first time. PREDICT 1.6 simulation program was employed to choose the desired implant energies and annealing thermal cycle based on theoretically predicted silicide thickness. The implanted CoSi₂ elevated junctions had low reverse current and no bias voltage dependence up to 5 V. Diffusion current dominated the junction forward current, and good ideality factors close to 1 were obtained. A nearly abrupt junction doping profile was achieved. Deep submicron n-channel MOSFETs incorporating implanted CoSi₂ elevated junctions were demonstrated. Sharp turn-off and reasonably large drain currents were achieved     

A manufacturable process to improve thermal stability of 0.25-μmcobalt silicided poly gate

A CoSi₂ salicidation process using a thin titanium capping layer is developed to improve the thermal stability of deep submicron CoSi₂/poly stacks. 50 nm CoSi₂ was uniformly formed on 0.25-μm wide poly lines. The electrical results show that the lines formed by a capping process using Ti can withstand higher thermal treatment (750° C for 30 min) without significant degradation. This work shows that the modified CoSi₂ process should be considered for 0.25-μm CMOS applications     

Field emission characteristics of CoSi2/TaN-coatedsilicon emitter tips

This work has improved the emission characteristics of Si emitter tips by coating a CoSi₂/TaN bilayer on the tips. The CoSi₂ layer was grown in situ by a reactive chemical-vapor deposition of cyclopentadienyl dicarbonyl cobalt at 650°C. The TaN was then deposited on the CoSi₂ layer at 550°C by a reactive sputtering of Ta with N as a reactive gas. The CoSi₂/TaN-coated emitters showed a lower turn-on voltage and higher emission current than the CoSi₂- or TaN-coated emitters due to the low work function by TaN and the easy transport of electron by CoSi₂ with low resistivity. The long-term emission stability of CoSi₂/TaN-coated Si emitter was as good as TaN-coated emitter     

Raman investigation of lattice defects in the CoSi2 synthesis using focused ion beam implantation

CoSi₂ layers were produced by 70 keV Co focused ion implantation into Si(111). Within a comparative study the CoSi₂ layer quality and implantation damage were investigated as a function of pixel dwell-time and substrate temperature. Irradiation damage measurements were done by micro-Raman analysis. The results suggest that the dwell-time dependence of the CoSi₂ layer formation — continuous layers for short and disrupted ones for long dwell-times — is caused by an accordant transition from crystalline to amorphous silicon.     

Suppression of cobalt silicide agglomeration using nitrogen(N2+) implantation

In this paper, the effects of nitrogen coimplantation with boron into p⁺-poly gate in PMOSFETs on the agglomeration effects of CoSi₂ are studied. The thermal stability of CoSi₂/poly-Si stacked layers can be significantly improved by using nitrogen implantation. Samples with 40-nm cobalt silicide (CoSi ₂) on 210-nm poly-Si implanted by 2×10¹⁵/cm ² N₂⁺ are thermally stable above 950°C for 30 s in N₂ ambient. If the dose of nitrogen is increased up to 6×10¹⁵/cm², the sheet resistance of CoSi₂ film is not increased at all, and TEM photographs show that the agglomeration of CoSi₂ film is completely suppressed     

Impact of nitrogen (N2+) implantation intopolysilicon gate on thermal stability of cobalt silicide formed onpolysilicon gate

A novel process which uses N₂⁺ implantation into polysilicon gates to suppress the agglomeration of CoSi₂ in polycide gated MOS devices is presented. The thermal stability of CoSi₂/polysilicon stacked layers can be dramatically improved by using N₂⁺ implantation into polysilicon. The sheet resistance of the samples without N₂⁺ implantation starts to increase after 875°C RTA for 30 s, while the sheet resistance of CoSi₂ film is not increased at all after 950 and 1000°C RTA for 30 s if the dose of nitrogen is increased up to 2×10¹⁵ cm^-2 and 6×10¹⁵ cm², respectively, and TEM photographs show that the agglomeration of CoSi₂ film is completely suppressed. It is found that the transformation to CoSi₂ from CoSi is impeded by N₂⁺ implantation such that the grain size of CoSi₂ with N₂⁺ implantation is much smaller than that without N₂⁺ implantation. As a result, the thermal stability of CoSi₂ is significantly improved by N₂⁺ implantation into polysilicon     

4H-SiC MOSFETs utilizing the H2 surface cleaningtechnique

The H₂ cleaning technique was examined as the precleaning of the gate oxidation for 4H-SiC MOSFETs. The device had a channel width and length of 150 and 100 μm, fabricated on the p-type epitaxial layer of 3×10¹⁶ cm^-3. The gate oxidation was performed after the conventional RCA cleaning, and H₂ annealing at 1000°C. The obtained channel mobility depends on the pre-cleaning process strongly, and was achieved 20 cm²/N s in the H₂ annealed sample. The effective interface-state density was also measured by the MOS capacitors fabricated on the same chips, resulting 1.8×10¹² cm^-2 from the photo-induced C-V method     

Improved electrical characteristics of CoSi2 usingHF-vapor pretreatment

We have developed a simple process to form epitaxial CoSi₂ for shallow junctions. Prior to metal deposition, the patterned wafers were treated with HF-vapor passivation. As observed by scanning tunneling microscopy (STM), this HF treatment drastically improves the native oxide-induced surface roughness. The epitaxial behavior was confirmed by cross-sectional transmission electron microscopy (TEM). Decreased sheet resistance and leakage current, and improved thermal stability are displayed by the HF treated samples, which is consistent with STM and TEM results     

Plasma etching of ternary silicide top layers

Plasma etching of epitaxial CoSi₂ films with a ternary Co–Ti–Si top layer formed during solid phase reaction of Co/Ti bilayers on Si(100) was investigated. By using a pure argon-RF-plasma the ternary top layer was sputtered without formation of a disturbing overlayer. The main disadvantage of this process is the formation of a crater-like surface morphology connected with a strong increase of the surface roughness. Etching the ternary top layer by a reactive process (CF₄/Ar) leads to a smoother surface, but a Co–fluoride film was grown on top of the silicide surface. In a following argon etch process this disturbing overlayer can be removed completely, simultaneously the roughness of the etched silicide surface is reduced considerably.     

The effect of Co incorporation on electrical characteristics of n+/p shallow junction formed by dopant implantation into CoSi2 and anneal

The impact of Co incorporation on the electrical characteristics has been investigated in n⁺/p junction formed by dopant implantation into CoSi₂ and drive-in anneal. The junctions were formed by As⁺ (30 or 40 keV, 1×10¹⁶ cm ^-2) implantation into 35 nm-thick CoSi₂ followed by drive-in annealing at 900°C for 30 s in an N₂ ambient. Deeper junction implanted by As⁺ at 40 keV was not influenced by the Co incorporation. However, for shallower junction implanted by As ⁺ at 30 keV, incorporation of Co atoms increased its leakage current, which were supposed to be dissociated from the CoSi₂ layer by silicide agglomeration during annealing. The mechanism of such a high leakage current was found to be Poole-Frenkel barrier lowering induced by high density of Co traps     

Comparison of transformation to low-resistivity phase andagglomeration of TiSi2 and CoSi2

The phase transformation and stability of TiSi₂ on n ⁺ diffusions are investigated. Narrower n⁺ diffusions require higher anneal temperatures, or longer anneal times, than wider diffusions for complete transitions from the high-resistivity C49 phase to the low-resistivity C54 phase. A model is presented which explains this in terms of the probability of forming C54 nuclei on narrow diffusions and the influence of diffusion width on C54 grain size. The results are that more C49 and C54 nucleation events are required to completely transform narrow lines. For thin TiSi₂ (40 nm), there is a narrow process window for achieving complete transformation without causing agglomeration of the TiSi₂. The process window decreases with decreasing silicide thickness. A significantly larger process window is achieved with short-time rapid annealing. Similar studies are performed for CoSi₂ on n⁺ and p⁺ diffusions. No linewidth dependence is observed for the transformation from CoSi_x to CoSi₂. There is a broad process window from 575°C to 850°C using furnace annealing, for which the low-resistivity phase is obtained without causing agglomeration     

The influence of Ti capping layers on CoSi2 formation

Cobalt silicide formation is very sensitive to the presence of oxygen. Oxygen contamination may originate from different sources: impurities in the annealing ambient, oxygen incorporated within the deposited Co layer and interfacial oxide at the Co/Si interface. In this work, it is shown that the cause of the sensitivity towards oxygen contamination is the formation of a SiO_x diffusion barrier between CoSi and the unreacted Co. This causes an increase in the activation energy for CoSi formation. Furthermore, we will show that a titanium capping layer eliminates the sensitivity of CoSi₂ formation for oxygen contamination, thus improving the formation of CoSi₂ layers.     

Improved electrical characteristics of CoSi2 usingHF-vapor pretreatment

We have developed a simple process to form epitaxial CoSi₂ for shallow junctions. Prior to metal deposition, the patterned wafers were treated with HF-vapor passivation. As observed by scanning tunneling microscopy (STM), this HF treatment drastically improves the native oxide-induced surface roughness. The epitaxial behavior was confirmed by cross-sectional transmission electron microscopy (TEM). Decreased sheet resistance and leakage current, and improved thermal stability are displayed by the HF treated samples, which is consistent with STM and TEM results     

Contact and via structures with copper interconnects fabricatedusing dual Damascene technology

A novel submicron process sequence was developed for the fabrication of CoSi₂/n⁺-Si, CoSi₂/p⁺-Si ohmic contacts and multilevel interconnects with copper as the interconnect/via metal and titanium as the diffusion barrier. SiO₂ deposited by plasma enhanced chemical vapor deposition (PECVD) using TEOS/O₂ was planarized by the novel technique of chemical-mechanical polishing (CMP) and served as the dielectric. The recessed copper interconnects in the oxide were formed by chemical-mechanical polishing. (dual Damascene process). Electrical characterization of the ohmic contacts yielded contact resistivity values of 10^-6Ω-cm² or less. A specific contact resistivity value of 1.5×10^-8Ω-cm² was measured for metal/metal contacts     

Electrical characterization of ultra-shallow junctions formed bydiffusion from a CoSi2 layer

Ultra-shallow p⁺/n and n⁺/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800-900°C). A thin layer (50 nm) of CoSi₂ was implanted with As or with BF₂ and subsequently annealed at different temperatures and times to form two ultra-shallow junctions with a distance between the silicide/silicon interface and the junction of 14 and 20 nm, respectively. These diodes were investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. The reverse leakage currents for the SADS diodes were as low as 9×10 ^-10 A/cm² for p⁺/n and 2.7×10^-9 A/cm² for n⁺/p, respectively. The temperature dependence of the reverse current in the p ⁺/n diode is characterized by a unique activation energy (1.1 eV) over all the investigated range, while in the n⁺/p diode an activation energy of about 0.42 eV is obtained at 330 K. The analysis of the forward characteristic of the diodes indicate that the p⁺ /n junctions have an ideal behavior, while the n⁺/p junctions have an ideality factor greater than one for all the temperature range of the measurements. TEM delineation results confirm that, in the case of As diffusion from CoSi₂, the junction depth is not uniform and in some regions a Schottky diode is observed in parallel to the n⁺/p junction. Finally, from the C-V measurements, an increase of the diodes area of about a factor two is measured, and it is associated with the silicide/silicon interface roughness     

CoSi2 ohmic contacts to n-type 6H---SiC

Cobalt disilicide (CoSi₂) ohmic contacts possessing low specific contact resistivity (_c < 3.0 ± 0.4 × 10⁻⁵ ωcm²) to n-type 6H---SiC are reported. The contacts were fabricated via sequential electron-beam evaporation of Co and Si layers followed by a two-step vacuum anealing process at 500 and 900°C. Stochiometry of the contact so formed was confirmed by Rutherford backscattering spectrometry and X-ray diffraction. Specific contact resistivities were obtained via current-voltage (I-V) analysis at temperatures ranging from 25 to 500°C. _c is compared as a function of carrier concentration, current density, temperature and time at elevated temperature.     

Improved Ge Surface Passivation With Ultrathin SiOX Enabling High-Mobility Surface Channel pMOSFETs Featuring a HfSiO/WN Gate Stack

To realize high-mobility surface channel pMOSFETs on Ge, a 1.6-nm-thick SiO_X passivation layer between the bulk Ge substrate and HfSiO gate dielectric was introduced. This approach provides a simple alternative to epitaxial Si deposition followed by selective oxidation and leads to one of the highest peak hole mobilities reported for unstrained surface channel pMOSFETs on Ge: 332 cm² middotV^-1middots^-1 at 0.05 MV/cm-a 2times enhancement over the universal Si/SiO₂ mobility. The devices show well-behaved output and transfer characteristics, an equivalent oxide thickness of 1.85 nm and an I_ON/I_OFF ratio of 3times10³ without detectable fast transient charging. The high hole mobility of these devices is attributed to adequate passivation of the Ge surface     

High‐Density Periodically Ordered Magnetic Cobalt Ferrite Nanodot Arrays by Template‐Assisted Pulsed Laser Deposition

A novel nanopatterning method using pulsed laser deposition through an ultrathin anodic aluminium oxide (AAO) membrane mask is proposed to synthesize well‐ordered nanodot arrays of magnetic CoFe₂O₄ that feature a wide range of applications like sensors, drug delivery, and data storage. This technique allows the adjustment of the array dimension from ～35 to ～300 nm in diameter and ～65 to ～500 nm in inter‐dot distance. The dot density can be as high as 0.21 Terabit in.^?2. The microstructure of the nanodots is characterized by SEM, TEM, and XRD and their magnetic properties are confirmed by well‐defined magnetic force microscopy contrasts and by hysteresis loops recorded by a superconducting quantum interference device. Moreover, the high stability of the AAO mask enables the epitaxial growth of nanodots at a temperature as high as 550 °C. The epitaxial dots demonstrate unique complex magnetic domains such as bubble and stripe domains, which are switchable by external magnetic fields. This patterning method creates opportunities for studying novel physics in oxide nanomagnets and may find applications in spintronic devices.