Fabrication of Schottky barrier MOSFETs using self-assembly CoSi2 nanopatterning and spacer gate technologies

A self-assembly patterning method for generation of epitaxial CoSi₂ nanostructures was used to fabricate 50 nm channel-length MOSFETs. The transistors have either a symmetric structure with Schottky source and drain or an asymmetric structure with n⁺-source and Schottky drain. The patterning technique is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal oxidation. The strain field is generated along the edges of a mask consisting of 20 nm SiO₂ and 300 nm Si₃N₄. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. A poly-Si spacer was used as the gate contact. The asymmetric transistor was fabricated by ion implantation into the unprotected CoSi₂ layer and a subsequent out-diffusion process to form the n⁺-source. I–V characteristics of both the symmetric and asymmetric transistor structures have been investigated.     

A novel charge pump drive circuit for power MOSFETs

Novel improved power metal oxide semiconductor field effect transistor (MOSFET) drive circuits are introduced. An anti-deadlock block is used in the P-channel power MOSFET drive circuit to avoid deadlocks and improve the transient response. An additional charging path is added to the N-channel power MOSFET drive circuit to enhance its drive capability and improve the transient response. The entire circuit is designed in a 0.6 μm BCD process and simulated with Cadence Spectre. Compared with traditional power MOSFET drive circuits, the simulation results show that improved P-channel power MOSFET drive circuit makes the rise time reduced from 60 to 14 ns, the fall time reduced from 240 to 30 ns, and its power dissipation reduced from 2 to 1 mW, while the improved N-channel power MOSFET drive circuit makes the rise time reduced from 360 to 27 ns and its power dissipation reduced from 1.1 to 0.8 mW.     

一款新型电荷泵功率管驱动电路

提出了一款新型功率管驱动电路。P沟道功率管驱动电路加入了防死锁模块防止了死锁的出现,提高了瞬态响应;N沟道功率管驱动电路加入了附加的充电支路,提高了驱动能力和瞬态响应。整个电路基于0.6μm BCD工艺,在Cadence Spectre下仿真。和传统的功率管驱动电路相比,新的P沟道功率管驱动电路的上升时间由60ns减少到14ns,下降时间由240ns减少到30ns,并且功耗从2mW减少到1mW;新的N沟道功率管驱动电路的上升时间由360ns减少到27ns,功耗从1.1mW减少到0.8mW。     

Feasible approach to the fabrication of asymmetric Schottky barrier MOSFETs by using the spacer technique

The spacer technique is proposed for the fabrication of the Asymmetric Schottky Barrier MOSFETs (ASB-MOSFET). The characteristics of the 45 nm and the 20 nm n-channel ASB-MOSFETs, which adopt a Schottky barrier height of 0.9 eV at source and that of 0.2 eV at drain, have been simulated and discussed by the comparisons with the conventional Schottky Barrier MOSFETs (SB-MOSFET). With a higher Ion/Ioff ratio, the ASB-MOSFET structure has shown a better performance than the conventional SB-MOSFETs.     

A charge sheet model for MOSFETs with an abrupt retrograde channel Part I. Drain current and body charge

Analytical solutions to drain current, depletion and inversion charges for MOSFETs with an ideally abrupt retrograde doping profile in the channel are derived based on the charge sheet model. The validity of the analytical solutions is confirmed by comparing the modeling results with simulation data obtained using numerical calculations; the modeling and simulation results are in excellent agreement. It is shown that the inclusion of an intrinsic surface layer in the channel causes a voltage shift in the drain current, in accordance with experimental observations. For the depletion charge, an analytical expression principally identical to that for the uniformly doped body case is found with a simple replacement of the surface potential, ψ_s, by the potential at the interface between the intrinsic surface layer and the doped substrate, ψ_ξ.     

A new method for extracting the effective channel length of MOSFETs

A new and simple method to extract the effective channel length L_eff of metal-oxide superconductor field effect transistor (MOSFET)s is presented. The method, which is developed based on an auxiliary integral function, has the advantage of determining the value of L_eff not influenced by the series resistances of the MOSFET. The method is tested in the environments of device simulation and measurements. In addition, comparison is made between the results obtained from the present method and a widely used L_eff extraction method.     

A channel resistance derivative method for effective channel lengthextraction in LDD MOSFETs

A channel resistance derivative method for extracting the electrical effective channel length and series resistance is proposed, and demonstrated on an advanced 0.35 μm LDD CMOS technology. A clear graphic image of the L_EFF and R_SD is obtained directly from the measured channel resistance and its derivative with respect to the gate bias. The method also provides guidelines for the proper gate bias range selection in traditional L_EFF extraction techniques     

A novel surface potential-based short channel MOSFET model for circuit simulation

In this paper a novel analytical approximation method for surface potential (ψ_s) calculation in compact MOSFET model is presented. It achieves excellent accuracy and good calculation speed over all regions from accumulation to strong inversion. With this approximation method, a surface potential-based compact model for short channel MOSFET is developed. Comparison with measured data is also presented to validate the new model.     

非掺杂对称双栅的基于完整表面电势的核心模型

通过求解Poisson方程自洽地得到了表面电势随沟道电压的变化关系,从而推出了非掺杂对称双栅MOSFET的一个基于表面势的模型.通过Pao-Sah积分得到了漏电流的表达式.该模型由一组表面势方程组成,解析形式的漏电流可以通过源端和漏端的电势得到.结果标明该模型在双栅MOSFET的所有工作区域都成立,而且不需要任何简化(如应用薄层电荷近似)和辅助拟合函数.对不同工作条件和不同尺寸器件的二维数值模拟与模型的比较进一步验证了提出模型的精度.     

MOSFET抗辐照能力预测方法

基于金属-氧化物-半导体场效应晶体管(MOSFET)噪声的载流子数涨落和迁移率涨落理论,建立起MOSFET抗辐照能力预测模型.利用该模型,可较好地通过辐照前的1/f噪声参量,预测辐照后分别由氧化层陷阱和界面陷阱诱使阈值电压漂移的情况.模型模拟结果与实际测量结果符合良好,验证了预测模型的正确性,并为工程应用提供MOSFET抗辐照能力预测方法.     

MOSFET抗辐照能力预测方法

基于金属-氧化物-半导体场效应晶体管(MOSFET)噪声的载流子数涨落和迁移率涨落理论,建立起MOSFET抗辐照能力预测模型.利用该模型,可较好地通过辐照前的1/f噪声参量,预测辐照后分别由氧化层陷阱和界面陷阱诱使阈值电压漂移的情况.模型模拟结果与实际测量结果符合良好,验证了预测模型的正确性,并为工程应用提供MOSFET抗辐照能力预测方法.     

用于红外探测的铱硅化物的X射线光电子能谱

用Ｘ射线光电子能谱方法测量了铱硅化物的芯能级谱。得到了与化学键有关的化学多和芯能级对称性变化方面的信息，提出了在ＩｒＳｉ／Ｓｉ肖特基势垒形成机理与界面外ＩｒＳｉ和Ｓｉ原子的化学键密切相关本文结果有益于解用铱硅化物肖特基势垒制备红外探测器。     

A charge sheet model for MOSFETs with an abrupt retrograde channel: Part II. Charges and intrinsic capacitances

The 16 intrinsic capacitance components related to the gate, source, drain and depletion charges are examined for MOSFETs with an ideally abrupt retrograde doping profile in the channel, based on the analytical solutions for the drain current and body charge in the preceding paper. Though lengthy and complex in their final mathematical expressions, analytical solutions for the capacitances can be obtained. The validity of the analytical solutions is confirmed by comparing the modeling results with simulation data obtained using numerical calculations. The inclusion of an intrinsic surface layer in the channel merely causes a simple voltage shift for the capacitances that are not associated with the depletion charge or body bias, similarly to the variation of the drain current shown in the preceding paper. For the capacitances that are related to the depletion charge or body bias, there is not only a parallel voltage shift with an amount commensurate to the shift in drain current as well as in the other capacitances, but also a decrease in their values. This decrease depends on the thickness of the intrinsic surface layer and it amounts to 25% for a surface layer of 30 nm thickness.     

Suppression of short channel effects by full inversion in deep sub-micron gate SOI MOSFETs

Classical modeling of fully inverted SOI MOSFET (FI MOSFET) has been performed. In FI MOSFETs, the top Si layer is thinner than the thickness of the inversion layer at the conducting state and so the depleted region in the top Si layer is completely eliminated. It was found that the gate electric field induces carriers in the channel more effectively in FI MOSFET than in the fully depleted SOI MOSFETs (FD MOSFET), so that the short channel effects can be suppressed significantly.     

高压MOSFET直流特性宏模型的建立与参数优化

分析了SPICE BSIM3模型对高压双扩散漏MOSFET(HV double diffuse drain MOSFET)模拟过程中产牛的较大偏差,有针对性地提出一种由nMOSFET,MESFET,二极管等常规SPICE器件组成的高压晶体管宏模型.该宏模型结构简单、使用方便,能准确描述HVMOS的I-V特性.为了提高该模型的尺寸可缩放性(scalability),将MESFET阈值电压对体电压的敏感因子K1进行优化,提取了不同沟道尺寸(W/L)下K1取值的半经验公式,使该宏模型能够适用于不同尺寸的晶体管,大大提高了它的实用价值.该尺寸可缩放宏模型(scalable macromodel)能应用于基于SPICE模型的各种通用EDA软件.     

一种基于载流子的双栅MOSFET解析模型

提出一种全新的基于载流子求解的双栅MOSFET解析模型. 针对无掺杂对称双栅MOSFET结构，该模型由求解泊松方程的载流子分布和Pao-Sah电流形式直接发展而来. 发展的解析模型完全基于MOSFET的基本器件物理进行直接推导,结果覆盖了双栅 MOSFET所有的工作区:从亚阈到强反型和从线性到饱和区,不需要任何额外假设和拟合参数. 模型的预言结果被2D数值模拟很好地验证，表明该解析模型是一个理想的双栅MOSFET建模架构.     

A capacitance-based method for experimental determination ofmetallurgical channel length of submicron LDD MOSFETs

A capacitance based method for determining L_met the metallurgical channel length of MOSFET, is proposed in this paper. This method has been extensively evaluated via two-dimensional numerical device simulation of MOSFETs with different source/drain tip and channel impurity concentration profiles as well as different gate oxide thicknesses. For all the impurity profiles tested, results demonstrated that the accuracy in extracting L_met of MOSFETs with gate oxides thinner than 100 Å is better than 110 Å. This method is applicable even when there is significant source/drain reoxidation induced gate oxide thickening, as long as the gate oxide thickening is not extended into the region directly above the metallurgically defined channel region. Unlike the determination of L_eff, the effective electrical channel length, from the drain current, L_met is extracted from capacitance data and the extraction is free from complications that can be introduced by incomplete removal of the resistive effects associated with contacts and the lightly doped source/drain region. Extensive measurements were performed on MOSFETs of different technologies. It is shown that the measurement is accurately repeatable and no device stressing is experienced over the required bias range. The L_met and L_eff extracted from measured capacitance and drain current data are compared. Results showed that L _met is typically 700 to 1200 Å shorter for submicron MOS technologies, but it tracks with L_eff, i.e. a shorter L _met corresponds to a shorter L_eff     

A robust spacer gate process for deca-nanometer high-frequency MOSFETs

This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 μm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 μS/μm with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 μA/μm. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.     

一种适用于短沟道LDD MOSFET参数提取的改进方法

提出了一种适用于短沟道LDD MOSFET的改进型参数提取方法,通过对栅偏压范围细分后采用线性回归方法,提取偏压相关参数,保证了线性回归方法的精度和有效性,避免了对栅偏压范围的优化和误差考虑.提取出的参数用于已建立的深亚微米LDD MOSFET的I-V特性模型中,模拟与测试数据的吻合表明了该方法的实用性.     

Characterization of double gate MOSFETs fabricated by a simple method on a recrystallized silicon film

A simple process to fabricate double gate SOI MOSFET is proposed. The new device structure utilizes the bulk diffusion layer as the bottom gate. The active silicon film is formed by recrystallized amorphous silicon film using metal-induced-lateral-crystallization (MILC). While the active silicon film is not truly single crystal, the material and device characteristics show that the film is equivalent to single crystal SOI film with high defect density, like SOI wafers produced in early days. The fabricated double gate MOSFETs are characterized, which demonstrate excellent device characteristics with higher current drive and stronger immunity to short channel effects compared to the single gate devices.