多级分块CRC的快速配置方法

分块循环冗余校验(CRC)方法能够满足高速通信链路要求.针对现在方法主要通过多项式公式推导和查表法实现,较难推广的问题,提出一种快速配置方法.首先,使用状态矩阵推导出CRC并行计算方法.通过矩阵变换,将余数计算和余数变换合并,简化计算步骤,实现多通道与并行位宽混合的多级分块CRC计算方法;对长度可变数据的计算,实现生成多项式、通道数、单通道并行处理位宽的任意配置.仿真结果表明该方法进一步提高了分块CRC校验速度,且增加通道数比并行位宽扩展更能提高运算性能.     

基于FPGA全参数化CRC的推导及实现

提出一种新型的全参数化CRC算法。详细地介绍全参数化CRC的算法原理,并给出算法公式的推理过程及结果,通过Verilog语言设计实现,给出了基于FPGA平台的仿真波形图,并成功应用于工程项目当中,最后详细分析了全参数化CRC算法在实现过程中的优势。这里提出的全参数化CRC算法,可以通过参数化配置,实现CRC-4、CRC-8、CRC-12等任何CRC-X的运算,亦可以实现任何数据位宽(数据位宽小于等于CRC校验码位宽)、任意生成多项式的CRC运算。     

Xmodem协议中CRC算法的FPAG实现

基于解决Xmodem协议中CRC校验的目的,以经典的LFSR硬件电路为基础,采用了按字节并行运算CRC校验码,以及多字节CRC算法的方法。在Quartus II环境下,通过以VHDL语言仿真试验,得出Xmodem协议中CRC校验,以多字节循环并行CRC算法能够满足高速实时性要求的结论。     

一种并行CRC算法的实现方法

简要分析了CRC算法的基本原理.在传统串行CRC的实现基础上,介绍了一种快速的CRC并行算法,导出了32位并行CRC码的逻辑关系,推导过程简单.与查表法比较,此并行算法不需要存储大量的余数表,可以减少延迟.同时,这种并行处理方法也适合于其他位宽并行CRC码.最后,利用ISE开发平台和Verilog HDL硬件描述语言进行设计,实现了基于此并行算法的32位并行CRC-32码的编码器,并给出了仿真和综合结果.设计出来的CRC编码器,已经成功应用于以太网的接入系统中.     

基于FPGA超高频RFID系统并行CRC模块设计

根据CRC(循环冗余校验码)算法的原理,和ISO/IEC18000-6标准中超高频射频识别系统对校验电路的要求,分析串行CRC算法,提出了一种并行CRC算法。经Verilog-HDL语言编写该算法程序,在QuartusⅡ9.0软件上仿真。最终给出仿真结果以及并行CRC生成模块和校验模块,仿真结果证明并行CRC算法有效提高了系统中数据的处理速度。     

基于公式递推法的可变计算位宽的循环冗余校验设计与实现

循环冗余校验(CRC)与信道编码的级联使用,可以有效改善译码的收敛特性。在新一代无线通信系统,如5G中,码长和码率都具有多样性。为了提高编译码分段长度可变的级联系统的译码效率,该文提出一种可变计算位宽的CRC并行算法。该算法在现有固定位宽并行算法的基础上,合并公式递推法中反馈数据与输入数据的并行计算,实现了一种高并行度的CRC校验架构,并且支持可变位宽的CRC计算。与现有的并行算法相比,合并算法节省了电路资源的开销,在位宽固定时,资源节约效果明显,同时在反馈时延上也有将近50%的优化;在位宽可变时,电路资源的使用情况也有相应的优化。     

32位CRC校验码的并行算法及硬件实现

通过对CRC校验码原理的分析,研究了一种并行32位CRC算法。该算法采用递推的方法,直接得出计算多位数据后的CRC余数与计算前余数之间的逻辑关系。相对于一般的按位串行计算或者查表并行计算的方法来说,该方法运算速度快且不需要额外的空间存储余数表,十分有利于硬件实现。     

针对任意位的CRC并行化方法及编解码器的实现

介绍了一种基于查表法的针对任意位数据的任意位CRC并行计算的原理及算法，克服了现有的两类CRC并行算法延时大、毛刺多或仅适于2^n位数据的2^n位CRC校验的缺点。该方法使并行CRC校验的传输数据位数与CRC码位数之间的选择更灵活，并且在加速比、功耗和面积等方面具有优势。     

新型超高频RFID编解码和CRC电路的设计与实现

提出了一种新的超高频射频识别(RFID)标签芯片的数据编解码与循环冗余校验(CRC)计算同步进行的电路结构。该电路采用ISO/IEC 18000.6C标准协议,在数据编解码过程中同步进行串行CRC计算来提高系统数据的处理速度。采用FPGA进行仿真分析。结果表明,该设计方法可实现CRC编解码与RFID数据的编解码同步,即不占用额外的时钟处理CRC计算,从而满足超高频RFID的快速通信要求。所提出的串行CRC电路在SIMC 0.18 μm标准CMOS工艺下进行综合,其面积比并行CRC电路节省31.4%,电路算法更简单。     

CAN总线中CRC编码的硬件实现

基于CAN总线数据传输过程中加入的CRC编码技术与原理,本文首先给出了比特串行CRC编码原理及基于除法编码运算的CRC编码算法硬件实现方法。然而,为了满足高速数据传输的需要,本文进一步给出了,利用空间换取时间的比特并行CRC编码算法的详细推导过程,最后是采用VHDL语言与FPGA器件,完成了CAN总线中比特并行CRC编码算法的硬件仿真、综合、布线及下载配置,结果表明完全达到了预期的设计要求。     

Low Power Memory Built in Self Test Address Generator Using Clock Controlled Linear Feedback Shift Registers

In the ongoing high-speed, high-tech sophistication in the technology of VLSI designs, Built-in Self-Test (BIST) is emerging as the essential element of the memory, which can be treated as the most essential ingredient of the System on Chip. The market is flooded with diverse algorithms exclusively intended for investigating the memory locations. LFSRs (Linear Feedback Shift Register) are employed extensively for engendering the memory addresses, so that they can be consecutively executed on the memory cores under experimentation. What we have attempted to put forward through this paper is a proposed LFSR based address generator with significant decrease in switching process for low power MBIST (Memory Built in Self Test). In this novel technique, the address models are produced by a blend of LFSR and a 2-bit pattern generator (Modified LFSR) and two distinct clock signals. With the efficient employ of the adapted architecture switching activity is considerably cut down. As the switching activity is in direct proportion to the power consumed scaling down the switching process of the address generator inevitably leads to the reduction in power consumption of the MBIST. In this paper we have taken pains to design and stimulate the proposed address generator by means of Xilinx ISE tools and contrasted it with the switching activities of the conventional LFSR and BS-LFSR (Bit Swapping Linear Feedback Shift Register). The encouraging outcomes illustrate a significant reduction in switching activity, to the tune of 90 % plus of the entire dynamic power in relation to the traditional LFSR.     

An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment

To obtain satisfactory fault coverage for testing a logic circuit, linear feedback shift registers (LFSRs) have been used to generate not only the pseudorandom, but also the deterministic patterns in the scan-based built-in self-test environment. However, like other scan-based methods, the LFSR based pattern generation schemes take a long test application time to feed deterministic patterns from the LFSR into a scan chain. In this paper we derive a general relationship between the bits in the scan chain and the states of the LFSR and show that any bit to be generated by an LFSR in any future clock cycle can be pre-generated by a linear function of the current LFSR state. With this relationship, we can divide a scan chain into multiple sub-chains and use one LFSR-based multiple sequence generator to simultaneously generate all the subsequences required by the sub-chains, hence can greatly reduce the test application time for deterministic patterns. Moreover, due to the scan time reduction, test power wasted during the scan operation can also be significantly reduced.     

缩扩生成器的构造与分析

论文将自扩生成器与缩减生成器组合构成了一种新型的伪随机序列生成器——缩扩生成器，它由两个三元的线性反馈移位寄存器（LFSR）构成。文中讨论了某种特殊情形下得到的缩扩序列的周期、符号分布、特征多项式等密码学性质。     

一种基于双三极管并联的UWB 窄脉冲发生器

脉冲产生器是IR-UWB通信系统的重要组成模块之一。提出了一种高可靠性的窄脉冲发生电路。该脉冲产生电路基于并联的双射频三极管所产生的雪崩效应与LC电路阻尼原理,产生一阶微分高斯脉冲波形。双三级管的并联设计加速了雪崩效应,降低了工作电压,易于电路实现。当其中单只三极管损坏时,电路仍然可以依靠另一只进行工作。实验测试结果表明：该电路所产生的脉冲峰峰值约为12.88V,脉冲宽度约为1.6ns,可以用于IR-UWB通信系统。     

一种新型混合模式BIST的低功耗设计

本文提出了一种基于折叠集的test-Der-clock结构的混合模式BIST设计方案,并且进行了低功耗的整体优化设计.该设计方案在电路结构上利用双模式LFSR将两部分测试生成器有机的进行了结合,针对伪随机测试序列与折叠测试序列两部分采用了不同的措施来优化测试生成器的设计,从而达到降低被测电路功耗的目的.     

A 3$,times,$5-Gb/s Multilane Low-Power 0.18-$mu{hbox {m}}$ CMOS Pseudorandom Bit Sequence Generator

A low-power, three-lane, pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-mum CMOS process to test a multilane multi-Gb/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator was designed to produce three uncorrelated 12-Gb/s PRBS sequences, measurement results included in this paper have been obtained at only 5 Gb/s due to test setup limitations. The prototype employs a CMOS latch optimized to operate at frequencies close to the of the process and a current-mode logic (CML) MUX with modified active inductor loads for better high-speed large-signal behavior. In order to reduce the power consumption, a quarter-clock rate linear feedback shift register (LFSR) core in a power-efficient parallel architecture has been implemented to minimize the use of power-hungry, high-speed circuitry. Further power reduction has been achieved through the clever partitioning of the system into static logic and CML. In addition, the prototype design produces three uncorrelated 12-Gb/s data streams from a single quarter-rate LFSR core, thereby amortizing the power across multiple channels which lowers the power per channel by 3 times. The total measured power consumption at 5 Gb/s is 131 mW per lane and the calculated figure of merit per lane is 0.84 pJ/bit, which is significantly better than previously published designs.     

XTR公钥密制的改进及可证明安全通信协议

提出一种新的迹函数,将基于3阶LFSR序列的XTR公钥密码体制(称之为XTR3体制),改进为基于4阶LFSR序列的XTR4公钥密码体制。与XTR3体制比较,同等安全程度下XTR4的密钥长度小于XTR3。提出XTR4体制上的密钥交换协议,可证明安全性保密通信协议,一次一密协议,可以应用于多种环境,既能保证安全性,又能显著地提高运算效率。     

RS编译码电路的可重构性研究

针对当前RS码编译码器通用性差的特点,以可重构的思想,提出了一种根据输入配置信息改变电路结构,满足多种RS码编码标准的编译码结构。介绍了基于线性反馈位移寄存器的编码原理及可重构改进方法。通过乘法和加法的迭代运算实现了伴随多项式的并行运算。采用改进欧几里德算法求解关键方程,运用钱氏搜索算法实现了错误位置的查找,并提出以上两种算法的可重构计算结构。通过分析可以看出:该方案增加了少量的资源开销,满足了多标准的RS码编译需要,具有较好的通用性。     

Cost-effective LFSR synthesis for optimal pseudoexhaustive BISTtest sets

The generation of pseudoexhaustive test sets for the built-in self-test (BIST) of combinational circuits is addressed, using as a test pattern generator a simple linear feedback register (LFSR), structure, known as LFSR/SR. It is shown that particular orderings of the LFSR cells can significantly reduce the test set size. In addition, it is shown that an LFSR/SK designed with a particular cell ordering and the allowance of a marginal number of additional cells guarantees pseudoexhaustive test sets of the minimum size 2^w, where w is the maximum input dependency limit of the circuit under test. Extensive experimentation on benchmark circuits and comparisons with the hardware overhead of other methods indicate the advantage of this approach     

一种新型的缩控生成器

将缩减生成器与一种新型的钟控生成器组合构成了一种新型的伪随机序列生成器—缩控生成器,它是由两个三元的线性反馈移位寄存器(LFSR)构成。文章讨论了这种新型的缩控序列的周期,线性复杂度,符号分布及1,2-重量复杂度等密码学性质。分析结果表明,这种缩控序列具有大的周期,大的线性复杂度,符号分布也比较均衡,而且当LFSR级数很大时,缩控序列能够有效地抵抗B-M算法的攻击,适合于流密码系统中的应用。