A 20-nm physical gate length NMOSFET featuring 1.2 nm gate oxide,shallow implanted source and drain and BF2 pockets

We have demonstrated the feasibility of 20-nm gate length NMOSFET's using a two-step hard-mask etching technique. The gate oxide is 1.2-nm thick. We have achieved devices with real N^- arsenic implanted extensions and BF₂ pockets. The devices operate reasonably well down to 20-nm physical gate length. These devices are the shortest devices ever reported using a conventional architecture     

Carrier mobility in p-MOSFET with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics

P/sup +/-poly-Si gate MOS transistors with atomic-layer-deposited Si-nitride/SiO/sub 2/ stack gate dielectrics (EOT=2.50 nm) have been fabricated. Similar to the reference samples with SiO/sub 2/ gate dielectrics (T/sub ox/=2.45 nm), clear saturation characteristics of drain current are obtained for the samples with stack gate dielectrics. Identical hole-effective mobility is obtained for the samples with the SiO/sub 2/ and the stack gate dielectrics. The maximum value of hole-effective mobility is the same (54 cm/sup 2//Vs) both for the stack and the SiO/sub 2/ samples. Hot carrier-induced mobility degradation in transistors with the stack gate dielectrics was found to be identical to that in transistors with the SiO/sub 2/ gate dielectrics. In addition to the suppression of boron penetration, better TDDB characteristics, and soft breakdown free phenomena for the stack dielectrics (reported previously), the almost equal effective mobility (with respect to that of SiO/sub 2/ dielectrics) has ensured the proposed stack gate dielectrics to be very promising for sub-100-nm technology generations.     

Pt-Germanide Schottky source/drain Germanium p-MOSFET with HfO/sub 2/ gate dielectric and TaN gate electrode

Schottky source/drain (S/D) transistors using Pt-germanide and HfO/sub 2//TaN gate stack are fabricated on Ge-substrate with conventional self-aligned top-gate process. It was found that Pt-germanide provides promising properties for p-MOSFET: negative effective hole barrier height, low resistivity, atomically sharp junction with Ge with good morphology. Pt-germanide Ge-p-MOSFETs showed well-behaved I/sub D/-V/sub D/ characteristics and much suppressed I/sub off/ compared to Ni-germanide and conventional heavily doped S/D MOSFETs.     

The effect of fluorine from BF2 source/drain extensionimplants on performance of PMOS transistors with thin gate oxides

Boron penetration from the gate electrode into the Si substrate presents a significant problem in advanced PMOS device fabrication. Boron penetration, which causes a degradation of many transistor parameters, is further enhanced when BF₂ is used to dope the gate electrode. It is known that pile-up of fluorine from the BR gate implant at the polysilicon/gate oxide interface is responsible for the enhanced boron penetration. However, no reports have been made that address enhanced boron penetration due to fluorine from the source/drain (S/D) implants. It is shown here that fluorine from the S/D extension implants is also a significant problem, degrading transistor performance for gate oxide thickness less than 27 Å and gate lengths less than 0.5 μm     

Slight gate oxide thickness increase in PMOS devices with BF2 implanted polysilicon gate

The gate oxide thickness increase in PMOSFET devices with BF₂ implanted p⁺ polysilicon gate is observed even when rapid thermal annealing (RTA) is used as a dopant activation thermal process. The increase of oxide thickness is studied as a function of RTA temperature, RTA time, and initial oxide thickness in the 35 Å regime and is being reported for the first time. It was found that oxide thickness increase could be as significant as 7% in this regime. This phenomenon can be explained by the model of fluorine incorporation, which is found to he effectively suppressed with nitrogen implanted in the polysilicon     

Hot carrier effects in n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate

Charge trapping and trap generation in field-effect transistors with SiO₂/HfO₂/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case.     

Enhanced gate induced drain leakage current in HfO2 MOSFETs

The substrate current of high-κ dielectric MOSFETs has been studied using dc sweep and transient (down to 100 μs per I-V curve) electrical measurements. These measurements reveal trap-assisted substrate current components in addition to the traditional bell-shaped impact ionization current. By separating the transversal and lateral electric field contributions, the gate induced drain leakage (GIDL) is shown to dominate the substrate current at low gate biases. At high gate biases, tunneling of valence band electrons from the bulk to the gate dominates. The results show that the GIDL current is the result of band-to-band tunneling assisted by traps located at the HfO₂/SiO₂ interface and transition layer, and not the result of oxide charging.     

Electrical properties of SiO2/TiO2 high-k gate dielectric stack

The trapping/detrapping behavior of charge carriers in ultrathin SiO₂/TiO₂ stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO₂ films at low temperature (<200 °C) on strained-Si/relaxed-Si_0.8Ge_0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO₂/TiO₂ stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO₂ layer. The increase in the gate current density observed during CVS from room temperature up to 125 ^oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10⁻¹⁹ cm² as compared to 10⁻¹⁶ cm² in SiO₂ has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.     

Characteristics of MOS capacitors of BF2 or B implantedpolysilicon gate with and without POCl3 co-doped

The characteristics of BF₂- or B-implanted polysilicon gate MOS capacitors with and without POCl₃ codoped were studied. It was found that the gate oxide thickness was increased very significantly with the number of high-temperature thermal cycles for BF ₂-implanted polysilicon MOS capacitors, but this was not true for POCl₃-codoped polysilicon MOS capacitors. A model that interprets this phenomenon well was developed using the results of SIMS (secondary ion ion mass spectrometry) measurements     

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported,to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions.This novel structure offers low barrier height at the source and offers high ON-state current.The ION/IoFF of ISE-CGAA-SB-MOS-FET increases by 1177 times and offers steeper subthreshold slope (～60 mV/decade).However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate,dual metal gate,single metal gate with ISE,and dual metal gate with ISE has been presented.The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design.The numerical simulation is performed using the ATLAS-3D device simulator.     

The use of ultrathin reoxidized nitrided gate oxide for suppressionof boron penetration in BF2+-implanted polysilicongated p-MOSFETs

The authors report the use of rapid thermal reoxidized nitrided thin (~90-Å) gate oxides in BF₂⁺-implanted polysilicon gated p-MOSFETs. Although lightly nitrided gate oxides are unable to block the boron penetration, reoxidized nitrided gate oxides are found to have excellent barrier properties against boron penetration. In addition, excellent electrical characteristics in terms of device subthreshold conduction and transconductance are illustrated     

Profiling of traps in SiO2/Al2O3 gate stack by the charge pumping technique

In this paper, we present our results on the distribution and generation of traps in a SiO₂/Al₂O₃ transistor. The investigation has been carried out by using charge pumping measurements, both variable voltage and frequency techniques, and constant voltage stress.By increasing the amplitude of the gate pulse we observe an increase of the charge recombined per cycle closely related to the contribution of shallow traps near the SiO₂/Al₂O₃ interface. By reducing the pulse frequency we measure an increase in the charge pumping current due to traps located deeper in the Al₂O₃. By combining charge pumping and constant voltage stress measurements, we found that the traps are mostly generated near the Si/SiO₂ interface.     

A novel process to form cobalt silicided p+ poly-Sigates by BF2+ implantation into bilayeredCoSi/a-Si films and subsequent anneal

A novel process that implants BF₂⁺ ions into thin bilayered CoSi/a-Si films has been shown to form cobalt silicided p ⁺ poly-Si gates with excellent gate oxide integrity and very small flatband shift. The effects of not only using the CoSi layer as an implantation barrier but also keeping the a-Si underlayer during the initial silicide formation both significantly suppress the boron penetration through thin gate oxide     

A novel technique of N2O-treatment onNH3-nitrided oxide as gate dielectric for nMOS transistors

A novel technique of N₂O treatment on NH₃-nitrided oxide is used to prepare thin gate oxide. Experiments on MOS capacitors and nMOSFET's with this kind of gate dielectric show that N₂O treatment is superior to conventional reoxidation step in suppressing both electron and hole trappings and interface trap creation under high-field stress. Interface hardness against hot-carrier bombardment and neutral electron trap generation are also improved. Thus, N₂O treatment on NH₃ -nitrided oxide shows excellent electrical and reliability properties, while maintaining sufficiently high nitrogen concentration in gate oxide which offers good resistance to dopant penetration     

Narrow-width effects of shallow trench-isolated CMOS with n+-polysilicon gate

Narrow-width effects are discussed of n- and p-MOSFETs with shallow trench isolation. MOSFETs with n⁺-polysilicon gates were fabricated down to channel widths of 0.5 μm by using a novel planarization process with an etch stop. The threshold behavior is characterized as a function of both the sidewall-implanted boron and the three dimensional process/device simulations. The trench-isolated n-MOSFET shows the narrow-width effect with excess boron doses implanted in the sidewalls. It is found that the lateral diffusion of sidewall-implanted boron induces enhancement of the edge current although the devices show narrow-width effects. The trench-isolated p-MOSFETs show narrow-width effects with the buried-channel mode and the inverse-narrow width effect when surface channel conditions dominate at threshold. It is found that the narrow-width effect of p-MOSFETs strongly depends on the threshold adjustment by means of counter doping     

Temperature dependence of electrical properties for MOS capacitor with HfO2/SiO2 gate dielectric stack

We investigated the temperature dependence of C–V and I–V characteristics in p-type Metal Oxide Semiconductor (MOS) capacitors with HfO₂/SiO₂ dielectric stacks. Dramatic degradation in the C–V characteristics at/over the measurement temperature of 125 °C was observed, which was caused by the increased effective oxide thickness, oxide trapped charge density, and interfacial density of state (D_it) with rising temperature during bias temperature stress. In the accumulation region, the leakage current density displayed strong temperature dependence in the ?3 V<Vg<0 V region, as expected for the direct tunneling compared to the trap-assisted component (DT+TAT) effect. The conduction mechanism was transformed into Fowler–Nordheim (FN) tunneling (weak T and Vg dependence) from DT+TAT (strong T and Vg dependence) at Vg <?3 V, which was confirmed by FN tunneling fitting. According to the conventional Shockley–Read–Hall model, the different levels in D_it were found at various measurement temperatures to interpret the strong temperature dependence and weak Vg dependence inversion current property.     

Epitaxial strontium oxide layers on silicon for gate-first and gate-last TiN/HfO2 gate stack scaling

We show that a thin epitaxial strontium oxide (SrO) interfacial layer enables scaling of titanium nitride/hafnium oxide high-permittivity (high-k) gate stacks for field-effect transistors on silicon. In a low-temperature gate-last process, SrO passivates Si against SiO₂ formation and silicidation and equivalent oxide thickness (EOT) of 5 Å is achieved, with competitive leakage current and interface trap density. In a gate-first process, Sr triggers HfO₂-SiO₂ intermixing, forming interfacial high-k silicate containing both Sr and Hf. Combined with oxygen control techniques, we demonstrate an EOT of 6 Å with further scaling potential. In both cases, Sr incorporation results in an effective workfunction that is suitable for n-channel transistors.     

A comparative study of gate direct tunneling and drain leakagecurrents in n-MOSFET's with sub-2 nm gate oxides

This work examines different components of leakage current in scaled n-MOSFET's with ultrathin gate oxides (1.4-2.0 nm). Both gate direct tunneling and drain leakage currents are studied by theoretical modeling and experiments, and their effects on the drain current are investigated and compared. It concludes that the source and drain extension to the gate overlap regions have strong effects on device performance in terms of gate tunneling and off-state drain currents     

TDDB and polarity-dependent reliability of high-quality, ultrathin CVD HfO/sub 2/ gate stack with TaN gate electrode

In this letter, we present a comprehensive study on longterm reliability of ultrathin TaN-gated chemical vapor deposition gate stack with EOT=8.5-10.5. It is found that, due to the asymmetric band structure of HfO/sub 2/ gate stack with an interfacial layer, the HfO/sub 2/ gate stack shows polarity-dependent leakage current, critical defect density, and defect generation rate, under gate and substrate injection. However, no such polarity dependence of time-to-breakdown (T/sub BD/) is observed when T/sub BD/ is plotted as a function of gate voltage. The 10-year lifetime of an HfO/sub 2/ gate stack is projected to be Vg=-1.63 V for the equivalent oxide thickness (EOT) =8.6 and Vg=-1.88 V for EOT=10.6 at 25/spl deg/C. These excellent reliability characteristics are attributed to reduced leakage current of HfO/sub 2/ gate stack with physically thicker films that result in larger critical defect density and Weibull slope to that of SiO/sub 2/ for the same EOT. However, at 150/spl deg/C, and with area scaling to 0.1 cm/sup 2/ and low percentile of 0.01%, the maximum allowed voltages are projected to Vg=-0.6 V and -0.75 V for EOT of 8.6, and 10.6, respectively.     

Electrical characteristics of low temperature polysilicon TFT with a novel TEOS/oxynitride stack gate dielectric

This investigation is the first to demonstrate a novel tetraethylorthosilicate (TEOS)/oxynitride stack gate dielectric for low-temperature poly-Si (LTPS) thin film transistors (TFTs), composed of a plasma-enhanced chemical vapor deposition (PECVD) thick TEOS oxide/ultrathin oxynitride grown by PECVD N/sub 2/O-plasma. The stack oxide shows a very high electrical breakdown field of 8.4 MV/cm, which is approximately 3 MV/cm larger than traditional PECVD TEOS oxide. The field effective mobility of stack oxide LTPS TFTs is over 4 times than that of traditional TEOS oxide LTPS TFTs. These improvements are attributed to the high quality N/sub 2/O-plasma grown ultrathin oxynitride forming strong Si/spl equiv/N bonds, as well as to reduce the trap density in the oxynitride/poly-Si interface.