Leakage current reduction in chemical-vapor-depositedTa2O5 films by rapid thermal annealing in N2O

This study aims to improve the electrical characteristics and reliability of low-pressure chemical vapor deposited (LPCVD) Ta₂ O₅, films by developing a new post-deposition single-step annealing technique. Experimental results indicate that excited oxygen atoms generated by N₂O decomposition can effectively repair the oxygen vacancies in the as-deposited CVD Ta₂ O₅ film, thereby resulting in a remarkable reduction of the film's leakage current. Two other post-deposition annealing conditions are compared: rapid thermal O₂ annealing and furnace dry-O₂ annealing. The comparison reveals that RTN₂O annealing has the lowest leakage current, superior thermal stability of electrical characteristics and the best time-dependent dielectric breakdown (TDDB) reliability     

High quality Al/sub 2/O/sub 3/ IPD with NH/sub 3/ surface nitridation

In this letter, the effect of surface NH/sub 3/ nitridation on the electrical properties and reliability characteristics of aluminum oxide (Al/sub 2/O/sub 3/) interpoly capacitors is studied. With NH/sub 3/ surface nitridation, the formation of an additional layer with lower dielectric constant during post-annealing process can be significantly suppressed, compared to that without nitridation treatment. Furthermore, the presence of a thin Si-N layer can make post-deposition annealing more effective in eliminating traps existing in the as-deposited films. As a result, a smoother interface and smaller electron trapping rate can contribute to the drastically reduced leakage current, enhanced breakdown field and charge to breakdown (Q/sub bd/) of Al/sub 2/O/sub 3/ interpoly capacitors with surface NH/sub 3/ nitridation.     

To optimize electrical properties of the ultrathin (1.6 nm)nitride/oxide gate stacks with bottom oxide materials andpost-deposition treatment

The electrical properties affected by the bottom oxide materials and the post-deposition treatment on the ultrathin (down to 1.6 nm) nitride/oxide (N/O) stacks, prepared by rapid thermal chemical vapor deposition (RTCVD) with two-step NH₃/N₂O post-deposition annealing, for deep submicrometer dual-gate MOSFETs have been studied extensively. N/O stack with NO-grown bottom oxide exhibits fewer flat-band voltage shifts and higher hole and electron mobility, but suffers from worse leakage current than that with conventional O₂-grown bottom oxide. In post-deposition treatment, increasing NH₃ nitridation temperature can effectively reduce the equivalent oxide thickness (EOT) and improve leakage current reduction rate, but can result in worse mobility. Furthermore, the subsequent N₂O annealing eliminates the defects and offers a contrary effect on the N/O stack in comparison with the NH₃ nitridation step     

Electrical and reliability characteristics of an ultrathin TaO/sub x/N/sub y/ gate dielectric prepared by ND/sub 3/ annealing of Ta/sub 2/O/sub 5/

This letter describes a unique process for the preparation of high quality tantalum oxynitride (TaO/sub x/N/sub y/) via the ND/sub 3/ annealing of Ta/sub 2/O/sub 5/, for use in gate dielectric applications. Compared with tantalum oxide (Ta/sub 2/O/sub 5/), a significant improvement in the dielectric constant was obtained by the ammonia treatment followed by light reoxidation in a wet ambient. We were able to confirm nitrogen incorporation in the tantalum oxynitride (TaO/sub x/N/sub y/) by Auger electron spectroscopy. Compared with NH/sub 3/ nitridation, tantalum oxynitride prepared by nitridation in ND/sub 3/ shows less charge trapping and larger charge-to-breakdown characteristics.     

Reduction of leakage current in chemical-vapor-deposited Ta2O5 thin films by furnace N2O annealing

In this brief, we present a post-deposition annealing technique that employs furnace annealing in N₂O (FN₂O) to reduce the leakage current of chemical-vapor-deposited tantalum penta-oxide (CVD Ta₂O₅) thin films. Compared with furnace annealing in O₂ (FO) and rapid thermal annealing in N ₂O (N₂O), FN₂O annealing proved to have the lowest leakage current and the most reliable time-dependent dielectric breakdown (TDDB)     

Effect of CF/sub 4/ plasma pretreatment on low temperature oxides

This study describes a novel technique for forming low temperature oxides (<350/spl deg/C) using a replacement metal gate process. Low temperature oxides were generated by N/sub 2/O plasma in a PECVD system with pretreatment in CF/sub 4/. Fabricated oxides demonstrate excellent current-voltage (I-V) characteristics, such as low leakage current, high breakdown charge and good reliability. Experimental results indicate that CF/sub 4/ plasma treatment can significantly improve the mobility and resistance against hot carrier stress of MOSFETs. With excellent electrical properties, this technique is suitable for fabrication low temperature devices.     

Ta2O5高k介电薄膜的制备及其电学性质的研究

用射频磁控溅射法制备了Ta2O5高介电薄膜,并对其进行了退火处理。用C-V,(G/ω)-V和I-V方法研究了Al/Ta2O5/p-Si结构的电学特性,观测到了C-V和(G/ω)-V的频散效应。认为串联电阻、Si/Ta2O5界面的界面态密度、边缘俘获是频散效应的主要原因,提取了界面态密度和边缘俘获电荷的大小。同时也研究了不同的退火温度对这些参数以及漏电流的影响,经600℃退火后,样品的电容最大,俘获电荷密度和漏电流最小,器件的电学性能最佳。     

Ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on surface-nitrided Ge

We have studied ultrathin Al/sub 2/O/sub 3/ and HfO/sub 2/ gate dielectrics on Ge grown by ultrahigh vacuum-reactive atomic-beam deposition and ultraviolet ozone oxidation. Al/sub 2/O/sub 3/-Ge gate stack had a t/sub eq//spl sim/23 /spl Aring/, and three orders of magnitude lower leakage current compared to SiO/sub 2/. HfO/sub 2/-Ge allowed even greater scaling, achieving t/sub eq//spl sim/11 /spl Aring/ and six orders of magnitude lower leakage current compared to SiO/sub 2/. We have carried out a detailed study of cleaning conditions for the Ge wafer, dielectric deposition condition, and anneal conditions and their effect on the electrical properties of metal-gated dielectric-Ge capacitors. We show that surface nitridation is important in reducing hysteresis, interfacial layer formation and leakage current. However, surface nitridation also introduces positive trapped charges and/or dipoles at the interface, resulting in significant flatband voltage shifts, which are mitigated by post-deposition anneals.     

Enhancing the reliability of n-p junction diodes using plasma treated tantalum barrier film

The properties of Ta barrier films treated with various plasma nitridations have been investigated by Cu/barrier/Si. An amorphous layer is formed on Ta barrier film after plasma treatments. The thickness of the amorphous layer is about 3 nm. Plasma treated Ta films possess better barrier performance than sputtered Ta and TaN films. It is attributed to the formation of a new amorphous layer on Ta surface after the plasma treatment. Cu/Ta(N,H)/Ta (10 nm)/Si remained stable after annealing at 750 °C. Ta(N,H)/Ta possesses the best thermal stability and excellent electrical properties. Cu/Ta/n⁺-p and Cu/Ta(N,O)/Ta/n⁺-p diodes resulted in large reverse-bias junction leakage current after annealing at 500 °C and 600 °C, respectively. On the other hand, Ta(N,H)/Ta and Ta(N)/Ta diffusion barriers improve the thermal stability of junction diodes to 650 °C. Ta(N,H)/Ta barrier film possesses lowest resistivity among Ta, Ta(N,O)/Ta, and Ta(N)/Ta films. Hydrogen plays an important role in enhancement of barrier properties. It is believed that hydrogen not only induces amorphization on Ta, but also eliminates the oxygen in the film. It is believed that the enhancement of ability against the copper diffusion is due to the combined effects of the hydrogen reaction and nitridation.     

DRAM plate electrode bias optimization for reducing leakage current in UV-O/sub 3/ and O/sub 2/ annealed CVD deposited Ta/sub 2/O/sub 5/ dielectric films

A new plate biasing scheme is described which allowed the use of 65% higher supply voltage without increasing the leakage current for the UV-O/sub 3/ and O/sub 2/ annealed chemical-vapor-deposited tantalum pentaoxide dielectric film capacitors in stacked DRAM cells. Dielectric leakage was reduced by biasing the capacitor plate electrode to a voltage lower than the conventionally used value of V/sub cc//2. Ta/sub 2/O/sub 5/ films with 3.9 nm effective gate oxide, 8.5 fF//spl mu/m/sup 2/ capacitance and <0.3 /spl mu/A/cm/sup 2/ leakage at 100/spl deg/C and 3.3 V supply are demonstrated.<>     

Effects of interstitial oxygen defects at HfO/sub x/N/sub y//Si interface on electrical characteristics of MOS devices

Effects of the defects at high-/spl kappa/ dielectric/Si interface on the electrical characteristics of MOS devices are important issues. To study these issues, a low defect (denuded zone) at Si surface was formed by a high-temperature annealing in hydrogen atmosphere in this paper. Our results reveal that HfO/sub x/N/sub y/ demonstrates significant improvement on the electrical properties of MOS devices due to its low amount of the interstitial oxygen [O/sub i/] and the crystal-originated particles defects as well as small surface roughness at HfO/sub x/N/sub y//Si interface. The current-conduction mechanism of the HfO/sub x/N/sub y/ film at the low- and high-electrical field and high-temperature (T>100/spl deg/C) is dominated by Schottky emission and Frenkel-Poole (FP) emission, respectively. The trap energy level involved in FP conduction was estimated to be around 0.5eV. Reduced gate leakage current, stress-induced leakage current and defect generation rate, attributable to the reduction of defects at HfO/sub x/N/sub y//Si interface, were observed for devices with denuded zone. The variable rise and fall time bipolar-pulse-induced current technique was used to determine the energy distribution of interface trap density (D/sub it/). The results exhibit that relatively low D/sub it/ can be attributed to the reduction of defects at Si surface. By using denuded zone at the Si surface, HfO/sub x/N/sub y/ has demonstrated significant improvement on electrical properties as compared to SiO/sub x/N/sub y/.     

Very high density RF MIM capacitors (17 fF//spl mu/m/sup 2/) using high-/spl kappa/ Al/sub 2/O/sub 3/ doped Ta/sub 2/O/sub 5/ dielectrics

Using high-/spl kappa/ Al/sub 2/O/sub 3/ doped Ta/sub 2/O/sub 5/ dielectric, we have obtained record high MIM capacitance density of 17 fF//spl mu/m/sup 2/ at 100 kHz, small 5% capacitance reduction to RF frequency range, and low leakage current density of 8.9/spl times/10/sup -7/ A/cm/sup 2/. In combination of both high capacitor density and low leakage current density, a very low leakage current of 5.2/spl times/10/sup -12/ A is calculated for a typical large 10 pF capacitor used in RF IC that is even smaller than that of a deep sub-/spl mu/m MOSFET. This very high capacitance density with good MIM capacitor characteristics can significantly reduce the chip size of RF ICs.     

High-k Al/sub 2/O/sub 3/ gate dielectrics prepared by oxidation of aluminum film in nitric acid followed by high-temperature annealing

A simple, cost-effective, and room temperature process was proposed to prepare high-k gate dielectrics. An aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric was prepared by oxidation of ultrathin Al film in nitric acid (HNO/sub 3/) at room temperature then followed by high-temperature annealing in O/sub 2/ or N/sub 2/. The substrate injection current behavior and interface trap-induced capacitance were introduced to investigate the interfacial property between the gate dielectric and Si substrate. Al/sub 2/O/sub 3/ gate dielectric MOS capacitors with and without initial SiO/sub 2/ layers were characterized. It was shown that the Al/sub 2/O/sub 3/ gate dielectrics with initial oxide exhibit better electrical properties than those without. The 650/spl deg/C N/sub 2/-POA Al/sub 2/O/sub 3/-SiO/sub 2/ sample with an equivalent oxide thickness of 18 /spl Aring/ exhibits three orders of magnitude reduction in gate leakage current in comparison with the conventional thermal SiO/sub 2/ sample.     

Electrical properties of Ta/sub 2/O/sub 5/ gate dielectric on strained-Si

High dielectric constant (high-k) thin Ta/sub 2/O/sub 5/ films have been deposited on tensilely strained silicon (strained-Si) layers using a microwave plasma enhanced chemical vapour deposition technique at a low temperature. The deposited Ta/sub 2/O/sub 5/ films show good electrical properties as gate dielectrics and are suitable for microelectronic applications. The feasibility of integration of strained-Si and high-k dielectrics has been demonstrated.     

HfTiO氮化退火对MOS器件电特性的影响

采用磁控溅射方法,在Si衬底上淀积HfTiO高k介质,研究了NO、N2O、NH3和N2不同气体退火对MOS电特性的影响。结果表明,由于NO氮化退火能形成类SiO2/Si界面特性的HfTiSiON层,所制备的MOS器件表现出优良的电特性,即低的界面态密度、低的栅极漏电和高的可靠性。根据MOS器件栅介质(HfTiON/HfTiSiON)物理厚度变化(ΔTox)和电容等效厚度变化(ΔCET)与介质(HfTiON)介电常数的关系,求出在NO气氛中进行淀积后退火处理的HfTiON的介电常数达到28。     

Direct nitridation of high-k metal oxide thin films using argon excimer sources

Reported, for the first time, is the formation of metal oxynitride thin films via direct nitridation of the metal oxide films by active nitrogen species generated from molecular nitrogen with argon excimer sources. Preliminary results on TaO/sub x/N/sub y/ thin films formed from 9 nm Ta/sub 2/O/sub 5/ films have exhibited excellent electrical properties with three orders magnitude lower leakage current density being achieved and 25% higher accumulation capacitance being obtained. The nitridation process for a specific film thickness can be optimised by adjusting the VUV irradiation time to achieve both increased accumulation capacitance and improved leakage property, without the need for the use of H/sub 2/O, NH/sub 3/ or high temperature substrate heating.     

RF溅射制备Ta2O5薄膜及其电学性能的研究

高介电常数薄膜广泛应用于动态随机存储器中.本文主要采用反应溅射在Si基体上制备Ta2O5薄膜,研究了在25～100nm厚度范围内薄膜的电学性能.讨论了不同退火时间对Ta2O5薄膜结构和性能的影响,测量了退火后薄膜的漏电流,并计算出其介电常数.     

Al/sub 2/O/sub 3/-Ge-on-insulator n- and p-MOSFETs with fully NiSi and NiGe dual gates

High-/spl kappa/ Al/sub 2/O/sub 3//Ge-on-insulator (GOI) n- and p-MOSFETs with fully silicided NiSi and germanided NiGe dual gates were fabricated. At 1.7-nm equivalent-oxide-thickness (EOT), the Al/sub 2/O/sub 3/-GOI with metal-like NiSi and NiGe gates has comparable gate leakage current with Al/sub 2/O/sub 3/-Si MOSFETs. Additionally, Al/sub 2/O/sub 3/-GOI C-MOSFETs with fully NiSi and NiGe gates show 1.94 and 1.98 times higher electron and hole mobility, respectively, than Al/sub 2/O/sub 3/-Si devices, because the electron and hole effective masses of Ge are lower than those of Si. The process with maximum 500/spl deg/C rapid thermal annealing (RTA) is ideal for integrating metallic gates with high-/spl kappa/ to minimize interfacial reactions and crystallization of the high-/spl kappa/ material, and oxygen penetration in high-/spl kappa/ MOSFETs.     

氧氩流量比对高介电薄膜Ta_2O_5电学性能的影响

利用反应溅射的方法沉积Ta2O5高介电薄膜,研究了溅射过程中氧气与氩气的体积流量比Ψ(O2:Ar)对薄膜电学性能的影响。结果表明,制备的薄膜退火后为多晶态四方结构的β-Ta2O5。随着Ψ(O2:Ar)的增大,薄膜的沉积速率逐渐减小,积累电容逐渐增大,等效氧化层厚度逐渐减小,平带电容增大,氧化层中可动离子电荷密度逐渐减小。当Ψ(O2:Ar)=6:5时,所沉积Ta2O5薄膜的相对介电常数r最大,为38.32;当Ψ(O2:Ar)=2:5时,漏电流密度最小,仅为7.7×10–7A/cm2。     

Effects of post-deposition annealing on the electrical propertiesand reliability of ultrathin chemical vapor deposited Ta2O5 films

This paper reports the effects of post-deposition rapid thermal annealing on the electrical characteristics of chemical vapor deposited (CVD) Ta₂O₅ (~10 nm) on NH₃-nitrided polycrystalline silicon (poly-Si) storage electrodes for stacked DRAM applications. Three different post-deposition annealing conditions are compared: a) 800°C rapid thermal O₂ annealing (RTO) for 20 sec followed by rapid thermal N₂ annealing (RTA) for 40 sec, b) 800°C RTO for 60 sec and c) 900°C RTO for 60 see. Results show that an increase in RTO temperature and time decreases leakage current at the cost of capacitance. However, over-reoxidation induces thicker oxynitride formation at the Ta₂O₅/poly-Si interface, resulting in the worst time-dependent dielectric breakdown (TDDB) characteristics