Highly configurable capacitive interface circuit for tri‐axial MEMS microaccelerometer

A highly configurable capacitive interface circuit with on‐chip calibration capability for tri‐axial microaccelerometer is presented. The capacitive interface circuit is designed to be programmable, and can reduce the output errors due to the parasitic capacitance variations and process variations. The capacitive sensing chain adopts the chopper stabilisation, and includes the front‐end charge amplifier with three 10‐bit programmable capacitor arrays, 9‐bit digital‐to‐analogue converter and 10‐bit programmable gain amplifier. The calibration coefficients are stored to the on‐chip erasable programmable read only memory. The outputs from the three‐channel capacitive sensing chain are converted to digital signal by the integrated 14‐bit algorithmic analogue‐to‐digital converter. After calibrating the 48 samples, all the samples meet the desired specification range. Before the calibration, the errors of the average values of the output offset and gain were +47.1% and ?85.9%, respectively. After the calibration, however, the errors of the average values of the output offset and gain are reduced to be 0.3% and 0.5%, respectively. The resolutions for x/y‐axis and z‐axis are measured to be 326 and 728?µg, respectively.     

Patent Abstracts

Presents a summary of twenty patents and includes abstracts as well as diagrams, where applicable. Covers such technologies, techniques, and/or methodologies as: a tuned continuous time delay FIR equalizer; linearity enhancement for capacitive sensors; method and apparatus for amplifier linearization using adaptive predistortion; method and apparatus for an LNA with high linearity and improved gain control; a switchless multi-resonant, multi-band power amplifier; a multi-stage variable gain amplifier utilizing overlapping gain curves to compensate for log-linear errors;method and apparatus for static phase offset correction; low ohmic techniques for MOS transistors;a high-accuracy continuous continuous duty-cycle correction circuit; a carbon nanotube based light sensor; and a harmonic rejection mixer and method of operation.     

A new capacitor-ratio and offset independent residue amplifier

Matching accuracy of capacitors at the first stage of the residue amplifier limits the overall resolution in pipelined analog-to-digital converters. A new residue amplifier is presented in this paper which is inherently insensitive not only to capacitor ratio but also to amplifier offset voltage and gain errors. Experimental and simulation results are provided to show how the proposed technique senses and compensates these errors.     

High-speed digital-to-analogue convertor using passiveswitched-capacitor algorithmic conversion

A purely passive parasitic-compensated switched-capacitor circuit is shown to implement a simple signal conversion algorithm consisting of a mere charge division between equal valued capacitors. Such a circuit is the core of the new digital-to-analogue convertor described, and which is particularly suitable for high-frequency applications. Appropriate design conditions are established to render the overall circuit insensitive to the offset voltage and finite DC gain errors of the amplifier     

A low-power 10-bit 250-KSPS cyclic ADC with offset and mismatch correction

A low power 10-bit 250-k sample per second(KSPS) cyclic analog to digital converter(ADC) is presented. The ADC’s offset errors are successfully cancelled out through the proper choice of a capacitor switching sequence.The improved redundant signed digit algorithm used in the ADC can tolerate high levels of the comparator’s offset errors and switched capacitor mismatch errors.With this structure,it has the advantages of simple circuit configuration,small chip area and low power dissipation.The cyclic ADC manufactured with the Chartered 0.35μm 2P4M process shows a 58.5 dB signal to noise and distortion ratio and a 9.4 bit effective number of bits at a 250 KSPS sample rate.It dissipates 0.72 mW with a 3.3 V power supply and occupies dimensions of 0.42×0.68 mm~2.     

Walk error minimisation by resonance-based laser pulse timing detection

A method for timing point detection in a laser pulse is presented. A pulse shaping circuit is placed at the input of the receiver to achieve a large dynamic range without gain control and timing errors caused by signal clipping. A parallel resonant circuit is proposed as the shaping circuit.     

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control(AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented.The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips.What’s more,a novel DC offset cancellation(DCOC) circuit with an HPCF(high pass cutoff frequency) less than 10 kHz is proposed.The AGC is fabricated by a 0.18μm CMOS process.Under analog control mode,the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz.Under digital control mode,through a 5-bit digital control word,the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB.The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV,while the offset voltage of 40 mV is introduced into the input.The overall power consumption is less than 3.5 mA,and the die area is 800×300μm~2.     

Area-efficient gain- and offset-compensatedvery-large-time-constant SC integrator

A novel gain- and offset-compensated (GOC) charge-differentiating (CD) SC integrator is presented. The resulting gain, phase and offset errors are considerably smaller than those of previously proposed non-GOC and GOC CD very-large-time-constant (VLT) integrators     

A simple inductance simulation scheme and its application in data communications

The properties of a circuit proposed earlier for the realization of an inductance using two unity gain amplifiers are first studied and an important application of the present circuit for delay equalization in data communications is also presented.     

DMR +: An efficient alternative to TMR to protect registers in Xilinx FPGAs

Registers are one of the circuit elements that can be affected by soft errors. To ensure that soft errors do not affect the system functionality, Triple Modular Redundancy (TMR) is commonly used to protect registers. TMR can effectively protect against errors affecting a single flip-flop and has a low overhead in terms of circuit delay. The main drawback of TMR is that it requires more than three times the original circuit area as the flip-flops are triplicated and additional voting logic is inserted. Another alternative is to protect registers using Error Correction Codes (ECCs), but those typically require a large circuit delay overhead and are not suitable for high speed implementations. In this paper, DMR + an alternative to TMR to protect registers in FPGAs, is presented. The proposed scheme exploits the FPGA structure to achieve a reduction in the FPGA resources (LUTs and Flip-Flops) at the cost of a certain overhead in delay. DMR + can correct all single bit errors like TMR but is more vulnerable to multiple bit errors. To evaluate the benefits, the DMR + technique has been implemented and compared with TMR considering standalone registers and also some simple designs.     

Group Delay Equalized UWB InGaP/GaAs HBT MMIC Amplifier Using Negative Group Delay Circuits

A negative group delay (NGD) circuit has been employed to equalize a group delay variation in a broadband ultra-wideband (UWB) InGaP/GaAs heterojunction bipolar transistor (HBT) monolithic microwave integrated circuit (MMIC) amplifier. Using the NGD circuit, a part of a salient group delay characteristic in the operation band of broadband amplifiers can be suppressed without an increase of the entire group delay. The MMIC amplifier has a steep group delay increase in the lower frequency region of the full-band UWB band (3.1-10.6 GHz) due to the sum of phase variations near the cutoff frequencies of the HBTs. The NGD circuit has been inserted to reduce this increase of the group delay in the UWB band. By adding a three-cell NGD circuit while considering input and output matching at the input side of the MMIC amplifier, the group delay variation is decreased by 78%. However, gain was also decreased by insertion of the multistage NGD circuit. In an attempt to avoid this decrease in gain, a one-cell NGD circuit was inserted into the feedback loop of the MMIC amplifier, and as a result, we were able to decrease the group delay variation by 79%, with minimal gain deterioration.     

A 2.5-V 56-mW baseband chain in a multistandard TV tuner for mobile and multimedia applications

This paper presents post-layout simulated results of an analog baseband chain for mobile and multimedia applications in a 0.13-μm SiGe BiCMOS process.A programmable 7th-order Chebyshev low pass filter with a calibration circuit is used in the analog baseband chain,and the programmable bandwidth is 1.8/2.5/3/3.5/4 MHz with an attenuation of 26/62 dB at offsets of 1.25/4 MHz.The baseband programmable gain amplifier can achieve a linear 40-dB gain range with 0.5-dB steps.Design trade-offs are carefully considered in designing the baseband circuit,and an automatic calibration circuit is used to achieve the bandwidth accuracy of 2%.A DC offset cancellation loop is also introduced to remove the offset from the layout and self-mixing,and the remaining offset voltage is only 1.87 mV.Implemented in a 0.13-μm SiGe technology with a 0.6-mm~2 die size,this baseband achieves IIP3 of 23.16 dBm and dissipates 22.4 mA under a 2.5-V supply.     

Sensing circuit for on-line detection of delay faults

A sensing circuit for on-line testing of delay faults is presented. It can be used to monitor the outputs of circuits that are either general, or designed to be self-checking with respect to steady-state errors. Detailed analyses of the proposed circuit have shown that it is preferable to alternate solutions from the point of view of both the accuracy and the self-testing capability that make it suitable for self-checking applications. Checking architectures for delay faults, making use of the proposed sensing circuit and of standard checkers, are presented     

Cancellation technique to reduce intercarrier interference in OFDM

Orthogonal frequency division multiplexing (OFDM) systems are sensitive to frequency errors, which cause intercarrier interference among subcarriers. A new cancellation method to reduce the effects of frequency offset errors is presented. The main feature is to map each data symbol a_k which is to be transmitted onto a pair of non-adjacent subcarriers, with weightings +1 and -1, rather than to a single subcarrier. The carrier-to-interference ratio gain of the proposed method over normal OFDM varies between 10 to 30 dB. This method also offers a frequency diversity effect in a multipath fading channel     

A second-order high-resolution incremental A/D converter withoffset and charge injection compensation

Measurement and instrumentation applications require absolute accuracy, e.g. offset and gain errors cannot be tolerated. These applications are characterized by DC performance such as differential and integral nonlinearities, offset and gain errors, and they often require high resolution. The second-order incremental A/D converter, which makes use of sigma-delta modulation associated with a simple digital filter, is capable of achieving such requirements. Experimental results of circuits fabricated in a SACMOS 3-μm technology indicate that 15-bit absolute accuracy is easily achievable, even with a low reference voltage     

一种新的并行交替采样系统误差估计方法

并行交替采样系统的性能依赖于各通道的精确配合,相对于传统单通道采样系统,其面临更多的系统误差源.未补偿的失配误差将导致采样波形非线性失真、输出信噪比降低以及无伪峰动态范围损失等.本文提出了一种新的并行交替采样系统误差校正方法,在频域利用相邻频率点输出矢量对应信号子空间的旋转关系和正交投影矩阵的唯一性,实现增益误差以及时基误差的精确估计.该方法无需迭代,估计精度较高,对噪声以及偏置误差稳健,并且可以同时完成信号重构.仿真数据的处理结果验证了本文方法的有效性.     

Effects of inductance on the propagation delay and repeaterinsertion in VLSI circuits

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale     

A programmable gain amplifier with a DC offset calibration loop for a directconversion WLAN transceiver

A high-linearity PGA(programmable gain amplifier) with a DC offset calibration loop is proposed.The PGA adopts a differential degeneration structure to vary voltage gain and uses the closed-loop structure including the input op-amps to enhance the linearity.A continuous time feedback based DC offset calibration loop is also designed to solve the DC offset problem.This PGA is fabricated by TSMC 0.13μm CMOS technology.The measurements show that the receiver PGA(RXPGA) provides a 64 dB gain range with a step of 1 dB,and the transmitter PGA(TXPGA) covers a 16 dB gain.The RXPGA consumes 18 mA and the TXPGA consumes 7 mA (I and Q path) under a 3.3 V supply.The bandwidth of the multi-stage PGA is higher than 20 MHz.In addition,the DCOC(DC offset cancellation) circuit shows 10 kHz of HPCF(high pass cutoff frequency) and the DCOC settling time is less than 0.45μs.     

An improved sampled-data current-mode-control model which explainsthe effects of control delay

A new sampled-data model for the current-mode controlled buck converter includes for the first time the effects of delay in the pulse-width-modulator (PWM). Modified z-transforms are used in this new model for constant frequency trailing-edge modulation. Realistic amounts of delay are found to be particularly significant when the buck converter is operating in the continuous conduction mode near the discontinuous conduction mode boundary. The new model is used to predict the loop gain measurements obtained with the “digital modulator” and with conventional measurement techniques. It is shown that conventional loop gain measurement techniques are insufficient to measure the loop gain in this region of operation. It is also shown that the digital modulator can add a significant amount of delay, thereby altering the loop gain of the circuit being measured. Unlike the case of a continuous system, PWM delay is found to significantly alter the low-frequency loop gain magnitude of this sampled-data system. The new model predicts the boundary condition for sub-harmonic instability, and reduces to Ridley's current-mode control model for the case of zero delay. Experimental corroboration is presented     

Some Design Aspects of a Two-Stage Rail-to-Rail CMOS Op Amp

A two-stage low-voltage CMOS op amp with rail-to-rail input and output voltage ranges is presented. The circuit uses complementary differential input pairs to achieve the rail-to-rail common-mode input voltage range. The differential pairs operate in strong inversion, and the constant transconductance is obtained by keeping the sum of the square roots of the tail currents constant. Such an input stage has an offset voltage which depends on the common input voltage level, resulting in a poor common-mode rejection ratio. Therefore, special attention has been given to the reduction of the op amp's systematic offset voltage. Gain-boost amplifiers are connected in a special way to provide not only an increase of the low-frequency open-loop gain, but also to provide a significant reduction of the systematic offset voltage.