基于IP核的滤波器复用模块的设计和实现

介绍了一种基于FIRIP核的抽取滤波器复用模块的设计和实现。FIRIP核可以进行灵活的参数设计,实现不同应用的滤波器设计。以FIRIP核为对象进行FIR滤波器算法的参数选择设计,并以128路的抽取滤波算法为例,在充分考虑到了滤波器特性、FPGA资源分配的诸多因素基础上,利用FIRIP核构建了合理的抽取滤波和复用模块,完成了128路信号的抽取滤波设计和实现。     

一种基于多相滤波器的高速匹配滤波器方法

提出了一种基于多相滤波器的高速匹配滤波器方法,这种方法在滤波器多相分解和整数倍抽取的基础上进行数学推导,不对输入信号做任何处理,仅将多相滤波器组的系数和前后顺序略做调整,即可实现滤波后波形中任意采样点的抽取.不仅具有多相滤波降低运算速率的优点,而且在匹配滤波后不减少采样点的个数,提高后续处理的同步精度.该方法误差小,实现简单,在宽带通信系统中具有良好的应用前景.     

半带滤波器的仿真

半带滤波器(Half-Band Filter)在多速率信号处理中有着特别重要的位置,因为这种滤波器特别适合D=2M倍(即2的幂次方倍)的抽取或者内插,而且计算效率高,实时性强。专门分析半带滤波器的时、频特性以及在抽取(或者内插)中的应用与设计方法。     

4路多相信号半带抽取滤波器优化实现结构

高速FIR滤波器的4路多相实现结构工作的采样速率是单路串行实现结构的4倍,针对4路多相信号半带抽取滤波器直接实现结构计算复杂度大这一问题,提出了一种4路多相信号半带抽取滤波器的优化实现结构。推导得到4路多相信号FIR滤波器优化实现结构;在此基础上,分析不同输出组合的计算复杂度,给出4路多相信号半带抽取滤波器的优化实现结构。对于4路多相信号半带抽取滤波器,仿真结果表明,提出的优化实现结构的计算复杂度约为直接实现结构的75%,验证了其优越性。     

软件无线电中的多速率信号处理

介绍了软件无线电和多速率信号处理的概念,多速率信号处理能够改变软件无线电系统不同节点处的信号速率。多速率信号处理最基本的两种方法是抽取和内插,分析了他们的原理,并给出了相应的多相滤波结构。多相滤波器组使各个支路滤波器的阶数降至1/D(1/I),是实现信号实时处理的有效途径。     

基于ASIC的并行流水线级联半带滤波器设计

针对高速ADC数字下变频中的实时滤波需求,设计了一种基于ASIC的并行流水线级联半带滤波器。首先根据ADC输出数据速率远高于DSP处理能力的工程问题设计了可以实现16、8、4、2倍抽取的四级级联结构,然后在传统串行滤波器基础上进行了4路并行流水线结构理论推导,该方法降低了运算速度,能够实现高速数据实时处理。在此基础上采用Verilog HDL实现了RTL级描述并采用65 nm CMOS工艺成功流片,仿真和测试结果显示,设计的滤波器能够在保证计算精度的同时实现1 GHz高速采样数据的实时滤波及16、8、4、2倍抽取。     

基于FPGA的数字化正交解调接收机最优设计

结合抽取滤波器的多项滤波结构,在一定条件下,推导出了一种含抽取正交解调接收机最优结构设计方法。在FPGA乘法器资源相同的条件下,采用最优结构设计的接收机内部FIR滤波器阶数比直接实现形式高了近4倍。最后给出了设计实例。     

多模无线移动终端中的采样速率转换

采样速率转换是基于软件无线电思想的多模无线移动终端设计中的一项关键技术。有理数采样速率转换可以划分为整数倍和分数倍采样率转换。实现整数倍采样率转换可以采用时不变滤波器 ,然而实现分数倍采样率转换一般需要采用较复杂的时变滤波器。本文以实现整数倍抽取内插的CIC滤波器为基础 ,提出了一种实现分数倍采样率转换的时变CIC滤波结构。     

DVB-T接收系统中DDC的设计

针对DVB-T接收机的中频数据进行数字下变频(DDC)处理。分析了引入噪声的原因,同时提出解决方案。为了便于ASIC实现,在设计模块时除了考虑功能实现还尽可能做到结构简化。在设计数控振荡器(NCO)时采用了CORDIC算法,在设计抽取滤波器时采用多相结构的半带滤波器级联,通过MATLAB仿真证明该系统能有效消除镜频干扰及噪声影响,恢复出符合系统要求的数据。     

宽带数字接收机的信道化设计

针对宽带数字信道化接收机中的信道化和抽取技术,分析了复信号多相滤波器无盲区算法及其数学模型,给出了信号的全概率捕获方法。同时,根据此数学模型,提出了复多相滤波器的FPGA设计方法。该方法根据模型中信道数与抽取倍数之间的关系,并利用可定制模块和时序的配合来完成延迟和抽取功能。而用乘加单元完成多相分量的滤波运算,同时用专用IP核完成FFT。整个模块采用乒乓RAM的设计思想和流水线结构。实验结果表明,该方法与一般旋转开关方法不同,它能够实现信道数不等于抽取倍数的延迟和抽取。     

一种应用于LTE协议的高速ΣΔADC的降采样滤波器

设计了一种应用于LTE协议的20 MHz带宽、12-bit精度ΣΔ模数转换器中的降采样低通数字滤波器,该滤波器采用一级梳状滤波器与两级半带滤波器级联的结构。基于低功耗设计考虑,降采样滤波器采用多相分解、CSD编码等技术,并对片内时钟偏差、串扰等进行优化以提高芯片的产率和可靠性。该设计在SMIC 00.13μm 1P8M标准CMOS工艺流片,测试结果表明芯片工作在11.2 V电源电压和500 MHz时钟频率时,在20 MHz的信号带宽内,带本滤波器的ΣΔADC的峰值SNDR和SNR分别为64.16 dB和64.71 dB,滤波器的功耗为4.8 mW。     

Wideband monopole antenna for DVB-T applications

A novel asymmetric fork-like monopole antenna for digital video broadcasting-terrestrial (DVB-T) signal reception for application in the UHF band is presented. The proposed antenna consists of two two-branch strip monopoles on a rectangular ground plane with a concave. The concavity in the ground pattern serves as an effective means for the gap between the radiating element and the ground plane for impedance matching. The influence of various parameters on antenna characteristics has been investigated. Results show a wide bandwidth of 461 MHz (451?912 MHz) or 70% of DVB-T centred frequency (655 MHz). The proposed antenna has omnidirectional radiation patterns in the yz-plane. Details of the proposed antenna design and experimental results of the constructed prototypes are presented.     

A CMOS quadrature charge-domain sampling circuit with 66-dB SFDR up to 100 MHz

A charge-domain quadrature sampling circuit realization in 0.35 /spl mu/m CMOS is presented. The circuit downconverts a real-valued IF input signal with a nominal frequency of 50 MHz into baseband quadrature components by decimation. Based on multiple integrative sampling of charge, the circuit integrates a 192-tap complex bandpass finite-impulse response filtering function into the sampling operation providing 18 dB of built-in anti-aliasing suppression for the nearest unwanted frequencies aliasing to dc and over 36 dB of image band rejection on the 923-kHz 3-dB bandwidth of the circuit. The measured third-order input intercept point is + 25 dBV at 50 MHz, while the spurious-free dynamic range is more than 66 dB up to 100-MHz IF input frequency. The power consumption excluding output buffers is 30 mW from a 3.3-V supply.     

A single-chip CMOS IF-band converter design for DVB-T receivers

This paper describes a CMOS single-chip IF-band converter (IFC) which is applied in the analog front end circuitry of DVB-T receivers. The proposed IFC is composed of a down-conversion mixer, an automatic gain controller (AGC), and an anti-aliasing filter (AAF). The down-conversion mixer uses a current folded-mirror technique which converts a 36 MHz intermediate frequency (IF) input into a 4.5 MHz baseband signal. The AGC loop applies a novel digital variable gain amplifier (VGA) basing on a g_m-boosting DVGA (digital VGA). A total of three tunable gain stages are cascaded to provide a 70 dB dynamic range. A temperature-compensated 6th order transconductance-C (Gm-C) filter with digitally tunable bandwidth (6, 7, 8 MHz) is used to constitute the proposed AAF. Moreover, a temperature-compensated circuitry is used to neutralize the AAF's bandwidth drifting caused by the temperature variation.     

高速TIADC采集系统中数字下变频电路设计

分析了数字下变频的原理,设计实现了能进行1、2、4、8等可选抽取倍数的高速数字下变频系统。对系统中的混频器和滤波器进行了优化设计。采用基4布斯编码和4-2压缩器,缩短混频器中的关键路径;引入基于Horner法则和子表达式共享的正则有符号数(CSD)编码,减小滤波器的硬件消耗。设计的数字下变频系统用于四通道、560 MHz 14位时间交织模数转换器(TIADC),并基于FPGA完成功能验证。结果表明,当输入信号频率为380 MHz、抽取倍数为8时,I/Q两路信号的无杂散动态范围(SFDR)在90 dB以上。     

一种宽带多模数字抽取滤波器

提出了一种应用于连续时间Σ-Δ ADC的多模数字抽取滤波器。通过采用不同类型滤波器级联结构,合理分配不同级间下采样因子,有效降低了电路复杂度、面积和功耗。通过级间滤波器相互配合,实现了该滤波器的多带宽、多模式功能。基于65 nm CMOS工艺进行后端设计,仿真结果表明,该多模抽取滤波器的工作带宽为20~50 MHz,当工作带宽为20 MHz和50 MHz时,有效位数分别为10.64位和10.48位。     

A CMOS Ripple Detector for Voltage Regulator Testing

This paper presents an RMS based ripple sensor for testing of fully integrated voltage regulators. A DC signal which is proportional to the input ripple amplitude is generated. Final digital pass/fail signal is obtained with a clocked comparator. The sensor can detect a peak-to-peak ripple voltage of up to 50 millivolts on the 1.2 V supply rail and has 220 MHz bandwidth. The sensor is designed using IBM 90 nm CMOS technology and its functionality is verified in Cadence Virtuoso simulation environment.     

低损耗高阻带抑制声表面波滤波器

为了提高雷达信号的接收灵敏度,提出一种低损耗高性能的单相单向换能器,其设计采用了电极宽度控制来实现。发射和接收叉指换能器分别选取适当的加权函数,能得到更低的旁瓣电平。设计制作了中心频率67 MHz,3 dB带宽1 MHz,单向性为21 dB,插损3.8 dB,阻带抑制大于45 dB的低损耗高阻带抑制声表面波滤波器。     

SC filter for RF sampling and downconversion with wideband image rejection

In this paper we present an SC filter for RF downconversion using the direct RF sampling and decimation technique. The circuit architecture is generic and it features high image rejection for wideband signals and good linearity. An SC implementation in 0.13μm CMOS suitable for an RF of 2.4 GHz and 20 MHz signal bandwidth is presented as a demonstrator. Simulation results obtained using Cadence Spectre simulation tools are included.     

A 14 mW 2.5 MS/s 14 bit Σ∆ Modulator Using Split-Path Pseudo-Differential Amplifiers

This paper presents the design and experimental results of a 1.25 MHz signal bandwidth 14 bit CMOS SigmaDelta modulator. With our proposed switched-capacitor split-path pseudo-differential amplifiers, this modulator achieves high power efficiency, high sampling frequency, and small die area. A new signal and reference front-end sampling network eliminates the input common-mode voltage and reduces power consumption and linearity requirement of the opamp. A prototype chip has been designed and fabricated in a 0.25 mum CMOS technology with a core area of 0.27 mm². Experimental results show that an 84 dB dynamic range is achieved over a 1.25 MHz signal bandwidth when clocked at 125 MHz. The power dissipation is 14 mW at 2.4 V including on-chip voltage reference buffers.