Analogue squarer and multiplier based on floating-gate MOStransistors

A simple squarer based on floating-gate MOS transistors is presented. The squarer has rail-to-rail input range with less than 0.5% non-linearity error. Using this squarer single-ended and/or differential signals can be processed without additional circuitry. Also, a four quadrant analogue multiplier can be realised using the proposed squarer. Simulation results are given to verify the theoretical analysis     

A 1.5 V Current-Mode CMOS RMS-to-DC Converter

A very low voltage, current-mode CMOS RMS-to-DC converter is presented. It is fully designed using MOS Translinear techniques. More specifically, its main building blocks are a squarer/divider and a geometric-mean cell which are obtained by using simple second-order MOS Translinear loops in a folded configuration, leading to a very regular and compact implementation. A novel biasing technique is employed for such loops, allowing them to operate at supply voltages as low as 1.5 V. Experimental results for a prototype IC demonstrating the correct operation of the circuit are included.     

A Symmetric Complementary Structure for RF CMOS Analog Squarer and Four-Quadrant Analog Multiplier

A symmetric complementary structure for CMOS analog squarer and four-quadrant multiplier is proposed and analyzed. Analog squarer and a four-quadrant analog multiplier by utilizing the square-algebraic identity in the MOS triode region are presented. The squarer has a symmetric complementary configuration of the push-pull source follower and provides high performance in terms of linearity, power consumption, frequency response and total harmonic distortion (THD). The squarer, with –3 dB bandwidth of 1.3 GHz, had a nonlinearity error less than 1% over input signal range of ±1 V. The multiplier is basically constructed by voltage subtractors (for differential function of inputs) and sum-squaring as well as difference-squaring core circuits (for multiplication of two differential inputs signals). The multiplier has a nonlinearity error less than 1% over ±0.5 V input range. The circuit provides a –3 dB bandwidth higher than 1.3 GHz and exhibits a THD lower than 1% with a 1 V peak-to-peak input voltage, which dissipating 2.6 mW. The second-order effects including mismatch effects are discussed. The proposed circuits will be useful in various RF analog signal-processing applications.     

Novel high-precision current-mode multiplier/divider

In this paper, a method to reduce the second order effects on the circuit performances caused by the small sized MOS transistors is proposed. A current mode square-root circuit, a squarer/divider circuit and a multiplier/divider circuit are designed using this method. Proposed circuits have been simulated with SPICE simulator using 0.35 μm CMOS technology parameters. The main advantages of the proposed circuit are reduced errors of the output current function, a smaller area on the chip, possibility of controlling the output current with the control voltage, operation at higher frequencies and more efficient power consumption. As a result, it can be considered as a useful building block for IC designer.     

FGMOS transistor based low voltage and low power fully programmable Gaussian function generator

In this paper floating gate MOS (FGMOS) transistor based fully programmable Gaussian function generator (GFG) is presented. The circuit combines the exponential characteristics of MOS transistor in weak inversion, tunable property of FGMOS transistor, and its square law characteristic in strong inversion region to implement the GFG. FGMOS based squarer is the core sub circuit of GFG that helps to implement full Gaussian function for positive as well as negative half of the input voltage. FGMOS implementation of the circuit provides low voltage operation, low power consumption, reduces the circuit complexity and increases the tunability of the circuit. The performance of circuit is verified at 0.75 V in TSMC 0.18 μm CMOS, BSIM3 and level 49 technology by using Cadence Spectre simulator. To ensure robustness of the proposed GFG, simulation results for various process corner variations have also been included.     

Switched-Current Filters Revisited: Square-Root Domain Sampled-Data Filters

In this brief, the well-known switched-current (SI) filtering technique is revisited using the concept of the square-root domain (SRD) filtering. It is proved that SI filters are a subclass of the SRD filters, where sampled-data signal processing is performed. This is achieved by considering typical lossless and lossy SRD sampled-data integrator configurations, using a set of complementary SRD operators which are based on the quadratic I-V relationship of MOS transistor operated in the saturation. Circuit examples are given, where linear-domain integrator and third-order filter configurations were derived using appropriate SRD sampled-data building blocks     

多功能AB类四象限模拟乘法器

在AB类电流镜基础上应用跨导线性原理设计出一种新颖的电流平方/电流跟随器,并以该模块为基本单元综合设计出一种多功能的四象限模拟乘法器.该乘法器在内部结构和元件参数不变的情况下,根据输入、输出信号的选择可以实现电压模式和电流模式乘法器.采用TSMC 0.35μm CMOS集成工艺对电路进行PSPICE仿真测试,结果表明提...     

An Analog Squaring Technique Based on Asynchronous Sigma–Delta Modulation

Accurate analog squarers are required for different signal processing functions, such as amplitude modulation, frequency shifting, signal power estimation, and neural and image processing. Transistor-level analog squarers suffer from limited accuracy, particularly in modern deep-submicrometer technology, where the squared law of the MOS transistor in the saturation region is no longer valid. Based on the asynchronous sigma–delta modulator (ASDM), a new circuit that provides the squared value of the input signal is proposed. For slowly varying input signals, the filtered output is a replica of the squared input signal. In this brief, the proposed analog squarer is studied, and the analytical results are validated by simulation in the time domain. The effect of analog imperfections on the accuracy of the squarer is also analyzed by showing that a high signal-to-noise-plus-distortion ratio can be obtained for typical values of the mismatch and up to frequencies near half the maximum frequency of the ASDM limit cycle.      

Very Low Voltage MOS Translinear Loops Based on Flipped Voltage Followers

A novel technique for operating MOS Translinear loops at very low supply voltages is described, based on the use of Flipped Voltage Followers for biasing the loops. The resulting topologies, suited to standard CMOS processes, can be successfully applied to a varied repertory of low-voltage analog circuits, such as squarers, multipliers, filters, oscillators, and RMS-DC converters. Measurement results for a geometric-mean and a squarer/divider circuit demonstrate on silicon the usefulness of this technique.     

MOS switched-capacitor analog sampled-data direct-form recursive filters

A new technique enabling the integration of audio frequency filters using standard MOS technology is described. This approach uses ratioed MOS capacitors, MOS amplifiers and switches to realize precision multiplication, summation, and delay functions. With these elements an analog sampled-data direct-form recursive filter, having the general biquadratic transfer function, was integrated in MNOS technology. This filter had a Q=19/spl plusmn/1 without external trimming and it could be electrically programmed into low-pass, bandpass, and high-pass responses. This biquadratic section can be used as a building block for higher order filters. The direct form switched-capacitor offers some useful advantages in comparison to the switched-capacitor integrator approach. These are the rejection of MOS amplifier noise and power supply noise below one-half the sampling rate, less silicon area especially when implementing high Q poles, and potential for multiplexing two or more filters.     

Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch

Time interleaving is one of the most efficient techniques employed in the design of high-speed sampled-data systems. However, the mismatches appearing among different channels will create distortion tones that will degrade the system performance. This paper presents a detailed analysis of the effect of sampling bandwidth mismatches in the statistical behavior of time-interleaved sampling systems. Closed-form and handy signal-to-noise distortion ratio formulas will also be derived which allow quick evaluation of the system performance, and the MATLAB simulations are provided in order to verify the effectiveness of those formulas. Finally, the corresponding design procedure extracted from the formulas will be further addressed through a design example.      

Switched-current (SI) integrators with reduced effect of transistor mismatches

Switched-current (SI) circuits are widely used for analog sampled-data signal processing, due to their compatibility to the pure digital CMOS process. As their main building blocks are current mirrors, they suffer from the effects of MOS transistor parameters mismatch. In this paper, the Functional Block Diagram (FBD) of already known integrator circuits is modified in such a way that the number of required current mirrors is reduced. Thus, the behavior of the derived integrator topologies, with respect to the effect of MOS transistor parameters mismatch, is improved.A comparison is performed, concerning the performance of the proposed bilinear integrator circuits and those that are already introduced in the literature. For this purpose, a fifth-order Chebyshev lowpass SI filter transfer function was simulated. In the case of the proposed filter configurations, the obtained results show that their performance is improved in terms of the effects of MOS transistor parameters mismatch, DC power dissipation, and total required silicon area.     

A novel high-speed CMOS circuit based on a gang of capacitors

There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from the relatively sluggish operation. In this paper, a circuit that contains a gang of capacitors sharing their charge with each other is proposed as an alternative to long N-channel MOS and P-channel MOS stacks. The proposed scheme is investigated quantitatively and verified by simulation using the 45-nm CMOS technology with V_DD = 1 V. The time delay, area and power consumption of the proposed scheme are investigated and compared with the conventional static CMOS logic circuit. It is verified that the proposed scheme achieves 52% saving in the average propagation delay for eight inputs and that it has a smaller area compared to the conventional CMOS logic when the number of inputs exceeds three and a smaller power consumption for a number of inputs exceeding two. The impacts of process variations, component mismatches and technology scaling on the proposed scheme are also investigated.     

Class AB CMOS analogue squarer circuit

CMOS analogue squarer circuit is presented. A compact pseudo-differential pair insensitive to input common-mode variations leads to class AB operation, hence yielding dynamic currents not bounded by quiescent currents. Measurement results for a 0.5 mum CMOS prototype are provided that verify the correct operation of the circuit.     

Low power FGMOS-based four-quadrant current multiplier circuits

In this paper, low-power, high-speed four-quadrant analog multiplier circuits have been presented, based on simple current squarer circuits. The squarer circuits consist of a floating-gate MOS transistor, operating in saturation region plus a resistor. These multipliers have a unique property of greatly reduced power as they do not have any bias currents. For performance evaluation, the designs are simulated using HSPICE software in 0.18 µm (level-49 parameters) TSMC CMOS technology. Using ± 0.5 V DC supply voltages for the first design, the simulation resulted in a maximum linearity error of 0.8%, the ? 3 dB bandwidth of 635 MHz, the Total Harmonic Distortion of 0.57% (at 1 MHz), and maximum and static power consumption of 40.4 and 5.75 µW, respectively. Corresponding values for the second design with 1 V DC supply voltage are 0.4%, 394.8 MHz, 0.72%, 44 and 11.4 µW, respectively. Furthermore, in order to verify the robustness and reliability of the proposed works, Monte Carlo analysis are performed. For the mentioned analysis, 5% variations in channel width and length, gate oxide thickness and threshold voltage of all transistors and resistance values are considered.     

Switched-current circuit design issues

Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%     

An Energy-Detector for Noncoherent Impulse-Radio UWB Receivers

This study proposes an energy detector for a noncoherent impulse-radio UWB receiver, designed in a 0.18-$mu$ m CMOS technology. The squaring functionality is realized exploiting the quadratic characteristic of MOS transistors, and the deviation from such a characteristic due to short channel effects and device mismatch is carefully considered in the paper. The squared signal is integrated using a Gm-C integrator that is interfaced with the squarer using a flipped voltage follower current sensor as a current to voltage converter. The proposed circuit dissipates 5.4 mW for a receiver sensitivity at the antenna of ${-}$89 dBm. Synchronization is demonstrated at the system level and some considerations on robustness to narrowband interferers are presented.      

A fast parallel squarer based on divide-and-conquer

Fast and small squarers are needed in many applications such as image compression. A new family of high-performance parallel squarers based on the divide-and-conquer method is reported. Our main result was realized for the basis cases of the divide-and-conquer recursion by using optimized n-bit primitive squarers, where n is in the range of two to six. This method reduced the gate count and provided shorter critical paths. A chip implementing an 8-b squarer was designed, fabricated, and successfully tested, resulting in 24 million operations per second (MOPS) using a 2-μm CMOS fabrication technology. This squarer had two additional features: increased number of squaring operations per unit circuit area and the potential for reduced power consumption per squaring operation     

A monolithic adaptive filter

Reports a monolithic adaptive filter which has been realized using purely analog sampled-data MOS and CCD techniques. The filter implements a full Widrow least mean-squares algorithm over 65 data points. Central to this design is a novel, compact analog multiplier/accumulator circuit, which is presented in detail. The 65-point adaptive filter, which is cascadable, dissipates 200 mW from a 15 V supply, and operates at sample rates up to 100 kHz.