FPGA动态可重构理论及其研究进展

近年来,随着微电子技术和计算机技术的发展,尤其是大规模现场可编程门阵列FPGA的出现,实时电路重构技术逐渐成为国际学术界的研究热点;基于FPGA的重构系统具有自适应、自主修复特性,在空间应用中具有非常重要的作用;文章介绍了基于FP-GA动态可重构技术的原理、分类,重点讨论了动态可重构的实现方法及两种技术,并给出了系统重构设计的流程,同时,介绍了基于FPGA动态可重构技术已取得的成功应用,最后展望了FPGA动态可重构技术的发展前景,并指出了有待解决的问题.     

基于模块的动态可重构系统设计

可重构计算是介于通用处理器和ASIC之间的全新计算解决方案,是一种即保留了硬件计算的速度性能,又兼具软件编程情况灵活性的算法实现方式.介绍了基于模块的动态可重构系统设计方法和模块间的通信方式.实现了基于单片Xilinx Virtex-Ⅱ Pro FPGA片上动态自重构系统,可在系统运行时以较短的时间开销灵活加载所需的重构功能模块,充分体现了可重构计算的性能与速度的优势.     

基于最大空闲矩形的可重构资源管理方法

可重构硬件如FPGA的规模和集成度的提高使其承载的硬件任务越来越多,FPGA的动态部分重构能力使任务可在系统运行过程中动态地添加或者删除而不影响其他任务的运行,对可重构硬件的资源管理非常重要。该文提出一种基于任务上边界计算最大空闲矩形的算法,使用这些最大空闲矩形能够有效地管理可重构资源,便于更好地利用具有动态部分重构能力的可重构硬件。     

可重构技术在虚拟仪器中的应用

主要研究以可重构计算技术为基础的虚拟仪器实验系统,系统分为计算机、主控FPGA、可重构FPGA以及仪器端口驱动等部分,采用动态和静态相结合的方式,通过主FPGA选择不同的下载程序以实现对从FPGA的重构;设计计数器及函数发生器两个功能模块对虚拟系统的重构性能进行了验证。可随时更改实验功能,加速产品研发速度并降低产品成本。     

动态部分可重构方法在SDRAM控制器中的应用

动态部分可重构方法应用于FPGA系统设计中,充分利用了FPGA芯片提供的可重配置功能,减小了FPGA芯片的配置时间。通过对可重构方法的研究,提出了基于模块化动态可重构方法应用到SDRAM控制器设计中,给出了重构流程,并对实验结果进行了分析。该方法提高了FPGA芯片的利用率,有效地提高了可重配置计算系统的整体性能。     

基于FPGA的可重构计算技术研究

本文介绍了可重构计算技术的提出和历程,结合器件发展、重构方式和结构模式分析了基于FPGA的可重构计算技术原理,从设计、配置角度探讨了实现技术,并阐述了在多个领域的应用。根据存在的问题,提出了可重构计算技术的发展研究方向。     

动态可重构系统的通信结构研究

动态可重构技术能在一定控制逻辑的驱动下,对全部或部分逻辑资源实现在系统的动态功能变换和硬件的时分复用.本文介绍了可重构体系结构及典型动态可重构结构;详细分析、比较了动态可重构系统4种通信结构的主要性能,指出各自适用领域,并给出一个应用实例;最后探讨了动态可重构技术研究面临的相关问题和发展趋势.     

可重构资源管理及硬件任务布局的算法研究

可重构系统具有微处理器的灵活性和接近于ASIC的计算速度,可重构硬件的动态部分重构能力能够实现计算和重构操作的重叠,使系统能够动态地改变运行任务,可重构资源管理和硬件任务布局方法是提高可重构系统性能的关键.提出了基于任务上边界计算最大空闲矩形的算法(TT-KAMER),能够有效地管理系统的空闲可重构资源;在此基础上使用FF和启发式BF算法进行硬件任务的布局.实验表明,算法能够有效地实现在线资源分配与任务布局,获得较高的资源利用率.     

动态部分可重构系统空闲资源全集管理研究

可重构系统兼具了传统处理器的灵活性和接近于ASIC的计算速度,FPGA的动态部分重构能够实现计算和重构操作的同时进行,使系统能够动态地改变任务的运行。在动态部分可重构系统中,高效的空闲资源管理策略对系统整体性起着非常重要的作用。提出了一种基于单向栈的算法来寻找最大空闲矩形(MFR)。利用可重构计算单元的不同叮值进出单向栈来找到所有最大空闲矩形。通过实验表明,算法通过使用单向找与算法优化,有效地提高了查找空闲资源全集的性能。     

基于FPGA 的局部动态可重构技术研究

可重构技术作为嵌入式系统中软硬件结合的设计方法,在可靠性、系统高集成度方面有很大优势。现场可编辑门 阵列(Field Programmable Gate Array,FPGA)不仅可以满足这些客观需求,还加强了系统的自适应性,降低了开发成本。 文章介绍了动态局部重构的实现方法,并在早期获取部分可重构(Early Access Partial Reconfiguration,EAPR)方法的基础 上加以改进。之后使用 Xilinx 生产的 Virtex-ML403 开发板实现整个设计,验证该方法的有效性,保证系统的稳定,在实 际应用的实现中有利于对资源有效的管理和合理的利用。     

面向可重构计算系统的模块映射算法

为消除重构时间对可重构计算系统性能的影响,针对多重构模块,提出一种基于动态部分可重构技术的顺序型应用程序模块映射算法。利用动态可重构技术的高效性和灵活性,通过隐藏重构时间,达到减少程序执行时间和提高系统性能的目的。基于JPEG编码测试实例的实验结果表明,运用该算法实现的模块映射方案其程序执行速度是软件实现方式的3.31倍,是硬件方式的2.59倍。     

动态重构硬件加速中的性能开销建模

近年来,随着可重构计算方法和可重构硬件特性的不断演进,基于FPGA动态部分重构技术构建运行时可重构加速器已经成为解决传统加速器设计中硬件资源限制问题的重要途径.然而,区别于传统静态重构加速器,FPGA的动态重构开销是影响硬件加速整体性能的重要因素,而目前尚缺少能够在可重构硬件设计的早期阶段进行动态重构开销精确估算的相关...     

A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations

Signal processors exploiting ASIC acceleration suffer from sky-rocketing manufacturing costs and long design cycles. FPGA-based systems provide a programmable alternative for exploiting computation parallelism, but the flexibility they provide is not as high as in processor-oriented architectures: HDL or C-to-HDL flows still require specific expertise and a hardware knowledge background. On the other hand, the large size of the configuration bitstream and the inherent complexity of FPGA devices make their dynamic reconfiguration not a very viable approach. Coarse-grained reconfigurable architectures (CGRAs) are an appealing solution but they pose implementation problems and tend to be application specific. This paper presents a scalable CGRA which eases the implementation of algorithms on field programmable gate array (FPGA) platforms. This design option is based on two levels of programmability: it takes advantage of performance and reliability provided by state-of-the-art FPGA technology, and at the same time it provides the user with flexibility, performance and ease of reconfiguration typical of standard CGRAs. The basic cell template provides advanced features such as sub-word SIMD integer and floating-point computation capabilities, as well as saturating arithmetic. Multiple reconfiguration contexts and partial run-time reconfiguration capabilities are provided, tackling this way the problem of high reconfiguration overhead typical of FPGAs. Selected instances of the proposed architecture have been implemented on an Altera Stratix II EP2S180 FPGA. On this system, we mapped some common DSP, image processing, 3D graphics and audio compression algorithms in order to validate our approach and to demonstrate its effectiveness by benchmarking the benefits achieved.     

Adaptive real-time image processing exploiting two dimensional reconfigurable architecture

Fine grained reconfigurable architectures, like Xilinx field programmable gate arrays (FPGAs) provide a high flexibility through runtime re-programming, called dynamic and partial reconfiguration. This feature allows for runtime adaptation of the system architecture and behavior configured on the FPGA. The exploitation of this feature enables to load video image processing algorithms on-demand in order to adapt the configuration in correspondence to the changing requirements of the application depending on the image content. For high resolution sensor images, this novel computing paradigm can provide a huge benefit in power reduction and performance gain for actual and future embedded electronic systems. This paper presents a two dimensional system approach exploiting dynamic and partial reconfiguration in order to adapt the system architecture to the actual requirements of image processing applications. The methodology of runtime reconfiguration can be exploited beneficially for highly adaptive multiprocessor systems. Such systems, different from the traditional static approach for multi- and many-core architectures have the advantage, for providing computational performance directly linked to the requirements of the application. The architecture presented in this paper allows for adapting the processing elements as well as the communication infrastructure which is a novel 2D switch-based Network-on-Chip. The presented approach follows and extends the actual trend in computer science of using many- and multi-core processors for bridging the gap between required computation performance for future application in the field of image processing.

适用于空间环境下的FPGA容错与重构体系

FPGA极大地提高了电子系统设计的灵活性和通用性，被广泛地应用在各个领域。在空间环境中，FPGA 容易受到SEU的影响而导致内部逻辑的紊乱，系统重构与故障恢复也比较困难。该文提出了一种在星载环境下，使用CPLD对FPGA进行基于错误诊断的容错体系结构设计，兼顾到了系统重构与故障恢复，在实验中取得了较好的效果。     

基于FPGA的拟态服务器设计

随着计算机技术的不断发展,传统架构下的CPU处理能力已无法应对日益多样化的计算处理任务,新型异构计算体系也存在可提升的空间.分析了以“应用决定结构,结构决定效能”为理念,基于多维重构函数化结构与动态多变体运行机制的拟态计算（Mimicry Computing,MC）体系架构,利用FPGA硬件可编程、动态可重构和功耗低的特性,设计了一种基于FPGA的拟态计算服务器,并阐明了该服务器的核心电路设计与关键技术实现.     

Run-time generation of partial FPGA configurations

This paper presents and evaluates a method of generating partial bitstreams at run-time for dynamic reconfiguration of sections of an FPGA. The method is intended for use in adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance. The proposed approach combines partial bitstreams of coarse-grained components to produce a new partial bitstream implementing a given circuit netlist. Topological sorting of the netlist is used to determine the initial positions of individual components, whose placement is then improved by simulated annealing. Connection routing is done by a breadth-first search of the reconfigurable area based on a simplified resource model of the reconfigurable fabric. The desired partial bitstream is constructed by merging together the default bitstream of the reconfigurable area, the relocated partial bitstreams of the components, and the configurations of the switch matrices used for routing. The approach is embodied in a code library that applications can use to create new bitstreams at run-time. For the members of a set of 29 benchmarks (both synthetic and application-derived) having between five and 41 components, the complete process of bitstream generation takes between 8 s and 35 s when running on an embedded PowerPC 405 microprocessor clocked at 300 MHz.     

基于动态局部重配置的FPGA抗辐射模拟

提出一种与具体硬件结构无关、基于权重的错误注入模型,用于准确模拟基于SRAM的现场可编程门阵列抗辐射性能。提出基于JTAG边界扫描技术和动态局部重配置的错误注入模拟平台。实验结果证明,由该软件模型和硬件平台组成的错误注入系统具有良好通用性,能更准确、高效地进行模拟,且成本较低。