1/f noise and radiation effects in MOS devices

An extensive comparison of the 1/f noise and radiation response of MOS devices is presented. Variations in the room-temperature 1/f noise of unirradiated transistors in the linear regime of device operation correlate strongly with variations in postirradiation threshold-voltage shifts due to oxide trap charge. A simple number fluctuation model has been developed to semi-quantitatively account for this correlation. The 1/f noise of irradiated n-channel MOS transistors increases during irradiation with increasing oxide-trap charge and decreases during postirradiation positive-bias annealing with decreasing oxide-trap charge. No such correlation is found between low-frequency 1/f noise and interface-trap charge. The noise of irradiated p-channel MOS transistors also increases during irradiation, but in contrast to the n-channel response, the p-channel transistor noise magnitude increases during positive-bias annealing with decreasing oxide-trap charge. A qualitative model involving the electrostatic charging and discharging of border traps, as well as accompanying changes in trap energy, is developed to account for this difference in n- and p-channel postirradiation annealing response. The correlation between the low-frequency 1/f noise of unirradiated devices and their postirradiation oxide-trap charge suggests noise measurements can be used as a nondestructive screen of oxide trap charge related failures in discrete MOS devices and for small scale circuits in which critical transistors can be isolated. It also suggests that process techniques developed to reduce radiation-induced-hole trapping in MOS devices can be applied to reduce the low-frequency 1/f noise of MOS circuits and devices. In particular, reducing the number of oxygen vacancies and vacancy complexes in the SiO ₂ can significantly reduce the 1/f noise of MOS devices both in and outside a radiation environment     

A low-noise amplifier with automatic gain control and anticlipping control in CMOS technology

A CMOS low-noise amplifier (LNA) with two variable gain ranges of 6 and 9 dB is presented. Variable gain is realized by using linearized MOS resistive circuits (MRCs) as voltage-controlled resistors. One of these resistors is located in the feedback loop of a transresistance output stage and the other is in the bias current generator of the transconductance input stage. Using compatible lateral bipolar transistors (CLBTs) in the fully differential transconductance input stage, the circuit takes advantage of the linear dependence of transconductance on bias current. The equivalent noise is 14 nV/ square root Hz and free from 1/f noise in the voice band. The circuit was integrated in a 2- mu m CMOS process and has an active area of 0.8 mm/sup 2/.<>     

Noise in DMOS transistors in a BICMOS-technology

An experimental and theoretical study of the 1/f noise and the thermal noise in double-diffused MOS (DMOS) transistors in a BICMOS-technology has been carried out. By using an analytical model that consists of an enhancement MOS transistor in series with a depletion MOS transistor and a resistance, and by attributing noise sources to each device, the noise in DMOS devices is simulated accurately. Three distinct regions of operation are defined: enhancement transistor control, depletion transistor control and the linear region. In the first region, the noise is strictly determined by the enhancement transistor. It was found that the 1/f noise in this region is caused by mobility fluctuations and is very low. In the depletion transistor control region both transistors influence the total noise. Here the 1/f noise is dominated by the depletion transistor. The series resistance is only of importance in the linear region     

The impact of device type and sizing on phase noise mechanisms

Phase noise mechanisms in integrated LC voltage-controlled oscillators (VCOs) using MOS transistors are investigated. The degradation in phase noise due to low-frequency bias noise is shown to be a function of AM-PM conversion in the MOS switching transistors. By exploiting this dependence, bias noise contributions to phase noise are minimized through MOS device sizing rather than through filtering. NMOS and PMOS VCO designs are compared in terms of thermal noise. Short-channel MOS considerations explain why 0.18-/spl mu/m PMOS devices can attain better phase noise than 0.18-/spl mu/m NMOS devices in the 1/f/sup 2/ region. Phase noise in the 1/f/sup 3/ region is primarily dependent upon the upconversion of flicker noise from the MOS switching transistors rather than from the bias circuit, and can be improved by decreasing MOS switching device size. Measured results on an experimental set of VCOs confirm the dependencies predicted by analysis. A 5.3-GHz all-PMOS VCO topology demonstrates measured phase noise of -124 dBc/Hz at 1-MHz offset and -100dBc/Hz at 100-kHz offset while dissipating 13.5 mW from a 1.8-V supply using a 0.18-/spl mu/m SiGe BiCMOS process.     

A compact model for flicker noise in MOS transistors for analog circuit design

Designers need accurate models to estimate 1/f noise in MOS transistors as a function of their size, bias point, and technology. Conventional models present limitations; they usually do not consistently represent the series-parallel associations of transistors and may not provide adequate results for all the operating regions, particularly moderate inversion. In this brief, we present a consistent, physics-based, one-equation-all-regions model for flicker noise developed with the aid of a one-equation-all-regions dc model of the MOS transistor.     

Hole-induced 1/f noise increase in MOS transistors

This paper presents experimental evidence for hole-generated 1/f noise traps in gate oxides near the MOS interface. To clarify the microscopic nature of noise traps, 1/f noise is measured in Si MOS transistors in which carriers are intentionally injected into the gate oxides. It was found that 1/f noise increases more rapidly after drain avalanche hot-carrier injection than after channel hot-electron injection. A rapid noise increase is also observed after X-ray irradiation. These results show that the increase in 1/f noise is closely related to holes. We propose a model in which the reaction between holes and oxygen vacancies near the interface creates noise traps, i.e., E' centers and fixed positive charges     

Low-Frequency Noise Partition of Asymmetric MOS Transistors Operating in Linear Regime

The low-frequency noise in asymmetric MOS transistors with graded channel doping from the source to the drain can be partitioned by assuming a series connection of two or more transistors along the device's channel length. The partition explains the noise overshoot at gate biases around the threshold voltage of the composite device. Expressions for the input-referred gate noise voltage are obtained and verified.      

Intrinsic 1/f device noise reduction and its effect on phase noisein CMOS ring oscillators

This paper gives experimental proof of an intriguing physical effect: periodic on-off switching of MOS transistors in a CMOS ring oscillator reduces their intrinsic 1/f noise and hence the oscillator's close-in phase noise. More specifically, it is shown that the 1/f³ phase noise is dependent on the gate-source voltage of the MOS transistors in the off state. Measurement results, corrected for waveform-dependent upconversion and effective bias, show an 8-dB-lower 1/f³ phase noise than expected. It will be shown that this can be attributed to the intrinsic 1/f noise reduction effect due to periodic on-off switching     

Noise associated with charge injection into-a CCD by current integration through a MOS transistor

The noise charge resulting from integrating a noisy current at a CCD input (equivalent to a MOS transistor) is evaluated. The noise contributions of the signal source and of the input transistor can be separated from other components of the CCD noise. Moreover, our measurements show a very good agreement with previously reported 1/f noise results for MOS transistors working in weak or strong inversion regimes.     

用1／f噪声表征MOSFET的负温偏不稳定性

负温偏不稳定性是ＭＯＳ顺件最重要的可靠问题之一。本文实验上发现ＭＯＳＦＥＴ的Ａ／ｆ噪声与其负温偏不稳定性相关，初始１／ｆ噪声谱密度正比于负温偏应力下的跨导退化量。     

A low-frequency noise study of gate-all-around SOI transistors

The low-frequency noise characteristics of both n- and p-type gate-all-around (GAA) SOI MOS transistors are reported and compared with the noise behavior of conventional, partially depleted (PD) SOI transistors. It is shown that the input-referred noise of n-channel GAA transistors is considerably lower than for standard ones, which is related to the higher device transconductance, coupled to the occurrence of volume inversion, P-channel devices have a one order of magnitude lower noise spectral density than n-MOSTs, which is due to the corresponding lower density of interface traps. GAA p-MOSTs tend to have a lower average noise in weak inversion than their standard-SOI counterparts. In strong inversion, the reverse situation is often found. Finally, it is shown that in n-type GAA transistors no kink-related excess noise is observed, which is an additional benefit for using this type of SOI technology     

A study of flicker noise in MOS transistors operated at room and liquid helium temperatures

A study of flicker noise in MOS transistors operated in the linear and non linear regions at room and liquid helium temperatures is proposed. Besides, a theoretical analysis of the drain current noise characteristics is developed in the framework of the mobility fluctuation model as well as of the carrier number fluctuation model. It is shown experimentally that a close correlation between the drain current spectral density and the transconductance squared dependencies with gate voltage (or drain current) and drain voltage is observed in our devices both at room and liquid helium temperatures. Therefore, it is concluded that the carrier number fluctuation model is not only applicable to MOS devices operated at room temperature but also at liquid helium temperature in ohmic and non ohmic regimes. In addition, peculiarities of the drain current noise related to the appearance of a kink effect at liquid helium temperature in the saturation current characteristics are also discussed.     

Theory and experiments of low-frequency generation-recombination noise in MOS transistors

A theoretical model for the generation-recombination (g-r) noise in MOS transistors is presented. This model takes into account the charge induced on all electrodes by the charge fluctuation of the impurity center in the depletion region. The model gives a finite equivalent gate noise resistance at saturation. Gold-doped and no-gold control devices were fabricated to verify the theory experimentally. The drain-voltage dependence of the g-r noise, which is shown to be distinctly different from the 1/f noise and thermal noise, is used to check the theory. Good agreement between theory and experiment is obtained.     

Silicon MOS transconductance scaling into the overshoot regime

Simulations incorporating velocity overshoot are used to derive the dependence of deep-submicrometer MOS transconductance on low-field mobility μ_eff and channel length L_ch. In contract to strict velocity saturation, saturated transconductance departs from a strict μ_eff/L_ch dependence when overshoot is considered. Constraints on μ_eff derived from conventional scaling laws together with strong μ _eff dependencies in these regimes indicate the importance of low-field inversion layer control and optimization. Transconductance in saturation is shown to approach a well-defined limit for very high μ _eff     

Dependence of transconductance on substrate bias in ultrathin silicon-on-insulator MOS transistors

A simple model is presented to explain the dependence of the transconductance on the substrate bias in ultrathin silicon-on-insulator MOS transistors. Good agreement with experimental data is found. The model can also be used to predict the dependence of transconductance on the underlying oxide thickness.<>     

Wide-Linear-Range Subthreshold OTA for Low-Power, Low-Voltage, and Low-Frequency Applications

We propose a novel configuration of linearized subthreshold operational transconductance amplifier (OTA) for low-power, low-voltage, and low-frequency applications. By using multiple input floating-gate (MIFG) MOS devices and implementing a cubic-distortion-term-canceling technique, the linear range of the OTA is up to 1.1 Vpp under a 1.5-V supply for less than 1% of transconductance variation, according to testing results from a circuit designed in a double-poly, 0.8-$muhbox m$, CMOS process. The power consumption of the OTA remains below 1$muW$for biasing currents in the range between 1–200 nA. The offset voltage due to secondary effects (contributed by parasitic capacitances, errors and mismatches of parameters, charge entrapment, etc.) is of the order of a few ten millivolts, and can be canceled by adjusting biasing voltages of input MIFG MOS transistors.     

On the ‘excess white noise’ in MOS transistors

Special silicon MOS transistors are fabricated to demonstrate that the proposed ‘excess white noise’ attributed to the mobility fluctuation does not exist. The previously observed excess noise over the white thermal noise is shown to be caused by a 1/f-type noise component due to noise measurements at insufficiently high frequencies on devices which have very high 1/f noise.     

1/f noise in n-channel silicon-gate MOS transistors

It is found that equivalent gate noise power for l/f noise in n-channel silicon-gate MOS transistors at near zero drain voltage at room temperature is empirically described by two noise terms, which vary asK_{1}(q/C_{ox}) (V_{G} -V_{T})/f and K_{2}(q/C_{ox})^{2}/f, where V_{G}is gate voltage, VTis threshold Voltage, and Coxis gate-oxide capacitance per unit area. Unification of carrier-density fluctuation (McWhorter's model)and mobility fluctuation (Hooge's model) can account for the experimental data. The comparison between the theory and experiment shows that the carrier fluctuation term K2is proportional to oxide-trap density at Fermi-level. The mobility fluctuation term K1is correlated to K2, being proportional toradic K_{2}. The origin of this correlation is yet to be clarified.     

Lithography-independent nanometer silicon MOSFETs on insulator

Future field-effect transistors should have control regions-also called channels or barriers-of a few tens of nanometers to achieve a transconductance of 1 Siemens per mm and beyond, f_T of 100 GHz and safe operating voltages beyond 1 V. This paper presents two approaches for the fabrication of such MOS transistors in silicon on insulator (SOI) on today's average technology lines without resorting to nanometer lithography, but rather using differential doping available in reduced temperature epitaxy and implantation. With 6 nm oxinitride gate dielectrics, inner transconductances of 700 mS/mm at room temperature are reported