0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficientredundancy and enhanced testability

This paper describes the 32-Mb and the 64-Mb embedded DRAM core with high efficient redundancy, which is fabricated using 0.13-μm triple-well 4-level Cu embedded DRAM technology. Core size of 18.9 mm ² and cell efficiency of 51.3% for the 32-Mb capacity, and core size of 33.4 mm² and cell efficiency of 58.1% for the 64-Mb capacity are realized. This core can achieve 230-MHz burst access at 1.0-V power-supply condition by adopting a new data bus architecture: merged shift column redundancy. We implemented four test functions to improve the testability of the embedded DRAM core. It realizes the DRAM core test in a logic test environment     

A 200-MSample/s trellis-coded PRML read/write channel with analogadaptive equalizer and digital servo

A fully integrated partial response maximum likelihood (PRML) read/write IC with analog adaptive equalization operates up to 200 MSample/s. The chip implements both matched spectral null (MSN) trellis and standard PR4 Viterbi detectors in the digital domain as well as digital servo. The device is integrated in a mature 0.7-μm BiCMOS technology, has a die size of 54 mm², and dissipates 2 W with MSN code or 1.5 W with PR4 code at 4.5-V supply and 200 MSample/s     

A fully integrated 0.13-/spl mu/m CMOS mixed-signal SoC for DVD player applications

This paper describes a fully integrated single-chip CMOS mixed-signal system on a chip (SoC) for DVD player applications. It integrates one digital signal processor (DSP), two 32-bit CPUs, three dedicated processing units, a partial response maximum likelihood (PRML) read channel with an analog front end (AFE), and many other subsystems on the same die. The AFE includes a fifth-order G/sub m/-C filter and attains over 66 dB C/N overall. PR(3,4,4,3) structure is employed in the PRML read channel. Owing to the PRML signal processing and the mixed-signal system level optimization in the PRML read channel, less than 10/sup -6/ of bit-error rate (BER) is obtained for the focus offset margins over /spl plusmn/0.5 /spl mu/m. This SoC is fabricated in 0.13-/spl mu/m one-poly six-Cu CMOS technology. It contains 24 million transistors in a 63.87 mm/sup 2/ die and consumes 1.5 W at 40 MSample/s data rate, which corresponds to DVD 1.5 times playback operation mode.     

A 965-Mb/s 1.0-μm standard CMOS twin-pipe serial/parallelmultiplier

This paper presents a two's complement high-speed twin-pipe serial/parallel multiplier architecture which produces y=cd, where c is the parallel coefficient and d is the serial data. The multiplier is based on the twin pipeline (twin-pipe) concept, in which two data bits are processed each clock cycle. The high serial data throughput rate is mainly due to the use of: 1) a novel twin-pipe architecture, 2) new twin-pipe adder types, and 3) a new multiplier circuit structure. A 4-bit high-speed twin-pipe serial/parallel multiplier, on an active area of 0.224 mm², has been designed and fabricated in a 1.0-μm N-well double-metal single-poly CMOS process. Testing of the multiplier shows that the maximal serial data throughput rate is 965 Mb/s at V_dd=5 V     

A 35 Mb/s mixed-signal decision-feedback equalizer for disk drivesin 2-μm CMOS

A 35 Mb/s mixed-signal adaptive decision-feedback equalizer (DFE) has been implemented in a 2-μm CMOS technology. The DFE has four feedback taps for cancelling intersymbol interference (ISI) and one tap for cancelling dc offset. The ISI is cancelled using fully differential analog circuits. Coefficient adaptation is digital, and two adaptation rates are available. The DFE occupies 24 mm² and dissipates 165 mW     

A 455-Mb/s MR preamplifier design in a 0.8-μm CMOS process

In this paper, we present a CMOS preamplifier for use with magnetoresistive (MR) read elements in disk drives. The performance of the CMOS design is competitive with the more expensive current generation of BiCMOS MR preamplifiers. The measured gain for the preamplifier is 43 dB and the measured 3-dB bandwidth is greater than 273 MHz corresponding to a 455-Mb/s data rate. Likewise, the measured input-referred voltage noise is less than 0.57 nV/√Hz, and measured input-referred current noise is less than 10.54 pA/√Hz at an MR bias current of 10 mA, The preamplifier has been implemented in a 0.8-μm 5 V CMOS process and occupies a die area of 1.78×1.78 mm ² In this paper, we introduce a new scheme to reduce current noise below that contributed by a single MOS device, This technique has the potential for even more impact for future submicron processes. We also showed that voltage amplifiers offer lower noise than transimpedance amplifiers for similar gain and bandwidth constraints     

A 3.3-V, 10-b, 25-MSample/s two-step ADC in 0.35-μm CMOS

This paper describes the design of a two-step analog-to-digital converter (ADC). By using techniques such as improved switching and offset compensated amplifiers, the high-speed two-step architecture can be expanded toward high resolution. The ADC presented here achieves 9 ENOB with a spurious-free dynamic range of more than 72 dB, at a sample rate of 25 MSample/s. The ADC is realized in a 0.35-μm mainstream CMOS process without options such as double poly. It measures 0.66 mm ² and dissipates 195 mW from a 3.3-V power supply     

A 0.18-μm 256-Mb DDR-SDRAM with low-cost post-mold tuning methodfor DLL replica

A 200-MHz double-data-rate synchronous-DRAM (DDR-SDRAM) was developed. The chip contains a delay-locked loop (DLL) which performs over a wide range of operating conditions. Post-mold-tuning allows precise replica programming. A 200-MHz intra-chip data bus is suitable for DDR operation     

A CMOS mainframe processor with 0.5-μm channel length

A processor chip set with IBM/370 architecture is implemented on five CMOS VLSI chips containing 2.8 million transistors with an effective channel length of 0.5 μm. The chip set consists of the instruction and the fixed-point processor, two cache chips with 16 KB of data and instructions, and the floating-point processor. The chips are implemented in a 1.0-μm technology with three layers of metal. An automatic design system based on the sea-of-gates technique and the standard cell approach was used. The worst-case operating frequency of the chip set is 35 MHz (typically 50 MHz). Four chips of the processor are packaged on a ceramic multichip module. Level-sensitive scan design, built-in self-test, and parity check guarantee high test coverage and reliability     

A 16-Mb CMOS SRAM with a 2.3-μm2 single-bit-linememory cell

A novel architecture that enables fast write/read in poly-PMOS load or high-resistance polyload single-bit-line cells is developed. The architecture for write uses alternate twin word activation (ATWA) with bit-line pulsing. A dummy cell is used to obtain a reference voltage for reading. An excellent balance between a normal cell signal line and a dummy cell signal line is attained using balanced common data-line architecture. A newly developed self-bias-control (SBC) sense amplifier provides excellent stability and fast sensing performance for input voltages close to V_CC at a low power supply of 2.5 V. The single-bit-line architecture is incorporated in a 16-Mb SRAM, which was fabricated using 0.25-μm CMOS technology. The proposed single-bit-line architecture reduces the cell area to 2.3-μm² , which is two-thirds of a conventional two-bit-line cell with the same processes. The 16-Mb SRAM, a test chip for a 64-Mb SRAM, shows a 15-ns address access time and a 20-ns cycle time     

A 0.18-μm CMOS IA-32 processor with a 4-GHz integer executionunit

This paper describes the main features and functions of the Pentium(R) 4 processor microarchitecture. We present the front-end of the machine, including its new form of instruction cache called the trace cache, and describe the out-of-order execution engine, including a low latency double-pumped arithmetic logic unit (ALU) that runs at 4 GHz. We also discuss the memory subsystem, including the low-latency Level 1 data cache that is accessed in two clock cycles. We then describe some of the key features that contribute to the Pentium(R) 4 processor's floating-point and multimedia performance. We provide some key performance numbers for this processor, comparing it to the Pentium(R) III processor     

A fully integrated analog front-end macro for cable modemapplications in 0.18-μm CMOS

An analog front-end (AFE) module designed for use together with a digital cable modem transceiver on one single die is presented. All the analog functionality is implemented in a pure 0.18-μm CMOS process with 1.8-V supply. Besides the critical requirements toward substrate and supply isolation, the design of the high-order antialiasing filter, the high-performance analog-to-digital converter, and the low-jitter phase-locked loop are most challenging. With a silicon area of 9.9 mm ² and a power dissipation of less than 1 W, this 3-channel AFE can be considered a reference design for first-IF sampling (surface acoustic wave (SAW)-less) cable modem systems     

A CMOS continuous-time Gm-C filter for PRML read channelapplications at 150 Mb/s and beyond

Design techniques for equiripple phase CMOS continuous-time filters are presented, and their integration within a partial-response maximum likelihood (PRML) disk drive read channel is discussed. A programmable seven-pole two asymmetric zero filter implementation is described based on a new transconductance (G_m) cell. The impact of integrator finite output impedance, excess phase, and other implementation related nonidealities is discussed. A filter tuning circuit that requires an accurate time base but no external components is presented. The filter has a cutoff frequency (f_c) range of 6-43 MHz, where f_c is the -3 dB point of the magnitude transfer function with the two zeros set to infinity. Also, with finite zeros it is able to provide up to 12 dB of boost which is defined as the maximum value of the magnitude transfer function referred to dc. The group delay ripple stays within ±2% for frequencies below 1.75 f _c. The cutoff frequency exhibits a 650 ppm/°C temperature dependency and a variation of ±1%/V with the power supply. Total harmonic distortion (THD) values are below -40 dB at twice the nominal operating input voltage (V_nominal=320 mV peak-to-peak differential), and the dynamic range exceeds 60 dB (for a maximum input signal of 640 mV peak-to-peak differential, maximum bandwidth setting, and no boost). Both the filter and a tuning circuit were implemented in a 0.6-μm single-poly triple-metal n-well CMOS process. They consume 90 mW from a single 5 V power supply and occupy an area of 0.8 mm²      

An 0.18-μm CMOS for mixed digital and analog applications withzero-volt-Vth epitaxial-channel MOSFETs

An 0.18-μm CMOS technology with multi-V_ths for mixed high-speed digital and RF-analog applications has been developed. The V _ths of MOSFETs for digital circuits are 0.4 V for NMOS and -0.4 V for PMOS, respectively. In addition, there are n-MOSFET's with zero-volt-V_th for RF analog circuits. The zero-volt-V_th MOSFETs were made by using undoped epitaxial layer for the channel regions. Though the epitaxial film was grown by reduced pressure chemical vapor deposition (RP-CVD) at 750°C, the film quality is as good as the bulk silicon because high pre-heating temperature (940°C for 30 s) is used in H₂ atmosphere before the epitaxial growth. The epitaxial channel MOSFET shows higher peak g_m and f_T values than those of bulk cases. Furthermore, the g_m and f_T values of the epitaxial channel MOSFET show significantly improved performances under the lower supply voltage compared with those of bulk. This is very important for RF analog application for low supply voltage. The undoped-epitaxial-channel MOSFETs with zero-V_th will become a key to realize high-performance and low-power CMOS devices for mixed digital and RF-analog applications     

0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using currentmode logic with tolerance to threshold voltage fluctuation

A feedback MOS current mode logic (MCML) is proposed for the high-speed operation of CMOS transistors. This logic is more tolerant to the threshold voltage fluctuation than the conventional MCML and is suitable for gigahertz operation of deep-submicron CMOS transistors. Using this logic, 8:1 multiplexer (MUX) and 1:8 demultiplexer (DEMUX) ICs for optical-fiber-link systems have been fabricated with 0.18-μm CMOS transistors. The ICs are faster than conventional CMOS MUX and DEMUX ICs and their power consumption is less than 1/4 of that of the conventional 10-Gb/s MUX and DEMUX ICs made using Si bipolar or GaAs transistors     

A 10-b 185-MS/s track-and-hold in 0.35-μm CMOS

This paper discusses the design and the implementation of a high-speed track-and-hold amplifier in 0.35-μm CMOS, featuring 10-b resolution up to 185 MS/s. The implemented folded-cascode input buffer allows a relatively large input range, 1-V_pp differential, and low harmonic distortion at the same time. The sampler is based oh a switched-source-follower (SSF) architecture with double switch-off action and saturation-mode switches, providing short aperture times and high linearity. A spur-free dynamic range (SFDR) of 63 dB at 185 MS/s was measured with a dual-tone 45-MHz±250-kHz test signal. The open-loop architecture makes harmonic distortion little sensitive to the input frequency: 10-b resolution is maintained up to 45 MHz with 1 V_pp and up to 70 MHz with 0.7 V_pp. A suitable hold-mode feedthrough rejection is achieved by means of feedforward cancellation with a MOS capacitor operating in depletion or accumulation. The track-and-hold amplifier consumes 70 mW from a 3.3-V supply     

A 2.5-V 12-b 54-Msample/s 0.25-μm CMOS ADC in 1-mm2with mixed-signal chopping and calibration

This paper describes a two-step analog-to-digital converter (ADC) with a mixed-signal chopping and calibration algorithm. The ADC consists primarily of analog blocks, which do not suffer from the matching limitations of active devices. The offset on two residue amplifiers limits the accuracy of the ADC. Background digital offset extraction and analog compensation is implemented to continuously remove the offset of these critical analog components. The calibrated two-step ADC achieves -70 dB THD in the Nyquist band, with a 2.5-V supply. The ADC is realized in standard single-poly 5-metal 0.25-μm CMOS, measures 1.0 mm² , and dissipates 295 mW     

A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS

A 6-b Nyquist A/D converter (ADC) that converts at 1.3 GHz is reported. Using array averaging and a wideband track-and-hold, a 6-b flash ADC achieves better than 5.5 effective bits for input frequencies up to 630 MHz at 1 Gsample/s, and five effective bits for 650-MHz input at 1.3 Gsample/s. Peak INL and DNL are less than 0.35 LSB and 0.2 LSB, respectively. This ADC consumes about 500 mW from 3.3 V at 1Gsample/s. The chip occupies 0.8-mm² active area, fabricated in 0.35-μm CMOS     

A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver

An 8-Gb/s 0.3-μm CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear phase-locked loop that achieves a loop bandwidth of 35 MHz, phase margin of 50°, and capture range of 20 MHz without a frequency acquisition aid. The transmitted 8 Gb/s data are successfully detected by the receiver after a 10-m coaxial cable. The 2×2 mm² chip consumes 1.1 W at 8 Gb/s with a 3-V supply     

A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with datarecovery using oversampling

A 4-Gbit/s serial link transceiver is fabricated in a MOSIS 0.5-μm HPCMOS process. To achieve the high data rate without speed critical logic on chip, the data are multiplexed when transmitted and immediately demultiplexed when received. This parallelism is achieved by using multiple phases tapped from a PLL using the phase spacing to determine the bit time. Using an 8:1 multiplexer yields 4 Gbits/s, with an on-chip VCO running at 500 MHz. The internal logic runs at 250 MHz. For robust data recovery, the input is sampled at 3× the bit rate and uses a digital phase-picking logic to recover the data. The digital phase picking can adjust the sample at the clock rate to allow high tracking bandwidth. With a 3.3-V supply, the chip has a measured bit error rate (BER) of <10^-14