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单脉冲雷达接收通道的幅相一致性及幅相调整电路 总被引:3,自引:1,他引:2
分析了单脉冲雷达相位测角对接收通道路与路之间一致性的要求,针对这些要求,研制了一种微波控幅相调整电路,还讨论了幅相调整和电路在单脉冲雷达中的应用情况。 相似文献
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介绍了重叠子阵在波束形成网络中的作用和意义。对单元电路的幅相频率特性进行了理论分析。指出当单元电路的功分比相差悬殊时采用混合环定向耦合器更便于实现。首次提出了减小子阵网络相位色散的有效措施,给出了仿真和实验结果。 相似文献
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以一级RC电路作为移相网络,对低频相位仪波形转换电路单元进行改进,采用同相输入滞回比较器电路以提高抗干扰能力,采用二分频鉴相电路以实现精确的鉴相脉冲,采用移相信号放大电路以实现5 Hz~20 kHz相位差频率测量范围,进一步引入自动增益控制技术,介绍了由集成运放和模拟开关构成的程控增益放大器.通过Multisim 10对400 Hz及40 Hz时电路改进前后输出波形及相位差的仿真结果表明,改进电路性能指标达到了设计要求,提高了相位差的测量精度. 相似文献
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一种基于DDS和DSP的高精度相位测量模块的实现 总被引:1,自引:0,他引:1
介绍了一种高精度相位测量模块的实现方法;该模块以DSP作为控制和信号处理单元,控制两路DDS分别产生发射信号和基准信号,通过调整基准信号相位增量的方法,追踪待测目标回波与基准信号的相位差。文中给出了具体的硬件。实现方案和测试结果,并分析了影响相位差测量精度的因素。 相似文献
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数字阵雷达具有通道数量多、设备量大的特点,其数字收发单元的小型化、可编程等优点,对降低系统复杂度、提高可靠性和降低成本起着关键的作用。随着数模混合集成电路的飞速发展,AD采样率和直接数字频率合成(DDS)输出频率均不断提高,数模信号的转换越来越靠近天线,意味着数字阵雷达将会实现真正意义上的全数字化。文中基于多通道模数转换、DDS和多通道同步技术,通过集成、高效的设计方案,完成数字收发单元的原理分析和电路集约化设计,对设计中的要点、难点及主要参数进行了简要阐述。 相似文献
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为了解决传统电阻层析成像系统中激励信号源的问题,如电路的频率、幅值调节困难,电路设计模块复杂等问题,本文设计了一种新的电阻层析成像激励信号源产生系统。该系统利用微控器控制DAC芯片产生幅度频率可调的激励信号,该信号驱动精密电压/电流转换电路后产生双极性脉冲电流激励信号。研究表明,此系统可以满足使用要求,同时,在一定程度... 相似文献
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This paper presents a new method and circuit for the conversion of binary phase-shift keying (BPSK) signals into amplitude shift keying signals. The basic principles of the conversion method are the superharmonic injection and locking of oscillator circuits, and interference phenomena. The first one is used to synchronize the oscillators, while the second is used to generate an amplitude interference pattern that reproduces the original phase modulation. When combined with an envelope detector, the proposed converter circuit allows the coherent demodulation of BPSK signals without need of any explicit carrier recovery system. The time response of the converter circuit to phase changes of the input signal, as well as the conversion limits, are discussed in detail. 相似文献
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设计了一个以AT89S52为核心控制器件,直接控制两片DDS芯片AD9850,通过并行控制方式实现的正弦信号发生器,并且利用差动放大芯片AD830进行正弦信号幅值调节。该系统具有频率、相位可变,幅值可调,并且能够输出稳定的相位差和振幅调制的功能。 相似文献
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The low power design of a field sequential color (FSC) liquid crystal on silicon (LCoS) chip for near-to-eye application is presented in this paper. Dual power supplies are used in the design, that is, the supply for part of driving circuits is 3.3 V, and the one for the active matrix is 5.0 V. Serial-to-parallel conversion circuits are adopted to lower the pixel clock frequency of the chip. Also, an idle state is inserted into the pixel clock signal to decrease the switching activity factor to further reduce the power consumption. The LCoS chip is fabricated with 0.35 μm CMOS process and its power consumption is only about 300 mW. 相似文献
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Darko B. Mitić Goran S. Jovanović Mile K. Stojčev Dragan S. Antić 《International Journal of Electronics》2013,100(3):362-375
Phase-synchronisers have many applications in VLSI circuit designs. They are used in CMOS RF circuits including phase (de)modulators, phase recovery circuits, multiphase synthesis, etc. In this article, a phase-synchroniser based on gm-C all-pass filter chain with sliding mode control is presented. The filter chain provides good controllable delay characteristics over the full range of phase and frequency regulation, without deterioration of input signal amplitude and waveform, while the sliding mode control enables us to achieve fast and predetermined finite locking time. IHP 0.25 µm SiGe BiCMOS technology has been used in design and verification processes. The circuit operates in the frequency range from 33 MHz up to 150 MHz. Simulation results indicate that it is possible to achieve very fast synchronisation time period, which is approximately four time intervals of the input signal during normal operation, and 20 time intervals during power-on. 相似文献