铌酸锂晶片的键合减薄及热释电性能研究

铌酸锂(LN)作为一种热释电材料,可以被用于制作光电探测器敏感单元的敏感层,但通常LN晶片厚度为0.5 mm,远大于光电敏感单元厚度的要求,所以需要用键合减薄及抛光技术对LN晶片进行加工处理。本研究所用键合减薄技术主要包含:RZJ-304光刻胶键合、铣磨、抛光、剥离液剥离和丙酮清洗RZJ-304胶。利用该技术加工得到了面积为10 mm×10 mm,厚度为50μm,表面比较光滑,表面粗糙度为1.63 nm的LN晶片。LN晶片的热释电信号峰峰值在减薄抛光后为176 mV,是未经处理时的4倍,满足了热释电探测器敏感层的要求。     

微结构传感器芯片划切工艺优化

MEMS传感器技术的发展,伴随着新结构、新材料、新工艺应用在晶圆制造中[1]。这对封装核心工序的划片工艺提出了很大挑战。主要通过芯片划切过程中容易出现的几个异常现象对微结构敏感芯片划切过程中的破片进行分析,提出了一些解决微结构芯片划切过程中存在问题的办法,并进行了划切参数的优化。     

Effect of wafer thinning methods towards fracture strength and topography of silicon die

This paper characterizes die damage resulting from various wafer thinning processes. Die fracture strength is measured using ball breaker test with respect to die surface finish. Further study on surface roughness and topography of each surface finish is obtained by atomic force microscopy (AFM) and scanning electron microscopy (SEM) techniques. Stress relief process with 25 μm removal is able to strengthen 100 μm wafer by 20.4% using chemical wet etch and 75 μm wafer by 36.4% with plasma etch. Relatively, plasma etching shows higher fracture strength and flexibility compared to chemical wet etch. This is due to topography of the finished surface of plasma etch is smoother and rounded, leading to a reduced stress concentration, hence improved fracture strength.     

乙醇辅助激光烧蚀切割硅晶圆工艺

为了减小激光切割硅晶圆时的热效应,选择去离子水作为辅助液体进行激光切割实验,研究了水下切割时激光烧蚀激发气泡对硅片表面造成的不良影响。为解决水下激光切割进程中诱导气泡大面积粘结在硅片表面的问题,提出了去离子水混入乙醇溶液的实验方案,分析了水下激光切割中激光参数和乙醇浓度对切割质量的影响。实验结果表明,采用乙醇溶液作为辅助介质能明显减少粘结气泡的数量,减轻气泡破溃冲击带来的负面影响。实验采用乙醇浓度5 wt.%时切割得到的硅片比纯水中切割得到的硅表面影响区减小50%以上、切缝宽减幅约20%,有效提升了激光切割质量。     

Evaluation of crystallinity of GaN epitaxial layer after wafer dicing

The crystallinity of GaN epitaxial layers on sapphire substrates following laser dicing was evaluated by Raman spectroscopy. Dicing was carried out using either full laser ablation or laser scribing followed by breaking. The results indicated that in a region within about 40 μm from the edges of the diced chips, the Raman peaks were shifted to lower wavenumber than near the chip center. The shifted peaks were at positions intermediate between those for the GaN epitaxial layer before dicing and those for a bulk GaN crystal. These results indicate that stress relaxation occurred near the edges of the diced chips.     

GaAs集成电路芯片在片直接故障检测分析

介绍了一种实用的电光采样测试系统 ,其稳定的光学系统结构可保持精度几年不变 ,单位带宽电压灵敏度为 2 5 2mV/Hz。改进了电子移相扫描法 ,利用倍频移相扫描法对GaAs动态分频器芯片故障进行了在片检测分析。     

Effect of parameter variations at chip and wafer level on clockskews

In this paper, a methodology is proposed to determine clock skews and the performance of clock architectures considering parameter variations in an early stage of technology development. With this methodology, it is possible to separate process-induced clock skew from other effects like imperfect loading. Parameter variations are seen as one of the most important effects influencing chip performance in future. By comparing a 0.45- and a 0.25-μm technology, it is shown that in the future, process variations will increase clock skew. The clock skews are determined by measuring the relevant device and metal line parameters as a function of position over chip and wafer. In the past, parameters like IDS, Vth, and resistances could be measured very precisely, although it was difficult to measure low capacitances of single metal lines in the range of femto farad. Thus a new measurement method is used to determine interconnect capacitances extremely precisely. Based on these measurement data, a netlist of a defined clock tree is created by a C-program, and the clock signal delay is simulated. From the delay simulation, we calculate the clock skew for each chip dependent on the parameter variations. Experimental results are separated into a basic random fluctuation part and processing-related contributions on the chip and wafer levels. In addition, the effect of temperature gradients on each chip to the clock skew is simulated. The methodology presented is not restricted to just one clocktree but allows investigation of all kinds of clock distribution circuits. The method has clear advantages with respect to chip area against clocktree realizations on a testchip. No direct and costly measurement of signal delays by voltage contrast methods is required, since all parameters are determined by measurement on the device level     

Investigations of the influence of dicing techniques on the strength properties of thin silicon

Thin silicon offers a variety of new possibilities in microelectronical, solar and micromechanical industries, e.g. for 3D-integration (stacked dies), thin microelectromechanical packages or thin single crystalline solar cells. The wafers in this investigation were thinned back by grinding and subsequent spin etching steps for stress relief followed by separation into single test dies by sawing or etching. In order to characterize and optimize relevant process steps in terms of quality and fabrication yield, the mechanical properties were investigated considering the defect formation and strength. In this paper the influence of three different dicing technologies on the mechanical strength of thin silicon samples was investigated by 3-point bending tests. Sawing, Dicing-by-Thinning with sawn grooves and Dicing-by-Thinning with dry-etched trenches were used as dicing technologies. Analytical and numerical calculations were performed to calculate fracture stresses from fracture forces in 3-point bending tests taking into account the non-linear relationship of force and displacement during testing. Thus the fracture stress as a parameter of strength could be calculated for all tested samples. The results were statistically evaluated by the Weibull distribution based on the weakest link theory. This approach allows a more comprehensive understanding of the influence of the process on strength properties independently of geometric factors. Samples, being separated by “Dicing-by-Thinning”, have much higher strength than simply sawed samples. If trenches are fabricated by dry-etched process the strength can be increased tremendously.     

Very low noise RF nMOSFETs on plastic by substrate thinning and wafer transfer

A very low minimum noise figure (NF/sub min/) of 1.2 dB and a high associated gain of 12.8 dB at 10 GHz were measured for six-finger, 0.18-/spl mu/m radio frequency (RF) metal-oxide semiconductor field-effect transistors mounted on insulating plastic following substrate-thinning (/spl sim/30 /spl mu/m) and wafer transfer. Before this process, the devices had a slightly better RF performance of 1.1-dB NF/sub min/ and a 13.7-dB associated gain. The small RF performance degradation of the active transistors transferred to plastic shows the potential of integrating electronics onto plastic.     

Effect of laminated wafer toward dicing process and alternative double pass sawing method to reduce chipping

Thin wafers of 100-/spl mu/m thickness laminated with die-attach film (DAF) was diced using a standard sawing process and revealed a low chipping crack resistance. Wafers laminated with conductive DAF shows greater chipping compared to nonconductive DAF and bare silicon wafer. It was found through scanning electron microscopy (SEM) micrographs, energy dispersive X-ray (EDX) analysis, and atomic force microscopy (AFM) that silver fillers in the conductive DAF was the cause of excessive blade loading which resulted in bad chipping quality. To reduce chipping/cracking induced by sawing, an alternative double-pass sawing method was developed and is explained in the paper. The methodology of this study discusses a double-pass method, where the first pass dice through the wafer and varied the percentage of DAF thickness cut. Best results were achieved when dicing through the wafer and 0% of DAF, followed by a full separation in the second pass. Approximately 80% of chipping reduction compared to conventional single pass.     

300mm晶圆芯片制造技术的发展趋势

采取300mm晶圆是半导体生产发展的必然规律.300mm晶圆与90nm工艺是互动的.90nm新工艺主要包括193nm光刻技术、铜互连、低k绝缘层、CMP、高k绝缘层、应变硅和SOI等.本文着重讨论300mm晶圆芯片制造技术的发展趋势.     

Dynamic strength of anisotropic conductive joints in flip chip on glass and flip chip on flex packages

The work presented in this paper focuses on the behavior of anisotropically conductive film (ACF) joint under the dynamic loading of flip chip on glass (COG) and flip chip on flexible (COF) substrate packages. Impact tests were performed to investigate the key factors that affect the adhesion strength. Scanning electron microscopy (SEM) was used to evaluate the fractography characteristics of the fracture. Impact strength increased with the bonding temperature, but after a certain temperature, it decreased. Good absorption and higher degree of curing at higher bonding temperature accounts for the increase of the adhesion strength, while too high temperature causes overcuring of ACF and degradation at ACF/substrate interface––thus decreases the adhesion strength. Higher extent of air bubbles was found at the ACF/substrate interface of the sample bonded at the higher temperature. These air bubbles reduce the actual contact area and hence reduce the impact strength. Although bonding pressure was not found to influence the impact strength significantly, it is still important for a reliable electrical interconnect. The behaviors of the conductive particles during impact loading were also studied. From the fracture mode study, it was found that impact load caused fracture to propagate in the ACF/substrate interface (for COG packages), and in the ACF matrix (for COF packages). Because of weak interaction of the ACF with the glass, COG showed poor impact adhesion.     

指纹图像细化算法的研究

指纹识别是一种重要的生物特征鉴别技术。随着计算机技术的不断发展,自动指纹识别系统得到广泛的应用。因此进一步提高指纹识别的性能具有十分重要的意义,而指纹图像增强在指纹图像预处理过程中非常重要,直接影响指纹识别的识别率和识别速度。对指纹图像的细化算法进行了较深入的研究,分析了OPTA算法并且在OPTA算法的基础上,重新构建了细化模板,提出了一种新的细化算法.经过实验证明,该算法能够很好地满足细化的要求,细化完全彻底,细化以后的指纹骨架在纹线中心线,并保持了纹线原有的拓扑结构和细节特征,而且光滑无毛刺,运算速度也很快。     

Relationship between wafer edge design and its ultimate mechanical strength

Due to its brittle nature, high stress-induced in manufacturing process, silicon wafer breakage has become a major concern for all semiconductor fabrication line. Furthermore, the production cost had increased in advanced technology day by day. Even a some-percent breakage loss drives device costs up significantly if wafers are broken near completion. Consequently, wafer breakage even near the beginning of the process is significant. In short words, silicon wafer breakage has become a major concern for all semiconductor fabrication lines, and so high stresses are easily induced in its manufacture process. The production cost is increasing even breakage loss of a few percent significantly drives device costs up, if wafers are broken near completion. Even wafer breakage near the beginning of the process is significant.In this paper, we first point out the approach for the characterization of silicon wafer failure strength employing a simple drop test, thereby providing a better understanding of the stress accumulated in wafer bulk before failure.This study also presents a brand new method using a charge coupled device (CCD) to capture the cross-section image of the wafer at the wafer edge; the data measured at the edge can be used to diagnose overall wafer strength. Analysis of the image of the wafer edge is used to characterize silicon strength and a simple drop test is conducted to elucidate wafer failure, improving our understanding of the accumulation of stress in wafer bulk before failure.A physical model would also be proposed to explain the results. This model demonstrates that the fracture rate of wafers can be reduced by controlling the uniformity of the difference between the front and rear bevel lengths during the wafer manufacturing process.     

Mechanisms of wafer sawing and impact on wafer properties

Silicon wafer wire‐sawing experiments were realized with different sets of sawing parameters, and the thickness, roughness, and cracks depth of the wafers were measured. The results are discussed in relation to assumptions underlying the rolling–indenting model, which describes the process. It was also found that the silicon surface at the bottom of the sawing groove is different from the wafer surface, implying different sawing conditions in the two positions. Furthermore, the measured parameters were found to vary along the wire direction, between the entrance of the wire in the ingot and its exit. Based on these observations, some improvements for the wire‐sawing model are discussed. Copyright © 2010 John Wiley & Sons, Ltd.     

Reference SAW oscillator on quartz-on-silicon (QoS) wafer forpolylithic integration of true single chip radio

The authors present an electro-acoustic circuit fabricated on quartz directly bonded on the processed silicon wafer (QoS), which allows us to polylithically integrate high precision passives with integrated circuits. We first fabricated a prototype SAW resonator and oscillator on thick QoS. The SAW resonator on QoS shows Q about 10,000 and 11 dB insertion loss at 289 MHz, and SAW oscillator on QoS shows phase noise of as small as -120 dBc at 100 kHz offset, demonstrating the feasibility of true single chip radio     

Temperature and duration effects on microstructure evolution during copper wafer bonding

Interfacial morphologies during Cu wafer bonding at bonding temperatures of 300–400°C for 30 min followed by an optional 30-min or 60-min nitrogen anneal were investigated by means of transmission electron microscopy (TEM). Results showed that increased bonding temperature or increased annealing duration improved the bonding quality. Wafers bonded at 400°C for 30 min followed by nitrogen annealing at 400°C for 30 min, and wafers bonded at 350°C for 30 min followed by nitrogen annealing at 350°C for 60 min achieve the same excellent bonding quality.     

Critical issues of wafer level chip scale package (WLCSP) withemphasis on cost analysis and solder joint reliability

Some of the critical issues of wafer level chip scale package (WLCSP) are mentioned and discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the, important parameters such as wafer-level redistribution, wafer-bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layer on the solder joint reliability of WLCSP on printed circuit board (PCB) through the creep responses such as the deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped with pad-redistribution WLCSPs are considered in this study     

一种混合晶向结构硅片研究

为15V-40V电压集成电路和MEMS传感器潜在应用,研发了两种5μm厚的混合晶向结构硅片。这种结构采用以键合SOI硅片和非选择性外延为主的方法实现。这种结构在国内首次被报道。这种结构埋氧层厚度为220nm,通过“Sirtl”缺陷显示液发现以（100）晶向为衬底的混合晶向结构硅片质量好于以（110）为衬底的混合晶向硅片。     

Si晶片激光标识码制作技术的研究

Si片标识码在工艺加工管理中起重要作用.传统手写方式存在字体不美观、划痕深及硅渣污染等缺点.鉴于此,采用波长1060 nm光纤激光器进行激光标识码制作.研究中分别改变激光平均输出功率、脉冲频率及扫描速度,借助目视、金相显微镜及动态三维光学轮廓仪来观察标识码清晰程度、污染程度及深浅程度的变化,了解它们与上述参数间相互对应关系.重点解决清晰度与打标深度之间的矛盾,从而得到清晰、清洁且深度满足后续半导体纳米级加工工艺要求的激光标码技术.研究表明:低脉冲频率(20 kHz)下,随平均功率上升,标识码的清晰度逐渐增加,镜检结果显示硅渣的数量及其分布区域增大;高脉冲频率(90 kHz)下,平均功率增加对标识码清晰度的影响不明显,镜检结果没有发现硅渣.扫描频率与清晰度及污染程度成正比关系.扫描速度与打标深度呈反比关系.采用40％平均功率,25 kHz频率,1500 mm/s扫描速度及双线填充字体(TrueType)的工艺条件,所得标识码在目视及镜检下清晰美观,无硅渣污染.轮廓仪测量结果显示字迹深度及边缘凸起均在200 nm以下.经批量产品验证,根据研究成果所开发的工艺技术稳定且对后续工艺无不良影响.目前已取代手写方式.