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传统的副瓣对消处理多基于通用DSP。为了在由FPGA构建的板级信号处理器上实现雷达副瓣对消处理,可以将副瓣对消的算法采用一种专用硬件架构来实现。在开发电路时充分考虑设计的可移植性,为以后类似的任务提供IP。基于硬件乘法器复用的方法设计的电路,已经过FPGA验证,实测对消比大于20 dB,达到了预定指标,并已应用于工程实践。 相似文献
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基于多FPGA的SAR成像信号处理机设计 总被引:1,自引:1,他引:0
文中针对FPGA在数字信号处理领域中一些区别于DSP的优点,以及SAR信号仿真与处理的大运算量、高数据通信量和实时性对成像处理机的可靠性和稳定性等特点,设计开发了一种基于多FPGA的SAR成像信号处理机。详细介绍了系统结构、数据通信方式以及FPGA配置等关键问题。 相似文献
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文章以嵌入式和数据采集技术为基础,研究设计并实现了基于ARM+FPGA体系架构面向高速实时数据采集应用的一种实用新型智能控制器。本文阐述了主处理器ARM最小系统、协处理器FPGA最小系统和ARM与FPGA通信接口等硬件系统技术的实现,以及Linux FPGA字符设备驱动程序开发、协处理器FPGA控制程序和主处理器ARM应用程序设计。智能控制器运用FPGA并行运算处理结构的优势,控制ADC进行高速数据采集。FPGA还可配置成软核处理器-Nios II嵌入式处理器,与ARM构成双核处理器系统。智能控制器通过ARM实现对FPGA的管理控制、实时数据采集和丰富外围接口的通信。 相似文献
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A new FPGA architecture suitable for digital signal processing applications is presented.DSP modules can be inserted into FPGA conveniently with the proposed architecture,which is much faster when used in the field of digital signal processing compared with traditional FPGAs.An advanced 2-level MUX(multiplexer) is also proposed.With the added SLEEP MODE PASS to traditional 2-level MUX,static leakage is reduced.Furthermore, buffers are inserted at early returns of long lines.With this kind of buffer,the delay of the long line is improved by 9.8%while the area increases by 4.37%.The layout of this architecture has been taped out in standard 0.13μm CMOS technology successfully.The die size is 6.3×4.5 mm~2 with the QFP208 package.Test results show that performances of presented classical DSP cases are improved by 28.6%-302%compared with traditional FPGAs. 相似文献
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Field Programmable Gate Array (FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing mieroehip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system inte- gration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, intercon- nects, and embedded resources. Moreover, some important emerging design issues of FPGA archi- tectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development. 相似文献
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以AT89S52单片机和FPGA作为测量和数据处理核心,基于DDS技术,并结合I/V变换、A/D采样等外围电路,以及离散傅立叶变换(DFT)等数字信号处理方法,设计并实现了一种简易的无源网络导纳分析仪.另外,系统具有连续测量、频率特性测量及其绘制曲线等功能;还具有性能稳定、结构简单、测量方法巧妙,精度较高,人机交互界面友好等特点. 相似文献
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Real-time image processing usually requires an enormous throughput rate and a huge number of operations. Parallel processing, in the form of specialized hardware, or multiprocessing are therefore indispensable. This piper describes a flexible programmable image processing system using the field programmable gate array (FPGA). The logic cell nature of currently available FPGA is most suitable for performing real-time bit-level image processing operations using the bit-level systolic concept. Here, we propose a novel architecture, the programmable image processing system (PIPS), for the integration of these programmable hardware and digital signal processors (DSPs) to handle the bit-level as well as the arithmetic operations found in many image processing applications. The versatility of the system is demonstrated by the implementation of a 1-D median filter. 相似文献
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Sanjay Singh Anil K Saini Ravi Saini A.S. Mandal Chandra Shekhar Anil Vohra 《International Journal of Electronics》2013,100(12):1705-1715
A new resource efficient FPGA-based hardware architecture for real-time edge detection using Sobel operator for video surveillance applications has been proposed. The choice of Sobel operator is due to its property to counteract the noise sensitivity of the simple gradient operator. FPGA is chosen for this implementation due to its flexibility to provide the possibility to perform algorithmic changes in later stage of the system development and its capability to provide real-time performance, hard to achieve with general purpose processor or digital signal processor, while limiting the extensive design work, time and cost required for application specific integrated circuit. The proposed architecture uses single processing element for both horizontal and vertical gradient computation for Sobel operator and utilised approximately 38% less FPGA resources as compared to standard Sobel edge detection architecture while maintaining real-time frame rates for high definition videos (1920 × 1080 image sizes). The complete system is implemented on Xilinx ML510 (Virtex-5 FX130T) FPGA board. 相似文献
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随着超大规模集成电路技术尤其是FPGA技术和数字信号处理技术的迅猛发展,为雷达信号处理技术的工程实现提供了新思路和新方法。采用FPGA技术对雷达的视频信号进行视频积累,克服了DSP处理速度有限、实时性差和ASIC器件灵活性差的问题。以自行研制的雷达信号处理PCI卡为平台,详细介绍了雷达视频积累算法在FPGA芯片上实现的原理和过程,并结合仿真结果说明了利用FPGA进行视频积累的优势,为雷达视频积累的工程实现提出了一条新思路。 相似文献
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本文介绍了一种用于扫描隧道显微镜的实时图像处理系统。通过改变形态学运算,定义条件腐蚀、条件膨胀、开运算、闭运算、可滤除幅度大于特定值的噪声信息。选择适当的模板结构和门限阈值,这种改进的形态滤波器既保留了传统形态滤波器的优点,又克服了它的特点。 相似文献
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大频差长地址码扩频系统快速捕获方案的设计与实现 总被引:2,自引:0,他引:2
该文基于离散时间信号处理分析了多普勒频移对捕获性能影响的表达式,给出部分匹配滤波器与FFT结合方案的原理。针对大频差长地址码扩频系统快速捕获问题,提出一种采用部分匹配滤波器与FFT结合算法的实现方案,在考虑捕获性能与实现复杂性间的折衷上,具有很好的灵活性。该方案应用FPGA与DSP芯片配合实现,应用结果表明该方案在移动卫星通信和直扩抗干扰通信中具有很好的应用前景。 相似文献