HF chemical etching of SiO2 on 4H and 6H SiC

Thickness and etch rate of SiO₂ films thermally grown on hexagonal SiC substrates were compared to results obtained from SiO₂/Si samples. The data confirm that profilometry and ellipsometry yield the same thickness values for oxides grown on Si and SiC. Within the accuracy of our measurements, oxides grown on different polytypes and faces of SiC etch at the same rate in a HF acid solution. The etch rate using a 50:1 H₂O:HF(50%) solution at room temperature is 0.1 nm/s and is uniform throughout the thickness of the SiO₂ films. The rate is the same as that obtained for SiO₂ grown on Si.     

Formation of buried oxide layers by high dose implantation of oxygen ions in silicon

Buried implanted oxide layers have been formed by high dose implantation of oxygen ions of the order of 1 × l0¹⁸−2 in silicon. The effects of dose at a given energy, and energy for a given peak concentration, on the distribution profile of oxygen have been studied. An approximately Gaussian distribution is observed at doses contributing less than the stoichiometric requirement of oxygen for the formation of silicon dioxide. A saturation in the oxygen peak concentration is reached when the stoichiometric requirement is exceeded. The excess implanted oxygen results in a broadening of the stoichiometric implanted oxide layer. A consequent reduction in the interface damage is observed. Other parameters being equal, at higher substrate temperatures the interface damage is decreased. For a given peak concentration, the implanted oxide is buried more deeply with increasing ion energy. Infra-red absorption characteristics of the implanted oxide are almost identical to those of thermal oxide layers grown in a dry oxygen ambient. The implanted oxide layer exhibits also an extremely high resistivity compared to the substrate material. Department of Electronics, University of Kent,Canterbury,Kent,U.K.     

Effect of epilayer characteristics and processing conditions on the thermally oxidized SiO2/SiC interface

The optimization of the SiO₂/SiC interface is critical for the development of SiC MOS devices. We investigate the effects of several variables spanning both epilayer attributes and processing conditions relative to our control oxidation process. Varying the shallow vicinal angle of the wafer does not affect the interface. There is a definite degradation of the interface as the epilayer doping density is increased. Sacrificial oxidation appears to reduce the number of border traps in the final oxide. Fluorine annealing has no effect on the interface quality. A low temperature (950°C) re-oxidation, which follows a bulk oxide growth at 1150°C, reduces D _it to the mid-10¹⁰ cm⁻²eV⁻¹ range near midgap and Q_f to a reacord low 5×10¹¹ cm⁻².     

Photoluminescence and Electroluminescence Imaging of Carrot Defect in 4H-SiC Epitaxy

Electroluminescence (EL) and photoluminescence (PL) imaging techniques were successfully used to reveal defect features in 34 carrots in 4H-SiC epilayers. Because EL and PL techniques are nondestructive and require minimal sample preparations, many carrots can be examined over a reasonable time. Our findings showed that some carrots had the basic components consistent with the model proposed by Benamara et al., but also contained additional features beyond the basic components. Eight carrots contained multiple bright line features, and 25 out of 50 bright line features exhibited multiple line characteristics. Eleven carrots were discovered to contain basal plane faults (B’s) and the corresponding small stacking faults (S’s) near the carrot heads. Not all the carrots lie along the off-cut direction; a couple were oriented 5° from the off-cut. Of the seven carrots with shape lengths -200 μm, one had a corresponding bright line length of 370 μm. Based on this line length, the calculated depth of origin was about midway in the epilayer, while all of the other carrots originated from the substrate. In summary, both EL and PL techniques were consistent in showing that carrots exhibit variable defect structures on a microscopic scale.     

Thin silicon oxide films on N-type 4H-SiC prepared by scanning frequency anodization method

The effect of selective anodization on SiC in direct voltage superimposed with alternative voltage of scanning frequencies has been investigated. Compared with the gate oxides grown with direct voltage or alternative voltage of a constant frequency, the oxide charge and the interface state density of the sample with scanning frequencies are significantly reduced. It is suggested that the bulk traps and interface traps in the oxides can be compensated during the scanning frequency anodization process since the scanning frequencies are in close proximity to the response times of interface states.     

一氧化氮退火对高温氧化SiC/SiO2界面特性的影响研究

本文研究了高温（1300℃）氧化并在一氧化氮（NO）气体中进行氧化后退火方法对4H-SiC 金属-氧化物-半导体（MOS）电容的SiC/SiO2界面特性的影响,主要通过SiC MOS的电容-电压(C-V)特性详细讨论了NO退火时间和温度与SiO2/SiC界面特性的相互关系. 结果表明在NO气体中进行氧化后退火可明显降低界面态密度,并且界面态密度随着温度和时间的增加会进一步降低。 同时,与常规1200℃及以下氧化温度相比,1300℃下热生长的氧化层具有更低的界面态密度且显著缩短了氧化时间,节约了生产成本。     

Radiation sensitivity of buried oxides

Capacitance-voltage (C-V) techniques have been used to examine the 10-keV x-ray radiation sensitivity of buried oxides that are created by the implantation of oxygen into silicon. Buried oxide to substrate interfaces have been studied by using samples implanted with different oxygen implant doses from a 100 mA-class implanter. Fiatband voltage (Vfb) shift for the buried oxide to the substrate interface has been used to monitor charge buildup as a function of radiation dose and applied electrical bias. The Vfb shift of the buried oxides indicate a oxide trapping behavior that is different than that of thermal oxides.     

Comment on A. Agarwal and S. Haney, “Some Critical Materials and Processing Issues in SiC Power Devices” [J. Electron. Mater. 37, 646 (2008)]

Agarwal and Haney [J. Electron. Mater. 37, 646 (2008)] have recently suggested that bulk defects may limit the inversion-layer mobility in SiC metal oxide semiconductor field-effect transistors. However, we believe that the physics of charge trapping and Coulomb scattering by bulk traps quantitatively contradicts this model.     

The Effects of Implant Activation Anneal on the Effective Inversion Layer Mobility of 4H-SiC MOSFETs

In this paper, we investigate the effective inversion layer mobility of lateral 4H-SiC metal oxide semiconductor field-effect transistors (MOSFETs). Initially, lateral n-channel MOSFETs were fabricated with three process splits to investigate phosphorus implant activation anneal temperatures of 1200, 1650, and 1800°C. Mobility results were similar for all three temperatures (using a graphite cap at 1650°C and 1800°C). A subsequent experiment was performed to determine the effect of p-type epi-regrowth on the highly doped p-well surface. The negative effects of the high p-well doping are still seen with 1500 ? p-type regrowth, while growing 0.5 μm or more appears to be sufficient to grow out of the damaged area. A continuing series of tests are being conducted at present.     

Improved oxidation procedures for reduced SiO2/SiC defects

A significant reduction in the effective oxide charge and interface state densities in oxides grown on p-type 6H-SiC has been obtained by lowering the oxidation temperature of SiC to 1050°C. Further improvements are obtained by following the oxidation with an even lower temperature re-oxidation anneal. This anneal dramatically improves the electrical properties of the Si/SiC interface, and substantially lowers the interface state density. The net oxide charge density on p-type 6H-SiC is also lowered significantly, but remains quite high, at 1.0 × 10¹² cm^-2. The interface state densities of 1.0 × 10¹¹ cnr⁻²/eV are approaching acceptable MOS device levels. The breakdown fields of the oxides are also substantially improved by both the lower oxidation temperature and re-oxidation anneal. Using a low temperature oxidation followed by a re-oxidation anneal for MOSFETs results in a room temperature mobility of 72 cm²/V-s, the highest channel mobility reported for SiC MOSFETs to date.     

Reactive ion etching of trenches in 6H-SiC

In this paper, we report the reactive ion etching (RIE) of trenches in 6H-silicon carbide using SF₆/O₂. The plasma parameters: etchant composition, gas flow rate, chamber pressure, and radio frequency power were optimized to obtain a maximum etch rate of 360Å/min. The etch rate of SiC was found to exhibit a direct correlation with the dc self bias except when the O₂ percentage was varied. Trenches were fabricated using the optimized conditions. It was found that the trench surface was extremely rough due to the aluminum micromasking effect. To overcome this effect, a Teflon^TM sheet was used to cover the cathode during the experiment. The trenches fabricated using this modification were found to have smooth etched surfaces and sidewalls. The angle of anisotropy of these trenches was approximately 80° which is suitable for device applications.     

Effect of NO annealing conditions on electrical characteristics of n-type 4H-SiC MOS capacitors

This paper presents the results of the effect of NO annealing temperature and annealing time on the interfacial properties of n-type 4H-SiC MOS capacitors. The interface trap density measured by conductance technique at 330°C decreases as NO annealing temperature increases from 930°C to 1130° and annealing time is extended from 30 min. to 180 min. The changes in effective oxide charge between room temperature and high temperature are calculated and used to compare different n-type 4H-SiC MOS capacitors. Higher NO annealing temperature and longer NO annealing time decrease the change in effective oxide charge, which is consistent with the NO annealing temperature/time dependence of interface trap density measured by conductance technique. However, NO annealing temperature has more pronounced influence on the SiO₂/SiC interface than NO annealing time.     

Effects of annealing conditions on the properties of tantalum oxide films on silicon substrates

The formation of a SiO₂ layer at the Ta₂O₅/Si interface is observed by annealing in dry O₂ or N₂ and the thickness of this layer increases with an increase in annealing temperature. Leakage current of thin (less than 40 nm thick) Ta₂O₅ films decreases as the annealing temperature increases when annealed in dry O₂ or N₂. The dielectric constant vs annealing temperature curve shows a maximum peak at 750 or 800° C resulting from the crystallization of Ta₂O₅. The effect is larger in thicker Ta₂O₅ films. But the dielectric constant decreases when annealed at higher temperature due to the formation and growth of a SiO₂ layer at the interface. The flat band voltage and gate voltage instability as a function of annealing temperature can be explained in terms of the growth of interfacial SiO₂. The electrical properties of Ta₂O₅ as a function of annealing conditions do not depend on the fabrication method of Ta₂O₅ but strongly depend on the thickness of Ta₂O₅ layer.     

Research of SiO2/InP structure prepared by photo-CVD

The SiO₂ film as an insulator in InP MOS structure was grown by mercury-sensitized photo induced chemical-vapor deposition (photo-CVD) utilizing gaseous mixture of monosilane (SiH₄) and nitrous oxide (N₄O) under 253.7 nm ultraviolet light irradiation. The PHOTOX SiO₂ film (i.e., SiO₂ film prepared by photo-CVD system) deposited at 250° C has a refractive index of 1.46 and breakdown field strength of 7.0 MV/cm. The 1 MHz capacitance-voltage characteristics of the InP MOS diode was measured to study the interface state densities. The minimum value is 1.2 × 10¹¹ cm⁻²eV⁻¹ for the sample prepared at a substrate temperature of 250° C.     

A framework for understanding fast-neutron induced defects in SiO2 MOS structures

Neutron radiation damage in solids results from nuclear collisions and reactions that produce energetic recoil atoms. The recoiling atoms slow down in the host material through nuclear and electronic collisions. During a nuclear collision, energy is transferred to translatory motion of another atom, whereas during an electronic collision, energy is transferred to atomic electrons, leading to electronic excitation or ionization. Nuclear collisions may result in displacing additional host atoms from their lattice sites if the energy received by the host atom is greater than the displacement threshold energy. As neutrons pass through the thin thermally grown gate oxide of a MOSFET device, they produce both silicon and oxygen primary knock-on atoms (PKAs). These PKAs can produce significant displacement damage regions in the bulk oxide which become potential hole traps or mobile ionic charge traps similar to the condition at the SiO₂/Si interface. It is also suspected that these PKAs may deposit part of their energies into plasmons, which will eventually decay to electron-hole pairs causing charge buildup at the interface, when the MOSFET device is in operation. Since the gate oxide region is susceptible to electronic effects, it is important to know the amount of damage from individual neutron interactions in the oxide layer. A key to a theoretical study is provided in this paper. Analytical and direct-simulation estimates are made of the neutron damage.     

Growth of CsLiB6O10 thin films on Si substrate by pulsed laser deposition using SiO2 and CaF2 as buffer layers

CsLiB₆O₁₀ (CLBO) thin films are grown on Si (100) and (111) substrates using lower index SiO₂ and CaF₂ as buffer layers by pulsed KrF (248 nm) excimer laser ablation of stoichiometric CLBO targets over a temperature range of 425 to 725°C. A CaF₂ buffer layer is grown on Si by laser ablation while SiO₂ is prepared by standard thermal oxidation. From extended x-ray analysis, it is determined that CaF₂ is growth with preferred orientation on Si (100) at temperatures lower than 525°C while on Si (111) substrate, CaF₂ is grown epitaxially over the temperature range; this agrees well with observed reflection high energy electron diffraction patterns. X-ray 2θ-scans indicate that crystalline CLBO are grown on SiO₂/Si and CaF₂/Si (100). Analysis of reflectance spectra from CLBO/SiO₂/Si yields the absorption edge at 182 nm. Surface roughness of the CaF₂ and CLBO/CaF₂/Si film are 19 and 15 nm, respectively. This relatively rough surface caused by the ablation of wide bandgap CaF₂ and CLBO limits the application of CLBO for waveguiding measurement.     

Some Critical Materials and Processing Issues in SiC Power Devices

There has been a rapid improvement in SiC materials and power devices during the last few years. However, the materials community has overlooked some critical issues, which may threaten the emergence of SiC power devices in the coming years. Some of these pressing materials and processing issues will be presented in this paper. The first issue deals with the possibility of process-induced bulk traps in SiC immediately under the SiC/SiO₂ interface, which may be involved in the reduction of effective inversion layer electron mobility in SiC metal–oxide–semiconductor field-effect transistor (MOSFETs). The second issue addresses the effect of recombination-induced stacking faults (SFs) in majority carrier devices such as MOSFETs, Schottky diodes, and junction field-effect transistors (JFETs). In the past it was assumed that the SFs only affect the bipolar devices such as PiN diodes and thyristors. However, most majority carrier devices have built-in p–n junction diodes, which can become forward biased during operation in a circuit. Thus, all high-voltage SiC devices are susceptible to this phenomenon.     

不同氧化退火工艺下SiO2/SiC界面特性研究

The effect of the different re-oxidation annealing （ROA） processes on the SiO2/SiC interface charac- teristics has been investigated. With different annealing processes, the flat band voltage, effective dielectric charge density and interface trap density are obtained from the capacitance-voltage curves. It is found that the lowest interface trap density is obtained by the wet-oxidation annealing process at 1050 ℃ for 30 min, while a large num- ber of effective dielectric charges are generated. The components at the SiO2/SiC interface are analyzed by X-ray photoelectron spectroscopy （XPS） testing. It is found that the effective dielectric charges are generated due to the existence of the C and H atoms in the wet-oxidation annealing process.     

Template approaches to growth of oriented oxide heterostructures on SiO2/Si

A template approach to growing highly oriented ferroelectric oxide heterostructures on SiO₂/Si substrates is presented. In this method, a thin “template” of a layered perovskite is used to induce the growth of the subsequent layers in the desired orientation. The efficacy of this “template” approach is illustrated through the example of growth of ferroelectric La-Sr-Co-0/Pb-Zr-Ti-O/La-Sr-Co-O heterostructures on SiO₂Si. Discrete test capacitors fabricated from these heterostructures grown using the template approach exhibit remnant polarization values in the range of 10–15 μ C/cm² and show very little degradation after 10¹¹ bipolar fatigue cycles. In contrast, test capacitors fabricated without the template layer showed very little crystallographic texture and poor ferroelectric properties.     

Temperature measurement in a silicon carbide light emitting diode by raman scattering

Raman spectra of the transverse-optic phonon mode from a light-emitting layer of a SiC diode have been measured. The phonon peak broadens and shifts to lower frequency with the rise of temperature when the injected current is increased. The frequency shift was compared with a result for bulk reference measured separately at various temperatures. We found that the temperature of the light-emitting layer reached 350°C at a current density of ∼200 A/cm².