Contrast-enhancement in black dielectric electroluminescent devices

A high contrast electroluminescent (EL) device structure is presented. The diffuse luminous reflectivity from the metal/dielectric/phosphor/indium-tin-oxide/glass EL device structure is /spl sim/3%. A Eu-doped GaN phosphor is used to demonstrate the contrast-enhanced operation. Low reflectivity is achieved by inserting a light-absorbing black thick-film BaTiO/sub 3/ layer between the phosphor and the rear metal electrode. In addition to providing contrast enhancement, the opaque thick dielectric film exhibits capacitance and high voltage reliability (40 nF/cm/sup 2/, dielectric constant /spl epsi//sub d/ /spl sim/ 500-1000, breakdown field E/sub d,br/ /spl sim/ 0.1-0.4 MV/cm) similar to that of the highest performance transparent thin-film dielectrics. An EL device luminance of only 20 cd/m/sup 2/ is sufficient for a display contrast ratio of /spl sim/10:1 under 140 lux indoor ambient lighting (illumination). Under sunlight illumination of 100000 lux, a display contrast ratio of >3:1 is expected with application of additional contrast enhancement techniques.     

Electroluminescent devices using a high-temperature stableGaN-based phosphor and thick-film dielectric layer

Red, green, and blue light emission has been obtained from electroluminescent devices on glass using a high-temperature stable (HTS) GaN-based phosphor doped with rare earths (Eu, Er, Tm) and a screen-printed thick-film dielectric layer. The thick-dielectric electroluminescent (TDEL) structure consists of metal/dielectric/GaN/indium-tin-oxide/Corning 1737 glass. The BaTiO₃-based ~20-40 μm thick-film dielectric layer has a dielectric constant of ϵ_r~500-1000 and breakdown voltage >300 V. Despite granularity of the dielectric layer, the emission is uniform to well-below pixel dimensions (<10 μm). Red GaN:Eu TDEL operated at 240 V and 1 kHz exhibits a luminance of 35-40 cd/m². Under 140 lux illumination, the TDEL device structure exhibits a contrast ratio of 5:1 at 120 V, 1 kHz biasing, without the assistance of contrast-enhancement techniques. Accelerated aging tests of TDEL devices show 60 Hz operating lifetimes exceeding 1000 h at >95% brightness. The TDEL structure has advantages over current thin-film and thick-dielectric electroluminescent structures in flat panel display applications     

AlGaN/GaN/InGaN/GaN DH-HEMTs with an InGaN notch for enhanced carrier confinement

We report an AlGaN/GaN/InGaN/GaN double heterojunction high electron mobility transistors (DH-HEMTs) with high-mobility two-dimensional electron gas (2-DEG) and reduced buffer leakage. The device features a 3-nm thin In/sub x/Ga/sub 1-x/N(x=0.1) layer inserted into the conventional AlGaN/GaN HEMT structure. Assisted by the InGaN layers polarization field that is opposite to that in the AlGaN layer, an additional potential barrier is introduced between the 2-DEG channel and buffer, leading to enhanced carrier confinement and improved buffer isolation. For a sample grown on sapphire substrate with MOCVD-grown GaN buffer, a 2-DEG mobility of around 1300 cm/sup 2//V/spl middot/s and a sheet resistance of 420 /spl Omega//sq were obtained on this new DH-HEMT structure at room temperature. A peak transconductance of 230 mS/mm, a peak current gain cutoff frequency (f/sub T/) of 14.5 GHz, and a peak power gain cutoff frequency (f/sub max/) of 45.4 GHz were achieved on a 1/spl times/100 /spl mu/m device. The off-state source-drain leakage current is as low as /spl sim/5 /spl mu/ A/mm at V/sub DS/=10 V. For the devices on sapphire substrate, maximum power density of 3.4 W/mm and PAE of 41% were obtained at 2 GHz.     

Fabrication of large-scaled organic light emitting devices on the flexible substrates using low-pressure imprinting lithography

This paper demonstrates an approach to fabricate large-scaled (70 /spl times/70 mm) patterned organic light-emitting devices (ITO/CuPc/NPB/Alq3/LiF/Al) on the flexible polyethyleneterephthalate substrates using low-pressure imprinting lithography. The patterns of the pixel array were defined in crossed-strip style with anode patterned by imprinting techniques followed by wet chemical etching and cathode strips deposited using metal mask. The measured results were: The turn-on voltage of the device was 7.5 V; the luminous efficiency reached 1.13 lm/W (3.04 cd/A) at a luminance of 3.8 cd/m/sup 2/ and its maximum luminance was 2440 cd/m/sup 2/, which were comparable to the performances of the devices patterned by conventional photolithography.     

White LED based on polyfluorene Co-polymers blend on plastic substrate

We report on high-performance, white light emission from polyfluorene co-polymers blend and study of the opto-electrical properties of polymer blend light-emitting devices (PLEDs) fabricated on plastic substrate. Our results show that efficient white light emission via energy transfer, producing higher device efficiencies and luminance in comparison with the conventional single PLEDs, can be realized by blending carrier donor (host) and acceptor (guest) organic polyfluorene co-polymers. A maximum luminance of /spl sim/7400 cd/m/sup 2/ was achieved at 13 V with Internationale de L'Eclairage coordinates of (0.33, 0.33). Maximum emission efficiency of /spl sim/2.0 cd/A and power efficiency of /spl sim/1.1 lm/W are obtained for white light PLEDs on plastic substrate.     

Low-Temperature Materials and Thin Film Transistors for Flexible Electronics

This paper addresses the low-temperature deposition processes and electronic properties of silicon based thin film semiconductors and dielectrics to enable the fabrication of mechanically flexible electronic devices on plastic substrates. Device quality amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a-SiN/sub x/) films and thin film transistors (TFTs) were made using existing industrial plasma deposition equipment at the process temperatures as low as 75/spl deg/C and 120/spl deg/C. The a-Si:H TFTs fabricated at 120/spl deg/C demonstrate performance similar to their high-temperature counterparts, including the field effect mobility (/spl mu//sub FE/) of 0.8 cm/sup 2/V/sup -1/s/sup -1/, the threshold voltage (V/sub T/) of 4.5 V, and the subthreshold slope of 0.5 V/dec, and can be used in active matrix (AM) displays including organic light emitting diode (OLED) displays. The a-Si:H TFTs fabricated at 75/spl deg/C exhibit /spl mu//sub FE/ of 0.6 cm/sup 2/V/sup -1/s/sup -1/, and V/sub T/ of 4 V. It is shown that further improvement in TFT performance can be achieved by using n/sup +/ nc-Si contact layers and plasma treatments of the interface between the gate dielectric and the channel layer. The results demonstrate that with appropriate process optimization, the large area thin film Si technology suits well the fabrication of electronic devices on low-cost plastic substrates.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-K dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-K dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/ A(2-5 /spl times/ 10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8 /spl times/ 10/sup 17/ cm/sup -3/ eV/sup -1/ to 1, 3 /spl times/ 10/sup 19/ cm/sup -3/ eV/sup -1/ somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-K/gate stacks, relative comparison among them and to the Si-SiO/sub 2/ system.     

A novel program-erasable high-/spl kappa/ AlN-Si MIS capacitor

We demonstrate a programmable-erasable MIS capacitor with a single layer high-/spl kappa/ AlN dielectric on Si having a high capacitance density of /spl sim/5 fF//spl mu/m/sup 2/. It has low program and erase voltages of +4 and -4 V, respectively. Such an erase function is not available in other single layer Al/sub 2/O/sub 3/, AlON, or other known high-/spl kappa/ dielectric capacitors, where the threshold voltage (V/sub th/) shifts continuously with voltage. This device exhibits good data retention with a V/sub th/ change of only 0.06 V after 10 000 s.     

High-voltage normally off GaN MOSFETs on sapphire substrates

Gallium nitride self-aligned MOSFETs were fabricated using low-pressure chemical vapor-deposited silicon dioxide as the gate dielectric and polysilicon as the gate material. Silicon was implanted into an unintentionally doped GaN layer using the polysilicon gate to define the source and drain regions, with implant activation at 1100/spl deg/C for 5 min in nitrogen. The GaN MOSFETs have a low gate leakage current of less than 50 pA for circular devices with W/L=800/128 /spl mu/m. Devices are normally off with a threshold voltage of +2.7 V and a field-effect mobility of 45 cm/sup 2//Vs at room temperature. The minimum on-resistance measured is 1.9 m/spl Omega//spl middot/cm/sup 2/ with a gate voltage of 34 V (W/L=800/2 /spl mu/m). High-voltage lateral devices had a breakdown voltage of 700 V with gate-drain spacing of 9 /spl mu/m (80 V//spl mu/m), showing the feasibility of self-aligned GaN MOSFETs for high-voltage integrated circuits.     

Engineering density of semiconductor-dielectric interface states to modulate threshold voltage in OFETs

Threshold-voltage control is critical to the further development of pentacene organic field-effect transistors (OFETs). In this paper, we demonstrate that the threshold voltage can be tuned through chemical treatment of the gate dielectric layer. We show that oxygen plasma treatment of an organic polymer gate dielectric, parylene, introduces traps at the semiconductor-dielectric interface that strongly affect the OFET performance. Atomic force microscopy, optical microscopy using crossed-polarizers, and current-voltage and capacitance-voltage characterization were performed on treated and untreated devices. A model is presented to account for the effects of trap-introduced charges, both 1) fixed charges (2.0/spl times/10/sup -6/ C/cm/sup 2/) that shift the threshold voltage from -17 to +116 V and 2) mobile charges (1.1/spl times/10/sup -6/ C/cm/sup 2/) that increase the parasitic bulk conductivity. This technique offers a potential method of tuning threshold voltage at the process level.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-/spl kappa/ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-/spl kappa/ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/A(2-5/spl times/10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ to 1.3/spl times/10/sup 19/ cm/sup -3/eV/sup -1/, somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/spl kappa//gate stacks, relative comparison among them and to the Si--SiO/sub 2/ system.     

InAlN/GaN HEMTs: a first insight into technological optimization

High-electron mobility transistors (HEMTs) were fabricated from heterostructures consisting of undoped In/sub 0.2/Al/sub 0.8/N barrier and GaN channel layers grown by metal-organic vapor phase epitaxy on (0001) sapphire substrates. The polarization-induced two-dimensional electron gas (2DEG) density and mobility at the In/sub 0.2/Al/sub 0.8/N/GaN heterojunction were 2/spl times/10/sup 13/ cm/sup -2/ and 260 cm/sup 2/V/sup -1/s/sup -1/, respectively. A tradeoff was determined for the annealing temperature of Ti/Al/Ni/Au ohmic contacts in order to achieve a low contact resistance (/spl rho//sub C/=2.4/spl times/10/sup -5/ /spl Omega//spl middot/cm/sup 2/) without degradation of the channels sheet resistance. Schottky barrier heights were 0.63 and 0.84 eV for Ni- and Pt-based contacts, respectively. The obtained dc parameters of 1-/spl mu/m gate-length HEMT were 0.64 A/mm drain current at V/sub GS/=3 V and 122 mS/mm transconductance, respectively. An HEMT analytical model was used to identify the effects of various material and device parameters on the InAlN/GaN HEMT performance. It is concluded that the increase in the channel mobility is urgently needed in order to benefit from the high 2DEG density.     

薄膜绝缘层对陶瓷厚膜电致发光显示器件的影响

采用丝网印刷技术，在Al2O3陶瓷板上印刷、高温烧结内电极及绝缘层制备出陶瓷厚膜基板，进而制备了新型厚膜电致发光显示器（TDEL），整个器件结构为陶瓷基板／内电极／厚膜绝缘层／发光层／薄膜绝缘层／ITO透明电极。对用不同薄膜绝缘材料制备的显示器件的特性进行测试、比较、分析，结果表明薄膜绝缘介质层对器件的阈值电压、发光亮度均有一定的影响，以复合绝缘层的性能最优。最后对器件的衰减特性进行了初步分析。     

4 kV 4H-SiC epitaxial emitter bipolar junction transistors

In this paper, we present 4H-SiC bipolar junction transistors (BJTs) with open-base blocking voltage (BV/sub CEO/) of 4000 V, specific on-resistance (R/sub on,sp/) of 56 m/spl Omega/-cm/sup 2/, and common-emitter current gain /spl beta//spl sim/9. These devices are designed with interdigitated base and emitter fingers with multiple emitter stripes. We assess the impact of design (emitter stripe width and contact spacing) on device performance and also examine the effect of emitter contact resistance on the device forward conduction characteristics.     

An amorphous silicon triode rectifier switching device for active-matrix liquid-crystal display

A triode rectifier switching (TRS) device composed of two amorphous silicon (a-Si) diodes and one resistor has been demonstrated experimentally to be a good switching device for active-matrix liquid-crystal display (AMLCD). The output and transfer characteristics of a TRS are very similar to those of an a-Si thin-film transistor. High on/off current ratio (>5/spl times/10/sup 6/) and low off-state leakage currents (<0.4 pA) have been demonstrated with a-Si diodes and a-Si resistor, indicating that the TRS is suitable for high-performance switching devices for AMLCD.     

Surface passivation of InGaP/InGaAs/GaAs pseudomorphic HEMTs with ultrathin GaS film

We report on the successful surface passivation of wide recess InGaP/InGaAs/GaAs pseudomorphic HEMTs with MBE-grown ultrathin GaS film (2 nm) employing a single precursor, tertiarybutyl-galliumsulfide-cubane ([(t-Bu)GaS]/sub 4/). At the recess length of 1.1 /spl mu/m, a GaS-passivated device with a 0.5-/spl mu/m gate length has the maximum transconductance (g/sub m max/) of 347 mS/mm, which is about 40% higher than that of 240 mS/mm for a device without GaS passivation. We found that one of the causes of an increased g/sub m max/ is the decrease of sheet resistance on the recessed surface because GaS passivation has reduced the depletion layer. Meanwhile, the two-terminal gate-to-drain reverse breakdown voltage (BV/sub gd/) was reduced after GaS passivation. The BV/sub gd/ is independent of the recess length between gate and drain (L/sub gd/) for GaS-passivated devices, unlike that for devices without GaS passivation. According to our calculation of the BV/sub gd/ involving the effects of impact ionization and the interface state, the BV/sub gd/ becomes almost independent of the L/sub gd/, when the interface state density (N/sub int/) is below 1/spl times/10/sup 12/ cm/sup -2/. Then, the calculated surface potential at the recess region is less than 0 eV. This result suggests that GaS passivation can remarkably reduce the N/sub int/ at the recess region.     

Output power density of 5.1/mm at 18 GHz with an AlGaN/GaN HEMT on Si substrate

Microwave frequency capabilities of AlGaN/GaN high electron mobility transistors (HEMTs) on high resistive silicon (111) substrate for power applications are demonstrated in this letter. A maximum dc current density of 1 A/mm and an extrinsic current gain cutoff frequency (F/sub T/) of 50 GHz are achieved for a 0.25 /spl mu/m gate length device. Pulsed and large signal measurements show the good quality of the epilayer and the device processing. The trapping phenomena are minimized and consequently an output power density of 5.1 W/mm is reached at 18 GHz on a 2/spl times/50/spl times/0.25 /spl mu/m/sup 2/ HEMT with a power gain of 9.1dB.     

High linearity InGaP/GaAs power HBTs by collector design

Improved power linearity of InGaP/GaAs heterojunction bipolar transistors (HBTs) with collector design is reported. The collector design is based on nonuniform collector doping profile which is to employ a thin high-doping layer (5/spl times/10/sup 17/ cm/sup -3//200 /spl Aring/) inside the collector (1/spl times/10/sup 16/ cm/sup -3//7000 /spl Aring/). The additional thin high-doping layer within the collector shows no obvious effects and impacts in dc characteristics and device fabrication if the layer was inserted close to the subcollector. For an HBT with a thin high-doping layer being inserted 4000 /spl Aring/ from the base-collector junction, the experimental result on third-order intermodulation demonstrates the significant reduction by as large as 9 dBc and improved IIP3 by 5 dB under input power of -10 dBm at frequency of 1.8 GHz.     

Recessed-gate structure approach toward normally off high-Voltage AlGaN/GaN HEMT for power electronics applications

A recessed-gate structure has been studied with a view to realizing normally off operation of high-voltage AlGaN/GaN high-electron mobility transistors (HEMTs) for power electronics applications. The recessed-gate structure is very attractive for realizing normally off high-voltage AlGaN/GaN HEMTs because the gate threshold voltage can be controlled by the etching depth of the recess without significant increase in on-resistance characteristics. With this structure the threshold voltage can be increased with the reduction of two-dimensional electron gas (2DEG) density only under the gate electrode without reduction of 2DEG density in the other channel regions such as the channel between drain and gate. The threshold-voltage increase was experimentally demonstrated. The threshold voltage of fabricated recessed-gate device increased to -0.14 V while the threshold voltage without the recessed-gate structure was about -4 V. The specific on-resistance of the device was maintained as low as 4 m/spl Omega//spl middot/cm/sup 2/ and the breakdown voltage was 435 V. The on-resistance and the breakdown voltage tradeoff characteristics were the same as those of normally on devices. From the viewpoint of device design, the on-resistance for the normally off device was modeled using the relationship between the AlGaN layer thickness under the gate electrode and the 2DEG density. It is found that the MIS gate structure and the recess etching without the offset region between recess edge and gate electrode will further improve the on-resistance. The simulation results show the possibility of the on-resistance below 1 m/spl Omega//spl middot/cm/sup 2/ for normally off AlGaN/GaN HEMTs operating at several hundred volts with threshold voltage up to +1 V.     

Optical and electrical properties of nanostructured metal-silicon-metal photodetectors

We report an experimental evaluation of the performance of silicon (Si) photodetectors incorporating one-dimensional (1-D) arrays of rectangular and triangular-shaped nanoscale structures within their active regions. A significant (/spl sim/2/spl times/) enhancement in photoresponse is achieved in these devices across the 400- to 900-nm spectral region due to the modification of optical absorption properties that results from structuring the Si surface on physical optics scales smaller than the wavelength, which both reduces the reflectivity and concentrates the optical field closer to the surface. Both patterned (triangular and rectangular lineshape) and planar Ni-Si back-to-back Schottky barrier metal-semiconductor-metal photodetectors on n-type (/spl sim/5/spl times/10/sup 14/ cm/sup -3/) bulk Si were studied. 1-D /spl sim/50-250-nm linewidth, /spl sim/1000-nm depth, grating structures were fabricated by a combination of interferometric lithography and dry etching. The nanoscale grating structures significantly modify the absorption, reflectance, and transmission characteristics of the semiconductor: air interface. These changes result in improved electrical response leading to increased external quantum efficiency (from /spl sim/44% for planar to /spl sim/81% for structured devices at /spl lambda/=700 nm). In addition, a faster time constant (/spl sim/1700 ps for planar to /spl sim/600 ps for structured at /spl lambda/=900 nm) is achieved by increasing the absorption near the surface where the carriers can be rapidly collected. Experimental quantum efficiency and photocurrents results are compared with a theoretical photocurrent model based on rigorous coupled-wave analysis of nanostructured gratings.