An Approach to Multi-Service Subscriber Loop System Using Packetized Voice/Data Terminals

A new subscriber communication system and its design philosophy are described. In addition to telephone communication, the system is simultaneously able to offer data communication, still picture communication, etc. The system is composed of a packetized voice/data terminal, a multi-service switching equipment and the digital subscriber loop connecting between them. The system utilizes the existing subscriber line efficiently and is entirely suitable for coming telephone and data public digital network. 64 kbit/s PCM coded voice conversation and 48 kbit/s data communication were achieved simultaneously over 96 kbit/s digital subscriber line which was spanned up to 2 km.     

Subscriber Line Equipment for an Elastic Carrier Switching System

This is the third of three papers [l], [2] dealing with an elastic carrier-concentrator system. The functioning of the subscriber line equipment is described herein. The system serves 256 telephone subscriber lines by digital concentration switching and transmission of multiplexed message channels over a singleT1transmission line. The concentration switching function is nonblocking. Message channels are the individual communication links between terminals and are created on demand at the request of active subscriber lines. They are not merely inactive without service requests; they do not exist unless service is requested. The created message channels serve for their normal communication function and, in addition, carry for each line the ancillary functions of dialing, ringing, and pay-station coin disposal. Message channels are coded by delta modulation, which permits flexible digital concentration and provides a smooth tradeoff of channel quality versus the instantaneous traffic load. Each of two complementary subscriber line interface units, one per line at each end, provides the delta-modulation encoding and decoding functions for the analog voice-band signal input and output and, by overriding the delta codec, provides the desired signaling functions of dialing, ringing, etc. The line interface units provide the major equipment interface between the subscriber line and the digitalT1line. An integral test facility permits remote loop-back of any selected subscriber line unit via a test channel to the office terminals and at the same time connects the subscriber loop to an auxiliary programmed test facility which may transmit pertinent loop-test results to the office terminal.     

Progress Towards Digital Subscriber Line Services and Signaling

With digital connectivity, future subscribers will be able to exercise local and network services involving the routine delivery, management, and processing of information. Accelerated by rapidly advancing technology, the evolutionary process towards digital connectivity and integrated voice and data services in the network is underway. This paper describes the methods of integrating voice and information capability into the telecommunications network. The attributes of this network will include the availability of digital connectivity directly to the subscriber, the availability of a robust signaling means between the subscriber and his local switching office, and common channel signaling to implement all interexchange signaling. Issues of interest include an overview of digital subscriber connectivity, signaling and information structures for these kinds of lines, communications protocols, and general network considerations for the provision of information services. Partitioning of intelligence between intelligent subscriber terminals and controllers and their switching system is investigated. The use of message and virtual channel switching facilities to handle limited information rate services is discussed. Finally, an exploratory digital subscriber line under investigation at Bell Laboratories is described.     

10 /spl Omega/ 370 V high voltage switches for line circuit application

The authors describe the integration of 8 high-voltage switches together with their low-voltage polygate CMOS control logic in an 18-pin package, the HVX chip. This custom IC is intended to be used as a switching cross-point between the subscriber line and circuit equipment in digital telephony. The high-voltage DMOS is processed in a dielectrically isolated substrate, and allows the switches to have both terminals floating with respect to the low-voltage circuitry. A novel control circuit guarantees that the switch status will be defined under all circumstances.     

Monolithic 70 V bipolar line driver IC for PCM SLIC

Describes a monolithic 70 V IC which is an integral part of a PCM subscriber line interface circuit (SLIC). A special design allows the realization of a line driving operational amplifier with stringent requirements on power drive, consumption, output overload protection and breakdown voltage. Other special SLIC functions are also implemented. Experimental results demonstrate the performance of the chip.     

A Subscriber Carrier System Based Upon Frame Addressing System

A new channel assignment scheme called a frame addressing system is proposed in this paper to realize an efficient telephone subscriber carrier system by means of PCM loop having a simplified switching capability at each subscriber. In the frame addressing system, a speech signal time slot is assigned by sending a bit for each subscriber at the beginning of each transmission frame. This results in an improvement of efficiency by a TASI-like effect in addition to efficiency by switching. The principle and an example of a practical circuit are described. Characteristics of the system are analyzed and a design example is described.     

Design Philosophy and Hardware Implementation for Digital Subscriber Loops

This paper presents various requirements and configurations in the information network system (INS) NTT's version of the integrated services digital network (ISDN)- such as field trials, and technologies and equipment design of the digital subscriber loop using balanced wire pairs. The main aspects characterizing digital subscriber loops, are a customer access structure, a digital transmission system on existing subscriber loops, and customer interface. A configuration of two-wire digital subscriber loops with two customer access channels, which is adopted in the field trials, will be described. The time-shared two-wire digital transmission and power feeding methods on subscriber loops are discussed. The common mode rejection ratio (CMRR) is discussed in detail, since CMRR is one of the main factors which affects the transmission ability of balanced wire pairs. A proposed self-clocked four-wire customer interface utilizes time division multiplexing technique. The digital subscriber loop operates on a call-by-call basis for link establishment to avoid excessive power dissipations as well as to avoid impairments caused by crosstalk from other lines within a cable. Its design objectives and implementation are also discussed.     

A floating, low-power subscriber line interface circuit [bipolar IC technology]

A subscriber line interface circuit is described which is smaller than and dissipates substantially less heat than conventional circuits which perform similar functions. Worst case heat dissipation in the circuit is only 0.65 W as compared to conventional arrangements which dissipate up to 4 W. The battery feed function is accomplished by a small 1.5 W DC-to-DC converter which also includes circuitry for detecting loop supervisory functions. The floating nature of the output circuitry renders it immune to power line induction and common mode power crosses. Primary protection from lightning and other induced surges utilizes conventional carbon block type protectors. Secondary circuit protection is accomplished with a high voltage diode and simple carbon composition resistor. Circuit disconnect is accomplished with a medium voltage SCR for ringing and loop testing the subscriber line. The battery feed control and loop supervisory functions have been realized in a low voltage, linear integrated circuitry using CBIC technology.     

Integrated electronic subscriber line interface circuit with ringing on chip

A new high-voltage, dielectrically isolated, complementary bipolar technology has been used to integrate high-voltage functions of a subscriber line interface circuit (SLIC). This circuit, in conjunction with a complementary low-voltage junction isolated bipolar integrated circuit, implements most of the line interface functions required for digital telephone switches. Partitioning of the junctions is based on technology requirements, and the two chips are encapsulated in 28-pin package.     

Rural Subscriber Physical Loops

This paper briefly traces the development of physical subscriber loop design in the Rural Electrification Administration (REA) Program from 1949 to the present. Development of equipment for overcoming in the most economical manner the signaling and transmission problems encountered with long subscriber loops is also discussed. This includes loading systems for wider bandwidth, better structural return loss, less bridging effects with multiparty lines; loop extenders in place of costly long-line adapters (LLA's); lower cost voice-frequency repeaters (VFR's) and switching methods such as Common-Mode Operation (CMO) where less equipment is required. Discussion of the problems still encountered with transmission and signaling on rural subscriber loop is presented with ideas for solution. Development of VFR equipment with automatic gain control for use in CMO or Common-Control Central offices would permit designing to common circuit net loss and minimize contrast between circuits. Extension of signaling limits of central office equipment (COE) now being developed could eliminate the need for external loop extension equipment on better than 90 percent of rural subscriber loops. Development of a telephone instrument requiring less dc line current would eliminate the need for elevated line voltages.     

A CMOS SLIC with an automatic balancing hybrid

A CMOS subscriber line interface circuit (SLIC) that has an automatic balancing hybrid facility is presented. Some of the key system aspects of line interface circuits, such as the relation between zero-loss switching and an automatic balancing hybrid circuit, power dissipation in the line circuit, and foreign voltage protection are described first. Next, details of the SLIC LSI, which comprises a dial pulse detecting circuit and and automatic balancing hybrid circuit, are described. The LSI is implemented with CMOS switched capacitor technology and is mounted on a 20-in DIL.     

ISDN-Oriented Modular VLSI Chip Set for Central-Office and PABX Applications

This paper describes a new ISDN-oriented modular (IOM®) architecture developed to establish the subscriber basic access to an Integrated Services Digital Network in a central-office or PABX environment with a minimum number of VLSI circuits. A four-component VLSI chip set is presented, consisting of the S-bus interface circuit (SBC), the ISDN burst transceiver circuit (IBC), and the ISDN echo cancellation circuit (IEC) for layer 1 data transmission at the fourwireSand the two-wireUinterface, respectively, and the ISDN communication controller for layer 2 link access protocol control. The development strategy, the functions of the IC's, and examples for their application in the subscriber terminal and digital subscriber line board are emphasized.     

Peripheral board controller for digital exchange systems

The controller implements a redundant PCM highway port and a 4-Mb serial communication link. Typical features are variable time slot assignment for up to 16 subscribers, processing of status signaling and feature control data, and high level support of the HDLC (high-level data link control) communications protocol. The circuit represents an innovative step in the development of modern subscriber boards in digital switching systems, particularly in the area of fully digital voice and data transmission capability. The circuit is realized in a 3.5-/spl mu/m NMOS process and contains more than 22000 transistors on a 7.24/spl times/5.24 mm die area.     

Selection of Call Progress Tones for Digital Systems

The precise tone system based on the four basic frequencies 350, 440, 480, and 620 Hz is extensively used in switching systems to indicate readiness to dial, ringing of the called subscriber, lines or trunks busy, and other conditions. In digital switching systems it is normally advantageous to generate and process these tones in a digital form. It is shown that by judicious selection of the tone frequencies, considerable simplification of digital tone generators may be achieved. Modification of the precise tone frequencies within ± 0.5 percent reduces the number of samples which must be stored in ROM's from 1650 to 326. Another set of frequencies is given which requires only 228 samples and simplifies the tone generator readout logic.     

One-stage one-sided rearrangeable switching networks

Switching networks consisting of subscriber lines and crosswires connected by switches are considered. A connection between two subscribers is made along one crosswire via two switches. The minimum number of switches necessary for such a switching network to be rearrangeably nonblocking is determined and a switching arrangement which achieves this minimum for any (even) number of subscriber lines is constructed. Two procedures for assignment of crosswires to subscriber line pairs are described. One makes the correct choice of connection route without backtracking provided all connections are known beforehand; the other determines a rearrangement of existing assignments when a new connection is required. The switching networks which have the minimum number of switches for networks with up to eight subscriber lines and give nonisomorphic solutions for larger networks are characterized     

Switching System Software Design for ISDN

The ISDN offers various services through multipurpose digital subscriber lines. The switching program for the ISDN should be so designed as to realize the control of various voice and nonvoice services and provide for developing service enhancement. To attain the goal, the ISDN services are classified hierarchically and each category is allocated to appropriate network nodes for implementation. As a result, the local switching program provides an out-slot subscriber line signaling capability and call connection with appropriate compatibility checking including a check for access capability to communications processing nodes. The switching program modules specific to analog services and those specific to digital services are separated to allow the use of the existing program file and to afford easy program design and maintenance. Remote-controlled switching is a suitable means for an economical introduction of the ISDN services to low traffic density areas. Special routing and reliability arrangements as well as the program structure for a remote-controlled switch are discussed.     

Special ICs in digital switching-an overview

Traces the influence of special-purpose integrated and LSI circuits in digital switching systems. The existence of custom digital chips, codecs and filters, and high- and low-voltage analog cross-point arrays is related to the choice between alternative architectures. Recent trends toward replacing mature components such as transformers by subscriber line interface circuits (SLICs) are outlined.     

A four-channel digital signal processor in 1.2-μm CMOS withon-chip D/A and A/D conversion serving four speech channels in anew-generation subscriber line circuit

The major component for a new-generation line circuit was designed and fabricated in a 1.2-μm CMOS technology. The circuit includes digital signal processing of receive (RX) and transmit (TX) signals as well as the analog front end of four subscriber lines to a PCM (pulse code modulation) digital exchange. The device operates on a single 5-V power supply. The four-channel digital signal-processor including the analog front ends is fabricated on a 40-mm² 1.2-μm CMOS die area. The DSP functions, the RX and TX filters, the decimator, the interpolator, and the A/μ-law transcoder are included as independent data paths, one for the TX and RX filters, one for the decimator, and another for the interpolator, the digital sigma-delta modulator, and the transcoder. The on-chip analog front end contains a notch filter to cancel the 12/16-kHz payphone signal, a switched-capacitor PDM A/D and D/A converter, and smoothing filters. On the first measured samples, the signal-to-distortion ratio is measured to be 33 dB at -45 dBmo for -7 dB gain setting     

The Loop Coverage Comparison Between TCM and Echo Canceller Under Various Noise Considerations

This paper describes loop coverage evaluations of two-wire digital subscriber transmission systems to support the CCITT recommended 1-430 interface. Several range-limiting factors are discussed and a cable utility design for two representative two-wire digital subscriber transmission systems is presented. The two transmission systems are time compression multiplexing (TCM) and echo canceller (EC), utilizing the AMI line code and full cosine rolloff line equalization for both systems. A new impulse noise evaluation is applied to cable utility design, because impulse noise is one of the most stringent range-limiting factors, especially for TCM in utilizing existing subscriber loops. Comparison of TCM with EC is also carried out according to various range-limiting factors. As a result, it is noted that the 320 kbit/s line bit rate TCM is more applicable in NTT's exchange area coverage than the 160 kbit/s EC to achieve the2B + Dbasic interface transmission.     

Adiabatic-CMOS/CMOS-adiabatic logic interface circuit

This paper describes the design of an adiabatic-CMOS/CMOS-adiabatic logic interface circuit for a group of low-power adiabatic logic families with a similar clocking scheme. The circuit provides interfacing between several recently proposed low-power adiabatic logic circuits and traditional digital CMOS circuits. One advantage of this design is that it is insensitive to clock overlap. With the proposed interface circuit, both adiabatic and CMOS logic circuits are able to co-exist on a single chip, taking advantage of the strengths of each approach in the design of low power systems.