Gate turn-off in p-n-p-n devices

A simple two-dimensional model for gated turn-off of a p-n-p-n device is used to derive an expression relating the storage time and the turn-off gain. The observed dependence of storage time on turn-off gain fits the derived expression well for devices specially fabricated consistant with the assumptions of the model. The fall time is discussed qualitatively.     

Gate resistance modeling of multifin MOS devices

This letter studies the effects of geometrical parameters (fin spacing, fin height and polysilicon thickness) on the gate resistance of multifin MOS devices. An effective lumped resistance model derived from distributed RC network is formulated and verified using a two-dimensional simulator. Based on the model, a design guideline for the fin spacing to minimize the gate resistance and RC delay is provided to design multifin MOS devices for high frequency applications.     

Gate oxide integrity of MOS/SOS devices

Time-dependent dielectric breakdown and ramp-voltage oxide breakdown measurements were used to evaluate the oxide integrity of MOS/SOS devices fabricated by a 3-µm process with a 500-Åthick gate oxide and dry-etched silicon islands. Field and temperature acceleration factors were determined on device arrays which ranged from 1 to 1000 devices. The measured temperature and field acceleration factors are used to give reasonable stress conditions for elimination of defective multiple device arrays without significantly altering the wear out time for nondefective arrays. Extrapolation of the data is used to suggest stress conditions and predict wear out time for 4K RAM's.     

Concerning the onset of heavy inversion in MIS devices

The accepted touchstone for the onset of heavy inversion in metal-insulator-semiconductor (MIS) devices is the condition that the minority carrier density at the surface equals the bulk impurity concentration. It is not always clear how to use that definition in practical problems. In this letter we propose a new definition, and we demonstrate that it leads to the same physical conditions for the onset of heavy inversion as does the heretofore conventional criterion.     

Processing of InP MIS devices monitored via photoluminescence measurements

A remarkable one-to-one correlation is observed between photoluminescence (PL) intensity and surface state density in the upper part of the gap of n-type InP. Measurement of the PL intensity is shown to be a simple and efficient method for monitoring each individual technological step of fabrication of MIS devices on InP.     

Gate leakage reduction for scaled devices using transistor stacking

In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (L/sub eff/) of 25nm (oxide thickness=1.1 nm), 50 nm (oxide thickness=1.5 nm) and 90 nm (oxide thickness=2.5 nm) is studied using device simulation. Overall leakage in a stack of transistors is modeled and the opportunities for leakage reduction in the standby mode of operation are explored for scaled technologies. It is shown that, as the contribution of gate leakage relative to the total leakage increases with technology scaling, traditional techniques become ineffective in reducing overall leakage current in a circuit. A novel technique of input vector selection based on the relative contributions of gate and subthreshold leakage to the overall leakage is proposed for reducing total leakage in a circuit. This technique results in 44% savings in total leakage in 50-nm devices compared to the conventional stacking technique.     

Gate capacitance attenuation in MOS devices with thin gatedielectrics

As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the silicon and polysilicon electrodes. For the first time, we quantitatively explore the combined impact of degenerate carrier statistics, quantum effects, and the semiconducting nature of the gate electrode on gate capacitance. Only by including all of these effects can we successfully model the capacitance-voltage behavior of sub-10 nm MOS capacitors. For typical devices, we find the gate capacitance to be 10% less than the oxide capacitance, but it can be attenuated by 25% or more for 4 nm oxides with polysilicon gates doped to less than 10²⁰ cm^-3     

Charge-coupled devices? A new approach to MIS device structures

Recent advances in materials and processing have resulted in a new class of information-handling structure?the charge-coupled device. This three-layer structure creates and stores minority carriers, or their absence, in potential wells near the surface of the semiconductor. The minority carriers move from under one electrode to a closely adjacent electrode on the same substrate when a more negative voltage is applied to the adjacent electrode. Because of their high transfer efficiency, these devices have already found application as image sensors. In addition, there is every expectation that memories made by use of the stored-charge concept will be less expensive and faster, and will require less power than a magnetic counterpart now in use.     

A comprehensive analytical model for metal-insulator-semiconductor(MIS) devices

A comprehensive model for metal-insulator-semiconductor (MIS) devices under dark conditions which consists of a wide range of parameters has been developed. Parameters neglected by other authors have been included. The effects of surface states, silicon dioxide thickness, substrate doping, fixed oxide charges, substrate thickness, and metal work function are taken into account. The permittivity and barrier height of thin oxide are included in the calculation. The limits on equilibrium and nonequilibrium are explored     

Electroluminescence from cadmium sulphide MS,MIS and SIS devices

The nature of electroluminescence in surface barrier structures of CdS has been investigated by studying clean and contaminated surface structures, conventional metal-insulator-semiconductor (MIS) devices, and by comparing the emissions with semiconductor-insulator-semiconductor (SIS) structures. Crystals cleaved and gold coated in high vacuum gave no electroluminescence under forward bias, indicating that the use of clean surfaces does not assist in obtaining efficient emission. However, contrary to previous reports, luminescence was obtained from air cleaved AuCdS devices. Both these devices and MIS structures (using collodion or SiO_x as insulator) were some two orders of magnitude less efficient than SIS devices made previously in this laboratory from the same CdS material. These results can be explained if the hole injection process is analysed using momentum conservation considerations, and leads to guidelines for device design taking band structure into account.     

Current conduction mechanism of MIS devices using multidimensional minimization system program

The present work presents an evaluation approach which enables the in-depth analysis of current–voltage (I–V) characteristics of MIS devices to determine their current transport mechanisms using a multidimensional minimization system program.Exemplarily, the current transport mechanisms were determined for a TiN/SiO₂/p-Si MOS and a TaN/HfSiO/SiO₂/p-Si MIS structure by fitting the analytical expressions for different current transport mechanisms to experimental I–V data in a wide range of applied biases and temperatures. The considered mechanisms for the investigated samples include temperature dependent Fowler–Nordheim (FN) tunneling and Poole–Frenkel (PF) emission as well as ohmic conduction. The presented approach can easily be extended to account for additional mechanisms such as trap assisted tunneling (TAT) if relevant for different samples. In contrast to typical extraction procedures which determine current conduction mechanism parameters sequentially, in this work, the adjustable fit parameters are extracted in a single operation using the Levenberg–Marquardt algorithm (Nash, 1990) to obtain a least-square fit of the model to measured I–V characteristics. Thus, simultaneously occurring current mechanisms can properly be evaluated which allows to determine the fraction of each conduction mechanism quantitatively for each voltage.     

便携设备的ESD保护器件

随着移动电话、PDA、MP3播放机以及数码相机等的迅速发展,便携电子设备需求出现热潮,消费者正要求越来越先进的性能。将来的便携电子设备不仅要能够处理基于数据的正文,而且还要改善图形乃至视频率信息处理能力。与此同时,一方面要求设计者削减元件数量和减小电路板占用的空间,另一方面还要保证达到适当的EMI和ESD的抑制标准。特别是将来,采用亚微米工艺和甚精细线条宽度布线的复杂半导体功能电路,对电路瞬变过程的影响更加敏感,将导致上述的问题更加激化起来。 此外,在工业标准方面,欧共体的IEC 61000-4-2已     

ESD保护器件在多晶硅上的实现

静电放电现象是导致集成电路损坏的一个重要原因,目前绝大多数集成电路中的ESD保护电路都是在硅片上实现的,这将占用一定的硅片面积,提升电路的成本.如果能够在多晶硅层(垂直空间)实现ESD保护器件,就能够节约一定的面积,从而节约成本.介绍了对于在多晶硅上实现的静电保护器件的研究结果.     

Gate current injection initiated by electron band-to-band tunnelingin MOS devices

A substrate hot-electron injection across the gate oxide initiated by electron band-to-band tunneling in p-type silicon is discussed. The injection electrons are generated by the energetic holes which are originally left behind by the band-to-band tunneling electrons. The injection can be easily controlled by an appropriate bias to a nearby n ⁺ diffusion, and the injection efficiency can be as high as 10^-2. Due to the small oxide field during injection, the electron fluence through the oxide before failure is much higher than under a Fowler-Nordheim tunneling stressing. These advantages make this band-to-band tunneling induced substrate hot-electron injection a possible programming mechanism for nonvolatile memories     

A software protection framework for mobile devices

The software protection technology is the main component of modern software security technology. Generally, confusion and encryption methods are using in software protection technology to provide traditional desktop applications. But applications based on mobile devices are also faces with threats such as piracy and tampering. The security problem in existing applications for mobile devices will do far more harm to users than traditional virus, but there is no effective software protection security framework for them. A software application framework for mobile devices is proposed in this paper, and the white box decryption algorithm involved is improved. And it is analyzed in this paper the performance and security of the framework proposed, the operational efficiency of the improved encryption algorithm is verified.     

Optimisation of very low voltage TVS protection devices

This paper is aimed at the design and optimisation of advanced Transient Voltage Suppressors (TVS) devices for IC protection against ESD. A four-layer N⁺P⁺PN⁺ structure has been used to achieve breakdown voltages lower than 3 V. The effect of the critical geometrical and technological parameters on the TVS electrical characteristics is analysed with the aid of technological and electrical simulations. In this sense, the trade-off between voltage capability, leakage current and clamping voltage has been optimised. Fabricated TVS devices exhibit better electrical performances than those of the equivalent three-layer TVS device counterparts.     

光电设备激光防护技术研究进展

为削弱激光对光电设备的损伤,提高复杂战场环境下光电系统的生存能力,光电设备需要采取必要的防护措施。总结了目前基于线性、非线性和相变的激光防护技术和材料,包括薄膜结构、光子晶体结构、聚合物结构、微镜结构等,分别说明了各种结构的防护机制、性能参数、适应性等指标以及未来的研究方向,最后指出激光防护技术的发展趋势。     

高阻硅基GaN晶片上MIS栅结构GaN HEMT射频器件研制

5G 通信中3. 4~3. 6 GHz 是主要使用频段。GaN 射频器件由于高频、低功耗、高线性度等优势,满足5G 通信应用需求。文中在高阻硅基GaN 外延片上研制了AlGaN/GaN 高电子迁移率晶体管(High Electron Mobility Transistor, HEMT),并分析了金属鄄绝缘层鄄半导体(Metal-Insulator-Semiconductor,MIS)栅对器件直流和射频特性的影响。研究发现:相比于肖特基栅结构,MIS 栅结构器件栅极泄漏电流减少2~5 个数量级,漏极驱动电流能力和跨导提高10%以上;频率为3. 5 GHz 时,增益从1. 5 dB 提升到4. 0 dB,最大资用增益从5. 2 dB 提升到11. 0 dB,电流增益截止频率为8. 3 GHz,最高振荡频率为10. 0 GHz。