Experimental high performance sub-0.1 μm channel nMOSFET's

Very high performance sub-0.1 μm channel nMOSFET's are fabricated with 35 Å gate oxide and shallow source-drain extensions. An 8.8-ps/stage delay at V_dd=1.5 V is recorded from a 0.08 μm channel nMOS ring oscillator at 85 K. The room temperature delay is 11.3 ps/stage. These are the fastest switching speeds reported to date for any silicon devices at these temperatures. Cutoff frequencies (f_T) of a 0.08 μm channel device are 93 GHz at 300 K, and 119 GHz at 85 K, respectively. Record saturation transconductances, 740 mS/mm at 300 K and 1040 mS/mm at 85 K, are obtained from a 0.05 μm channel device. Good subthreshold characteristics are achieved for 0.09 μm channel devices with a source-drain halo process     

Highly doped InGaP/InGaAs/GaAs pseudomorphic HEMT's with 0.35 μmgates

We fabricated 0.35-μm gate-length pseudomorphic HEMT DCFL circuits using a highly doped thin InGaP layer as the electron supply layer. The InGaP/InGaAs/GaAs pseudomorphic HEMT grown by MOVPE is suitable for short gate-length devices with a low supply voltage since it does not show short channel effects even for gate length down to 0.35 μm. We obtained a K value of 555 mS/Vmm and a transconductance g_m of 380 mS/mm for an InGaP layer 18.5 nm thick. Fabricated 51-stage ring oscillators show the basic propagation delay of 11 ps and the power-delay product of 7.3 fJ at supply voltage of V_DD of 1 V, and 13.8 ps and 3.2 fJ at V_DD of 0.6 V for gates 10 μm wide     

Inverter performance of 0.10 μm CMOS operating at roomtemperature

The switching performance of 0.10 μm CMOS devices operating at room temperature has been discussed on the basis of both experimental and simulated results. The measured propagation delay time of a 0.10 μm gate length CMOS has been quantitatively divided into intrinsic and parasitic components for the first time. The results have shown that the drain junction capacitance strongly affects the propagation delay time in the present 0.10 μm CMOS. The switching performance of a 0.10 μm ground rule CMOS has been simulated by using device parameters extracted from the experimental results. In the 0.10 μm ground rule CMOS, it has been shown that an increase of the contact resistance will degrade the propagation delay time, which is one of the most essential problems in further device miniaturization. It has been also demonstrated that even if the specific contact resistance ρ_c is reduced to be less than 1×10^-7 Ω cm, further reduction of the gate overlap capacitance C_ov will be required to achieve the propagation delay time to be less than 10 ps in the 0.10 μm ground rule CMOS at room temperature     

Super low noise InGaP gated PHEMT

Very high performance InGaP/InGaAs/GaAs PHEMTs will be demonstrated. The fabricated InGaP gated PHEMTs devices with 0.25 × 160/cm² and 0.25 × 300 μm² of gate dimensions show 304 mA/mm and 330 mA/mm of saturation drain current at V_GS = 0 V, V_DS = 2 V, and 320 mS/mm and 302 mS/mm of extrinsic transconductances, respectively. Noise figures for 160 μm and 300 μm gate-width devices at 12 GHz are measured to be 0.46 dB with a 13 dB associated gain and 0.49 dB with a 12.85 dB associated gain, respectively. With such a high gain and low noise, the drain-to-gate breakdown voltage can be larger than 11 V. Standard deviation in the threshold voltage of 22 mV for 160 μm gate-width devices across a 4-in wafer can be achieved using a highly selective wet recess etching process. Good thermal stability of these InGaP gated PHEMTs is also presented     

Ultrafast operation of Vth-adjustedp+-n+ double-gate SOI MOSFET's

To optimize the V_th of double-gate SOI MOSFET's, we fabricated devices with p⁺ poly-Si for the front-gate electrode and n⁺ poly-Si for the back-gate electrode on 40-nm-thick direct-bonded SOI wafers. We obtained an experimental V_th of 0.17 V for nMOS and -0.24 V for pMOS devices. These double-gate devices have good short-channel characteristics, low parasitic resistances, and large drive currents. For gates 0.19 μm long, front-gate oxides 8.2 nm thick, and back-gate oxides 9.9 nm thick, we obtained ring oscillator delay times of 43 ps at 1 V and 27 ps at 2 V. To our knowledge, these values are the fastest reported for this gate length with suppressed short-channel effects     

Gate length scaling in high performance InGaP/InGaAs/GaAs pHEMTs

The performance of InGaP-based pHEMTs as a function of gate length has been examined experimentally. The direct-current and microwave performance of pHEMTs with gate lengths ranging from 1.0-0.2 μm has been evaluated. Extrinsic transconductances from 341 mS/mm for 1.0 μm gate lengths to 456 mS/mm for 0.5 μm gate lengths were obtained. High-speed device operation has been verified, with f_t of 93 GHz and f_max of 130 GHz for 0.2 μm gate lengths. The dependence of DC and small-signal device parameters on gate length has been examined, and scaling effects in InGaP-based pHEMT's are examined and compared to those for AlGaAs/InGaAs/GaAs pHEMTs. High-field transport in InGaP/InGaAs heterostructures is found to be similar to that of AlGaAs/InGaAs heterostructures. The lower ϵ_r of InGaP relative to AlGaAs is shown to be responsible for the early onset of short-channel effects in InGaP-based devices     

Fully depleted CMOS/SOI device design guidelines for low-powerapplications

We report the fully depleted (FD) CMOS/SOI device design guidelines for low-power applications. Optimal technology, device and circuit parameters are derived and compared with bulk CMOS based design. The differences and similarities are summarized. Device design guidelines using devices with L=0.1 μm for FDSOI low-power applications are presented using an empirical drain saturation current model fitted to experimental data. The model is verified in the deep-submicron regime by two-dimensional (2-D) simulation. For L=0.1 μm FDSOI low-power technology, optimum speed and lower-power occurs at V_dd=3V_th and V_dd=1.5 V_th, respectively. Optimum buried oxide thickness is found to be between 300 and 400 nm for low-power applications. Optimum transistor sizing is when the driver device capacitance is 0.3 times the total load capacitance. Similarly optimum gate oxide thickness is when the driver device gate capacitance is 0.2-0.6 times the total load capacitance for performance and 0.1-0.2 for low-power, respectively. Finally optimum stage ratio for driving large loads is around 2-4 for both high-performance and low-power     

A 0.4-μm gate-length AlGaAs/GaAs P-channel HIGFET with 127-mS/mmtransconductance at 77 K

WN-gate, p-channel AlGaAs-GaAs heterostructure insulated-gate field-effect transistors (HIGFETs) fabricated on a metalorganic vapor-phase epitaxy (MOVPE) wafer are discussed. A self-aligned Mg ion implantation (80 keV, 6×10¹³ cm^-2) annealed at 850°C in an arsine atmosphere and the control of the SiO₂ sidewall dimensions allow the fabrication of p-channel HIGFETs with a gate length smaller than 0.5 μm with low subthreshold current. P-channel HIGFETs with 0.4-μm gate lengths exhibit extrinsic transconductances as high as 127 mS/mm at 77 K and 54 mS/mm at 300 K     

On the SiO2-based gate-dielectric scaling limit forlow-standby power applications in the context of a 0.13 μm CMOS logictechnology

This paper describes a leading-edge 0.13 μm low-leakage CMOS logic technology. To achieve competitive off-state leakage current (I _off) and gate delay (T_d) performance at operating voltages (V_cc) of 1.5 V and 1.2 V, devices with 0.11 μm nominal gate length (L_g-nom) and various gate-oxide thicknesses (T_ox) were fabricated and studied. The results show that low power and memory applications are limited to oxides not thinner than 21.4 Å in order to keep acceptable off-state power consumption at V_cc=1.2 V. Specifically, two different device designs are introduced here. One design named LP (T_ox=26 Å) is targeted for V_cc=1.5 V with worst case I_off <10 pA/μm and nominal gate delay 24 ps/gate. Another design, named LP1 (T_ox=22 Å) is targeted for V_cc =1.2 V with worst case I_off<20 pA/μm and nominal gate delay 27 ps/gate. This work demonstrates n/pMOSFETs with excellent 520/210 and 390/160 μA/μm nominal drive currents at V_cc for LP and LP1, respectively. Process capability for low-power applications is demonstrated using a CMOS 6T-SRAM with 2.43 μm² cell size. In addition, intrinsic gate-oxide TDDB tests of LP1 (T _ox=22 Å) demonstrate that gate oxide reliability far exceeding 10 years is achieved for both n/pMOSFETs at T=125°C and V _cc=1.5 V     

High speed p-type SiGe modulation-doped field-effect transistors

We report on the fabrication and characterization of high-speed p-type modulation-doped field-effect transistors (MODFETs) with 0.7-μm and 1-μm gate-lengths having unity current-gain cut-off frequencies (f_T) of 9.5 GHz and 5.3 GHz, respectively. The devices were fabricated on a high hole mobility SiGe heterostructure grown by ultra-high-vacuum chemical vapor deposition (UHV-CVD). The dc maximum extrinsic transconductance (g_m) is 105 mS/mm (205 mS/mm) at room temperature (77 K) for the 0.7-μm gate length devices. The fabricated devices show good pinch-off characteristics and have a very low gate leakage current of a few μA/mm at room temperature and a few nA/mm at 77 K     

New field-effect transistor with quantum wire and modulation-dopedheterostructures

A new field-effect transistor, consisting of an AlGaAs/GaAs heterostructure and an (AlAs)_0.25(GaAs)_0.75 vertical superlattice, is fabricated. It has a large transconductance of 14 mS/mm at a gate length of 250 μm, corresponding to a transconductance of 3.5 S/mm for 1 μm gate length. Hall measurement revealed a novel FET operation mode called `velocity modulation'     

Effect of gate length on DC performance of AlGaN/GaN HEMTs grown by MBE

The DC performance of AlGaN/GaN high electron mobility transistors grown by plasma-assisted molecular beam epitaxy was investigated for gate lengths in the range 0.1–1.2 μm. On 0.25 μm gate length devices we obtained 40 V_DS operation with >50 mA peak I_D. The peak drain current density was 0.44 A/mm for 100 μm gate width devices with 1.2 μm gate lengths. The extrinsic transconductance (g_m) decreased with both gate length and gate width and was 75 mS/mm for all gate widths for 0.25 μm devices. E-beam written gates typically produced a slightly lower Schottky barrier height than optically patterned gates.     

High-performance sub-quarter-micrometer PMOSFET's on SOI

PMOS transistors with effective channel lengths down to 0.15 μm have been fabricated on silicon-on-insulator (SOI) films. Gate oxide thicknesses of 5.5 and 10 nm are used. These P⁺ gate PMOS devices exhibit excellent short-channel behavior, low-source-drain resistance, and remarkably large current drive and transconductance. for T_ox=5.5 nm, saturation transconductances of 274 mS/mm at 300 K and 352 mS/mm at 80 K are achieved, which are the highest reported values for this oxide thickness. The result is attributed to low series resistance, forward-bias body effect, and the reduction of body charge effect     

Design and performance of 0.1-μm CMOS devices usinglow-impurity-channel transistors (LICT's)

0.1-μm CMOS devices using low-impurity-channel transistors (LICTs) with dual-polysilicon gates have been fabricated by nondoped epitaxial growth technology, high-pressure oxidation of field oxide, and electron-beam lithography. These devices, with gate lengths of 0.135 μm, achieved normal transistor operation at both 300 and 77 K using 1.5-V supply voltage. Maximum transconductances are 203 mS/mm for nMOS transistors and 124 mS/mm for pMOS transistors at 300 K. Low-impurity channels grown on highly doped wells provide low threshold voltages of about 0.35 V for nMOS transistors and about -0.15 V for pMOS transistors at 77 K, and preserve good turn-offs with subthreshold swings of 25 mV/decade at 77 K. LICTs suppress short-channel effects more effectively, compared with conventional devices with nearly uniform dopings     

A low-resistance self-aligned T-shaped gate for high-performancesub-0.1-μm CMOS

This paper describes the high performance of T-shaped-gate CMOS devices with effective channel lengths in the sub-0.1-μm region. These devices were fabricated by using selective W growth, which allows low-resistance gates smaller than 0.1 μm to be made without requiring fine lithography alignment. We used counter-doping to scale down the threshold voltage while still maintaining acceptable short-channel effects. This approach allowed us to make ring oscillators with a gate-delay time as short as 21 ps at 2 V with a gate length of 0.15 μm. Furthermore, we experimentally show that the high circuit speed of a sub-0.1-μm gate length CMOS device is mainly due to the PMOS device performance, especially in terms of its drivability     

Self-aligned GaAs p-channel enhancement mode MOS heterostructurefield-effect transistor

Self-aligned GaAs enhancement mode MOS heterostructure field-effect transistors (MOS-HFET) have been successfully fabricated for the first time. The MOS devices employ a Ga₂O₃ gate oxide, an undoped Al_0.75Ga_0.25As spacer layer, and undoped In_0.2Ga_0.8As as channel layer. The p-channel devices with a gate length of 0.6 μm exhibit a maximum DC transconductance g_m of 51 mS/mm which is an improvement of more than two orders of magnitude over previously reported results. With the demonstration of a complete process flow and 66% of theoretical performance, GaAs MOS technology has moved into the realm of reality     

Experimental 0.1 μm p-channel MOSFET withp+-polysilicon gate on 35 Å gate oxide

Very-high-transconductance 0.1 μm surface-channel pMOSFET devices are fabricated with p⁺-poly gate on 35 Å-thick gate oxide. A 600 Å-deep p⁺ source-drain extension is used with self-aligned TiSi₂ to achieve low series resistance. The saturation transconductances, 400 mS/mm at 300 K and 500 mS/mm at 77 K, are the highest reported to date for pMOSFET devices     

多晶硅双栅全耗尽SOI CMOS器件与电路

对多晶硅双栅全耗尽SO I CM O S工艺进行了研究,开发出了1.2μm多晶硅双栅全耗尽SO I CM O S器件及电路工艺,获得了性能良好的器件和电路。NM O S和PM O S的阈值电压绝对值比较接近,且关态漏电流很小,NM O S和PM O S的驱动电流分别为275μA/μm和135μA/μm,NM O S和PM O S的峰值跨导分别为136.85 m S/mm和81.7 m S/mm。在工作电压为3 V时,1.2μm栅长的101级环振的单级延迟仅为66 ps。     

21-ps 0.1-μm CMOS devices operating at room temperature

High-speed complementary metal-oxide semiconductor (CMOS)-inverter ring oscillators with the shortest gate length of 0.17 μm were fabricated by a conventional large-scale integrated (LSI) technology. The propagation delays were 21 ps / stage (2.0 V) at room temperature and 17 ps / stage (2.0 V) at 80 K. These results are the fastest records reported for bulk CMOS devices as of today. The results were obtained by reducing effective drain junction capacitances with “double-finger gates,” and devices will probably be faster if the areas are completely proportionally reduced to the feature size. Though it is important for CMOS devices to increase drain currents, a silicidation technique for source and drain was not necessary for the tested devices to reduce series resistance     

n+-polysilicon gate PMOSFET's with indium dopedburied-channels

In this letter a n⁺-polysilicon gate PMOSFET with indium doped buried-channel is discussed, The gate length scaling of n ⁺-polysilicon gate buried-length PMOSFET's is limited by the channel punch-through effect. Designing shallow counter-doped layers (buried-channels) has been established as a means to reduce the undesirable short channel effects in these devices. Indium, an acceptor dopant in Si, has a low diffusion coefficient and implant statistics favorable for achieving shallow doping layers. Indium implants are explored (as an alternative to BF₂) to counter dope the n-tub for adjusting the threshold voltage. Devices are fabricated using AT&T's 0.5 μm CMOS technology but with t_ox=50 Å. Although no special effort has been made to optimize the n-tub or to take full advantage of the diffusion and implant characteristics of indium, excellent electrical results are obtained for devices with L_eff=0.25 μm. Improved V_th roll-off characteristics and reduced body effect (γ≈0.18 V^½ versus γ_B≈0.40 V^½) in indium implanted buried channels are demonstrated over BF₂ implanted buried channels for PMOSFET's with identical long channel threshold voltages. The effects of incomplete ionization (freeze-out) of the indium acceptor states on the electrical device characteristics are demonstrated by device simulations and measurements