A methodology for deep sub-0.25 μm CMOS technology prediction

We present a novel methodology for characterization of sub-quartermicron CMOS technologies. It involves process calibration, device calibration employing two-dimensional device simulation and automated Technology Computer Aided Design (TCAD) optimization and, finally, transient mixed-mode device/circuit simulation. The proposed methodology was tested on 0.25 μm technology and applied to 0.13 μm technology in order to estimate ring oscillator speed. The simulation results show an excellent agreement with available experimental data     

Fully integrated 0.25 μm CMOS VCSEL driver with current peaking

A vertical-cavity-surface-emitting laser (VCSEL) driver chip based on a novel circuit concept for current peaking has been designed and fabricated in a 0.25 μm complementary metal-oxide-semiconductor (CMOS) process. This concept allows the easy integration of a peaking driving scheme in CMOS. Experimental results show speed extension from 500 Mbit/s for current on-off to 3.9 Gbit/s for current peaking driving     

BiCMOS technology with 60 GHz n-p-n bipolar and 0.25 μm CMOS

A BiCMOS technology has been developed that integrates a high-performance self-aligned double-polysilicon bipolar device into an advanced 0.25 μm CMOS process. The process sequence has been tailored to allow maximum flexibility in the bipolar device design without perturbation of the CMOS device parameters. Thus, n-p-n cutoff frequencies as high as 60 GHz were achieved while maintaining a CMOS ring oscillator delay per stage of about 54 ps at 2.5 V supply comparable to the performance in the CMOs-only technology. BiCMOS and BiNMOS circuits were also fabricated. BiNMOS circuits exhibited ≈45% delay improvement compared to CMOS-only circuits under high load conditions at 2.5 V     

High performance sub-0.25 μm devices using ultrathinoxide-nitride-oxide gate dielectric formed with low pressure oxidationand chemical vapor deposition

An ultra-thin, high reliability oxide-nitride-oxide (ONO) gate dielectric was formed using low pressure oxidation and chemical vapor deposition. A sub-0.25 μm device with high performance was fabricated for which the gate dielectric reliability was studied using both Fowler-Nordheim tunneling stress and hot carrier aging. The results from both techniques demonstrate that the device lifetime is longer than 100 years. Auger spectroscopy shows that there is about 9 at.% nitrogen at the SiO₂/Si interface. However, no transconductance degradation is observed     

A low-voltage CMOS complementary active pixel sensor (CAPS)fabricated using a 0.25 μm CMOS technology

A low voltage rail-to-rail CMOS complementary active pixel sensor (CAPS) architecture is presented. Compared with a conventional active pixel sensor (APS), the CAPS surpasses the bottleneck of limited output swing at ultra-low supply voltage operation imposed by highly scaled technology, making it more scalable compared with other reported architectures. The CAPS has been implemented with a commercially available 0.25 μm CMOS technology. The pixel size of the fabricated CAPS is 12 μm × 10 μm with a fill factor of 30%. It is verified that the CAPS is capable to operate at a V_DD below 1 V with a reasonable output swing     

Microwave performance of 0.25-µm gate length high electron mobility transistors

The performance of 0.25-µm gate length high electron mobility transistors (HEMT's) is reported. Devices were fabricated on layers grown by MBE. One of the heterostructures had no undoped AlGaAS spacer layer (wafer A), whereas the other had a 40-Å spacer layer (wafer B). The maximum stable gain on both wafers was ∼ 12 dB at 18 GHz. The minimum noise figure measured was 0.60 dB at 8 GHz and 1.3 dB at 18 GHz. Wafer A yielded devices with a unity current gain cutoff frequency ftof 65 GHz whereas wafer B gave an ftof 70 GHz. These results can be attributed primarily to the high quality material, low parasitic resistance, and short gate length.     

1.5 μm CMOS gate arrays with analog/digital macros designedusing common base arrays

Mixed analog and digital circuits are realized on a 1.5 μm silicon-gate CMOS chip with +5 V power supply only. The circuit uses CMOS digital gate arrays of 0.32 K to 19.6 K cells and is created without any additional turnaround time or any restriction on the design. Typical internal digital gate (two-input NAND) speed, with a fanout of 3 and a wire length of 3 mm, is 1.4 ns. A voltage comparator with ±8 mV maximum input offset voltage and 60 ns response time, digital-to-analog and analog-to-digital converters with 4-, 6-, and 8-bit resolution, respectively, and an analog switch of 25 Ω on-resistance can be realized on the same chip with digital circuits. Using this technology, about one-tenth of the turnaround time can be achieved compared with full-custom LSIs for the same system. The product development flow and computer-aided-design tools for designing mixed analog and digital gate arrays are the same as for digital gate arrays     

Embedded HIMOS(R) flash memory in 0.35 μm and 0.25 μm CMOStechnologies

In this paper, the performance and reliability characteristics of the 0.35 μm/0.25 μm High Injection MOS (HIMIOS(R)) technology is described in detail. This flash EEPROM technology relies on source-side injection for programming and Fowler-Nordheim tunneling for erasing, and has been successfully implemented in a 1 Mbit memory array embedded in a 0.35 μm CMOS technology, adding only about 30% to the processing cost of digital CMOS. Due to its triple gate structure, the HIMOS(R) cell exhibits a high degree of flexibility and scalability. A fast programming operation (10 μs) at 3.3 V supply voltage is combined with an endurance of well over 100000 program/erase cycles, immunity to all possible disturb effects and a retention time that largely exceeds 100 years at 125°C. Furthermore, the cell has been scaled to a 0.25 μm version, which is a laterally scaled version with the same operating voltages and tunnel oxide thickness. The use of secondary impact ionization is investigated as well and proves to be very promising for future generations when the supply voltage is scaled below 2.5 V     

Positive oxide-charge generation during 0.25 μm PMOSFEThot-carrier degradation

A new hot-carrier degradation mechanism becomes important in 0.25 μm PMOSFET's. Hot-hole injection generates positive oxide charge near the drain. We determine the time dependence and the oxide-thickness dependence and we show a considerable enhancement of this degradation mechanism for nitrided gate oxides. For many bias conditions and many geometries, the time dependence of PMOSFET degradation can be successfully described by a summation of the time dependences of three separate degradation mechanisms: generation of interface states, negative oxide charge and positive oxide charge     

Impact of pad and gate parasitics on small-signal and noisemodeling of 0.35 μm gate length MOS transistors

Microwave noise performance of p and n-type MOSFETs fabricated on the. same wafer was investigated in order to study the effect of the pad and gate parasitic circuit elements on noise performance. At low drain currents, the gate parasitic circuit was involved in the modeling to explain the observed kinks and loops in the s-parameters. Simulation of the noise parameters for p and n-type devices, measured in the 2-26 GHz frequency range, was performed by using extracted small-signal models of the transistor in connection with parasitic pad and gate circuits. Under the bias far from the optimal one, the additional parasitic inductance in the gate circuit was found responsible for the degradation of the noise performance by exhibiting peaks in the noise parameters     

Scaling of poly-encapsulated LOCOS for 0.35 μm CMOS technology

We demonstrate the scaling of Poly-Encapsulated LOCOS (PELOX) for 0.35 μm CMOS technology without detrimental effects on gate oxide and shallow source/drain junction integrity. As-grown bird's beak punchthrough is shown to fundamentally limit the scalability of LOCOS-based schemes for narrow nitride features. A quantitative comparison of bird's beak punchthrough is made between LOCOS, Poly-Buffer LOCOS (PBL), and PELOX. The PELOX scalability is emphasized by evaluating the impact of the polysilicon-sealed cavity length for narrow nitride features. We present the realization of a 1 μm active/isolation pitch fully meeting the geometry and off-leakage requirements of 0.35 μm CMOS technologies (VDS⩽5 V). This field-implant-free isolation module avoids unnecessary process complexity by successfully integrating scaled PELOX with the split well-drive-in scheme. A highlight of this new approach is that the NMOSFET characteristics are largely width-independent down to 0.3 μm dimensions     

0.25-μm gate millimeter-wave ion-implanted GaAs MESFETs

Quarter-micrometer gated ion-implanted GaAs MESFETs which demonstrate device performance comparable to AlGaAs/InGaAs pseudomorphic HEMTs (high-electron mobility transistors) have been successfully fabricated on 3-in-diameter GaAs substrates. The MESFETs show a peak extrinsic transconductance of 480 mS/mm with a high channel current of 720 mA/mm. From S-parameter measurements, the MESFETs show a peak current-gain cutoff frequency f_t of 68 GHz with an average f_t of 62 GHz across the wafer. The 0.25-μm gate MESFETs also exhibit a maximum-available-gain cutoff frequency f_t greater than 100 GHz. These results are the first demonstration of potential volume production of high-performance ion-implanted MESFETs for millimeter-wave application     

High performance damascene metal gate MOSFETs for 0.1 μm regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (~1000°C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450°C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO₂ or Ta₂O₅ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance     

Metallized ultra-shallow-junction device technology for sub-0.1μm gate MOSFET's

This paper describes a new ultra-thin SOI-CMOS structure offering reduced parasitic diffusion-layer resistance. It addresses ways to deal with the ultra-shallow junctions required by sub-0.1 μm MOSFET's. Based on a CVD tungsten process we experimentally investigate the characteristics of selectively grown tungsten used in the source and drain region made in SOI layers of various thicknesses ranging from 10 to 100 nm. We also investigate certain CMOS device characteristics. The SOI-CMOS structure, with low parasitic diffusion-layer resistance and good contact characteristics for ultra-shallow junction devices exhibits superior device performance and high scalability     

350 MHz opamp-RC filter in 0.18 μm CMOS

A 350 MHz fifth-order elliptic opamp-RC filter demonstrates that opamp-based filters need not have bandwidth disadvantages compared to transconductor-based filters. The filter, fabricated in standard digital 0.18 μm CMOS with 1.8 V V_DD, achieves 0.5 Vp-p signal swing at -40 dB THD     

A room temperature 0.1 μm CMOS on SOI

An advanced 0.1 μm CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 μm) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 μm were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 Å effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C_L=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained     

DC and RF performance of 0.25 μm p-type SiGe MODFET

The DC and RF performance of a 0.25 μm gate-length p-type SiGe modulation-doped field-effect transistor (MODFET) is reported. The hole channel consists of compressively strained Si_0.3Ge_0.7 layer grown on a relaxed Si_0.7Ge_0.3 buffer on a Si substrate. The combination of high-hole mobility, low-gate leakage current, and improved ohmic contact metallization results in an enhancement of the DC and RF performance. A maximum extrinsic transconductance (g(m_ext)) of 230 mS/mm was measured. A unity current gain cut-off frequency (fT) of 24 GHz and a maximum frequency of oscillation (f_max) of 37 GHz were obtained for these devices     

Characterization of polysilicon resistors in sub-0.25 μm CMOSULSI applications

The characteristics of polysilicon resistors in sub-0.25 μm CMOS ULSI applications have been studied. Based on the presented sub-0.25 μm CMOS borderless contact, both n⁺ and p⁺ polysilicon resistors with Ti- and Co-salicide self-aligned process are used at the ends of each resistor. A simple and useful model is proposed to analyze and calculate the essential parameters of polysilicon resistors including electrical delta W(ΔW), interface resistance R_interface, and pure sheet resistance R_pure . This approach can substantially help engineers in designing and fabricating the precise polysilicon resistors in sub-0.25 μm CMOS technology     

An analytical model for self-limiting behavior of hot-carrierdegradation in 0.25 μm n-MOSFET's

Hot-carrier degradation of short-channel n-MOSFETs becomes saturated after reaching a certain threshold value. The physical mechanism for this self-limiting behavior is investigated. It is proposed that the hot-carrier-induced oxide trapped charge and interface states form a potential barrier that repels subsequent hot carriers from causing further damage and can lead to the saturation of device degradation. A physical model is developed on the basis of the analysis. The model is verified by experimental results and can be used for more accurate device reliability projection     

Electrical properties of Si p+-n junctions for sub-0.25μm CMOS fabricated by Ga FIB implantation

p⁺-n junction diodes for sub-0.25-μm CMOS circuits were fabricated using focused ion beam (FIB) Ga implantation into n-Si (100) substrates with background doping of N_b=(5-10)×10 ¹⁵ and N_b⁺=(1-10)×10¹⁷ cm^-3. Implant energy was varied from 2 to 50 keV at doses ranging from 1×10¹³ to 1×10¹⁵ cm^-2 with different scan speeds. Rapid thermal annealing (RTA) was performed at either 600 °C or 700°C for 30 s. Diodes fabricated on N_b⁺ with 10-keV Ga⁺ exhibited a leakage current (^I_R) 100× smaller than those fabricated with 50-keV Ga⁺. Tunneling was determined to be the major current transport mechanism for the diodes fabricated on N_b⁺ substrates. An optimal condition for I_R on N_b⁺ substrates was obtained at 15 keV/1×10¹⁵ cm^-2. Diodes annealed at 600°C were found to have an I_R 1000× smaller than those annealed at 700°C. I-V characteristics of diodes fabricated on N_b substrates with low-energy Ga⁺ showed no implant energy dependence. I-V characteristics were also measured as a function of temperature from 25 to 200°C. For diodes implanted with 15-keV Ga ⁺, the cross-over temperatures between I_diff and I_g-r occurred at 106°C for N_b ⁺ and at 91°C for N_b substrates