Improving the performance of the organic thin-film transistors with thin insulating lithium fluoride buffer layer

The pentacene-based organic thin-film transistors (OTFTs) with a thin insulating lithium fluoride (LiF) buffer layer between the pentacene and source/drain electrodes were fabricated. Compared with conventional OTFTs, the introduction of the buffer layer (1 nm) leads to field-effect mobility increases from 0.16 to 0.5 cm²/Vs, and threshold voltage downshifts from −19 to −8 V for the linear region. The on/off current ratio is improved to a level of 10⁵ for the off-state current decreasing. These improvements are attributed to (i) tunneling injection through the LiF layer and (ii) interface dipole energy barrier decreasing and contact resistance reduction between pentacene and Au. The results demonstrate that it is an effective method to improve the device characteristics by using a buffer layer.     

Morphology transformations of pentacene on an UV-patternable polymer insulator and their effect on performance of flexible organic thin-film transistors

This work presents a low temperature with high resolution capability UV-patternable polymer, i.e. mr-UVCur06, for use as a gate insulator in OTFTs, by investigating the morphology transformation of pentacene deposited on the mr-UVCur06. The device structure is polyethylene terephthalate (PET)/indium-tin oxide (ITO)/mr-UVCur06/pentacene/Au (source/drain). In addition to its solution-processable capability, mr-UVCur06 is directly patterned by UV light in a low-temperature process. UV/ozone post-treatment of the patternable mr-UVCur06 can illuminate organic contaminants from its surface and increases surface energy. Experimental results indicate that a high surface energy existing at the mr-UVCur06 surface has produced in a larger ratio of I_{thin film phase}/I_{triclinic bulk phase} in pentacene. Then, the distance of pentacene molecular crystal structure, which is arranged in the thin film phase, is shorter than that in triclinic bulk phase. The performance of pentacene-based OTFTs can be enhanced with few contaminants and a high surface energy on the UV-patternable gate insulator. By performing UV/ozone post-treatment on the mr-UVCur06 insulator surface for 60 s, the OTFTs demonstrate a mobility, on/off drain current ratio, and V_T of 0.34 cm²/V s, 5.5 × 10⁴, and 2.5 V, respectively. Furthermore, the low-temperature photopatternable polymer dielectric paves the way for a relatively easy and low-cost fabrication of an OTFT array without expensive and complicated photolithography and dry etching.     

High-mobility pentacene phototransistor with nanostructured SiO2 gate dielectric synthesized by sol-gel method

We have fabricated a pentacene based phototransistor by employing a modified nanostructured SiO₂ gate dielectric. The photosensing properties of the pentacene thin film transistor fabricated on n-Si substrate with nanostructured SiO₂ as gate dielectric have been investigated. The photocurrent of the transistor increases with an increase in illumination intensity. This suggests that the pentacene thin film transistor behaves as a phototransistor with p-channel characteristics. The photosensitivity and responsivity values of the transistor are 630.4 and 0.10 A/W, respectively at the off state under AM 1.5 light illumination. The field effect mobility of the pentacene phototransistor was also found to be 2.96 cm²/Vs. The nanostructured surface of the gate possibly is the cause of the high-mobility value of the phototransistor due to light scattering from the increased surface area.     

Self-assembled monolayer modification of silver source-drain electrodes for high-performance pentacene organic field-effect transistors

We demonstrated excellent performance improvement of bottom-contact pentacene-based organic thin film transistors (OTFTs) fabricated at room-temperature with silver electrodes modified by self-assembled monolayers (SAMs) of binary mixtures of n-alkanethiol (n-decanethiol, HDT) and the fluorinated analog (3,3,4,4,5,5,6,6,7,7,8,8,9,9,10,10,10-heptadecafluoro-1-decanethiol, FDT). The OTFTs with modified silver (Ag) electrodes exhibit carrier mobility of 0.21 cm²/V s, which is faster than most of bottom-contact pentacene-based OTFTs fabricated at room-temperature with gold (Au) electrodes. The threshold voltage is reduced from −30 V of the devices with Au electrodes to −5.4 V of the devices with modified Ag electrodes. The hole injection barrier is also reduced with modified Ag as indicated by ultraviolet photoemission spectroscopy. The enhancement of the saturation current and the mobility of the devices are due to both the reduction of hole injection barriers and the continuous grain size of pentacene on top of electrodes and dielectrics.     

Printable Ferroelectric PVDF/PMMA Blend Films with Ultralow Roughness for Low Voltage Non‐Volatile Polymer Memory

Here, a facile route to fabricate thin ferroelectric poly(vinylidene fluoride) (PVDF)/poly(methylmethacrylate) (PMMA) blend films with very low surface roughness based on spin‐coating and subsequent melt‐quenching is described. Amorphous PMMA in a blend film effectively retards the rapid crystallization of PVDF upon quenching, giving rise to a thin and flat ferroelectric film with nanometer scale β‐type PVDF crystals. The still, flat interfaces of the blend film with metal electrode and/or an organic semi‐conducting channel layer enable fabrication of a highly reliable ferroelectric capacitor and transistor memory unit operating at voltages as low as 15 V. For instance, with a TIPS‐pentacene single crystal as an active semi‐conducting layer, a flexible ferroelectric field effect transistor shows a clockwise I–V hysteresis with a drain current bistability of 10³ and data retention time of more than 15 h at ±15 V gate voltage. Furthermore, the robust interfacial homogeneity of the ferroelectric film is highly beneficial for transfer printing in which arrays of metal/ferroelectric/metal micro‐capacitors are developed over a large area with well defined edge sharpness.     

High-performance thin-film transistor with 6,13-bis(triisopropylsilylethynyl) pentacene by inkjet printing

We have studied the performance improvement of organic thin-film transistor (OTFT) with a solution based TIPS pentacene (6,13-bis(triisopropylsilylethynyl)pentacene) by inkjet printing. The TIPS pentacene with 1.0 wt.% solution in 1,2-dichlorobenzene was used for printing of an active layer of OTFT. The OTFT printed at room temperature shows a shoulder-like behavior but it disappears for the OTFT printed at the substrate temperature of 60 °C. The OTFT on plastic exhibited an on/off current ratio of ∼10⁷, a threshold voltage of −2.0 V, a gate voltage swing of 0.6 V/decade and a field-effect mobility of 0.24 cm²/Vs in the saturation region.     

Influence of passivation with non-charged fluorinated ethylene propylene on the properties of pentacene organic thin film transistor

High electronegativity of non-charged fluorinated ethylene propylene (FEP) affected the performance of pentacene organic thin film transistors (OTFTs). The threshold voltage of the OTFT shifted from −14.7 V to −12.5 V without deterioration of on–off ratio and charge mobility. The degree of shift was related to the coverage of the FEP film on an active layer. No further shift was observed upon reaching the full coverage of surface at a 3-nm thickness of FEP. Encapsulation of the FEP-covered pentacene OTFT in a multilayer of PMMA/PUA/PET protected the device from oxygen and moisture.     

基于插入WO3缓冲层并五苯有机场效应晶体管性能的研究

The pentacene-based organic field effect transistor （OFET） with a thin transition metal oxide （WO3） layer between pentacene and metal （AI） source/drain electrodes was fabricated. Compared with conventional OFET with only metal AI source/drain electrodes, the introduction of the WO3 buffer layer leads to the device performance enhancement. The effective field-effect mobility and threshold voltage are improved to 1.90 em2/（V.s） and 13 V, respectively. The performance improvements are attributed to the decrease of the interface energy barrier and the contact resistance. The results indicate that it is an effective approach to improve the OFET performance by using a WO3 buffer layer.     

Enhanced electrical and photosensing properties of pentacene organic thin-film phototransistors by modifying the gate dielectric thickness

The effects of dielectric layer thickness on the electrical performance and photosensing properties of organic pentacene thin-film transistors have been investigated. To improve the electrical performance of pentacene thin-film transistors (TFTs), the poly-4-vinylphenol (PVP) polymer with various thicknesses was used in fabrication of the pentacene transistors. The pentacene thin-film transistor with the PVP dielectric layer of 70 nm exhibited a field-effect mobility of 4.46 cm²/Vs in the saturation region, a threshold voltage of −4.0 V, a gate voltage swing of 2.1 V/decade and an on/off current ratio of 5.1 × 10⁴. In the OFF-state, the photoresponse of the transistors increases linearly with illumination intensity. The pentacene transistor with the thinner dielectric layer thickness indicates the best photosensing behavior. It is evaluated that the electrical performance and photosensing properties of pentacene thin-film transistors can be improved by using various thickness dielectric layer.     

Memory effects in hybrid silicon-metallic nanoparticle-organic thin film structures

We report on the electrical behaviour of metal–insulator–semiconductor (MIS) structures fabricated on silicon substrates and using organic thin films as the dielectric layers. These insulating thin films were produced by different methods, including spin-coating (polymethylmethacrylate), thermal evaporation (pentacene) and Langmuir–Blodgett deposition (cadmium arachidate). Gold nanoparticles, deposited at room temperature by chemical self-assembly, were used as charge storage elements. In all cases, the MIS devices containing the nanoparticles exhibited hysteresis in their capacitance versus voltage characteristics, with a memory window depending on the range of the voltage sweep. This hysteresis was attributed to the charging and discharging of the nanoparticles from the gate electrode. A maximum memory window of 2.5 V was achieved by scanning the applied voltage of an Al/pentacene/Au nanoparticle/SiO₂/p-Si structure between 9 and −9 V.     

Natural polyelectrolyte: Major ampullate spider silk for electrolyte organic field-effect transistors

The major ampullate (MA) silk collected from giant wood spiders Nephila pilipes consists of 12% glutamic acid (Glu) and 4% tyrosine (Tyr) acidic amino residues. The MA silk may act as a natural polyelectrolyte for organic field-effect transistors (OFETs). Pentacene and F₁₆CuPc OFETs were fabricated with the MA silk thin film as the gate dielectric. The MA silk thin film with surface roughness of 4 nm and surface energy of 36.1 mJ/m² was formed on glass using a hexafluoroisopropanol (HFIP) organic process. The MA silk gate dielectric in pentacene OFETs may improve the field-effect mobility (μ_FE,sat) value in the saturation regime from 0.11 in vacuum to 4.3 cm² V⁻¹ s⁻¹ in air ambient at ca. 70% RH. The corresponding threshold voltage (V_TH) value reduced from −6 V in vacuum to −0.5 V in air ambient. Similar to other polyelectrolytes, the changes of μ_FE,sat and V_TH may be explained by the generation of electric double layers (EDLs) in the MA silk thin film in air ambient due to water absorption.     

Low voltage copper phthalocyanine organic thin film transistors with a polymer layer as the gate insulator

Low voltage organic thin film transistors(OTFTs) were created using polymethyl-methacrylate-co g-lyciclyl-methacrylate(PMMA-GMA) as the gate dielectric.The OTFTs performed acceptably at supply voltages of about 10 V.From a densely packed copolymer brush,a leakage current as low as 2×10~(-8) A/cm~2 was obtained.From the measured capacitance-insulator frequency characteristics,a dielectric constant in the range 3.9-5.0 was obtained. By controlling the thickness of the gate dielectric,the threshold voltage ...     

Effects of grain boundaries, field-dependent mobility, and interface trap States on the electrical Characteristics of pentacene TFT

We have fabricated pentacene-based thin film transistors and analyzed their electrical properties with the help of two-dimensional drift-diffusion simulations which favorably compare with the experimental results. We have set up a model considering the polycrystalline nature of pentacene and the presence of grains and grain boundaries. We show how this model can be applied to different devices with different grain sizes and we analyze the relationship between mobility, grain size and applied gate voltage. On the basis of the simulation results, we can introduce an effective carrier mobility, which accounts for grain-related effects. The comparison between experimental results and simulations allows us to clearly understand the differences in the mobility derived by the analysis of current-voltage curve (as done experimentally by using standard MOSFET theory) and the intrinsic mobility of the organic layer. The effect of the pentacene/oxide interface traps and fixed surface charges has also been considered. The dependence of the threshold voltage on the density and energy level of the trap states has been outlined.     

Pentacene organic thin-film transistors with solution-based gelatin dielectric

Gelatin is a natural protein in the field of food, pharmaceutical and tissue engineering, which works very well as the gate dielectric for pentacene organic thin-film transistors (OTFTs). An aqueous solution process has been applied to form a gelatin thin film on poly(ethylene terephthalate) (PET) or glass by spin-coating and subsequent casting. The device performance of pentacene OTFTs depend on the bloom number (molecular weight) of gelatin. The pentacene OTFT with 300 bloom gelatin as the gate dielectric in air ambient exhibits the best performance with an average field-effect mobility (μ_FE) value of ca. 16 cm² V^?1 s^?1 in the saturation regime and a low threshold voltage of ?1 V. The high performance of the pentacene OTFT in air ambient is attributed to the water resided in gelatin. The crystal quality of pentacene is not the key factor for the high performance.     

Non‐volatile Ferroelectric Poly(vinylidene fluoride‐co‐trifluoroethylene) Memory Based on a Single‐Crystalline Tri‐isopropylsilylethynyl Pentacene Field‐Effect Transistor

A new type of nonvolatile ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) (P(VDF‐TrFE)) memory based on an organic thin‐film transistor (OTFT) with a single crystal of tri‐isopropylsilylethynyl pentacene (TIPS‐PEN) as the active layer is developed. A bottom‐gate OTFT is fabricated with a thin P(VDF‐TrFE) film gate insulator on which a one‐dimensional ribbon‐type TIPS‐PEN single crystal, grown via a solvent‐exchange method, is positioned between the Au source and drain electrodes. Post‐thermal treatment optimizes the interface between the flat, single‐crystalline ab plane of TIPS‐PEN and the polycrystalline P(VDF‐TrFE) surface with characteristic needle‐like crystalline lamellae. As a consequence, the memory device exhibits a substantially stable source–drain current modulation with an ON/OFF ratio hysteresis greater than 10³, which is superior to a ferroelectric P(VDF‐TrFE) OTFT that has a vacuum‐evaporated pentacene layer. Data retention longer than 5 × 10⁴ s is additionally achieved in ambient conditions by incorporating an interlayer between the gate electrode and P(VDF‐TrFE) thin film. The device is environmentally stable for more than 40 days without additional passivation. The deposition of a seed solution of TIPS‐PEN on the chemically micropatterned surface allows fabrication arrays of TIPS‐PEN single crystals that can be potentially useful for integrated arrays of ferroelectric polymeric TFT memory.     

Effect of rapid thermal annealing on pentacene-based thin-film transistors

The bottom contact pentacene-based thin-film transistor is fabricated, and it is treated by rapid thermal annealing (RTA) with the annealed temperature up to 240 °C for 2 min in the vacuum of 1.3 × 10⁻² torr. The morphology and structure for the pentacene films of OTFTs were examined by scanning electron microscopy and X-ray diffraction technique. The thin-film phase and a very small fraction of single-crystal phase were found in the as-deposited pentacene films. While the annealing temperature increases to 60 °C, the pentacene molecular ordering was significantly improved though the grain size only slightly increased. The device annealed at temperature of 120 °C has optimal electrical properties, being consistent with the experimental results of XRD. The post-annealing treatment results in the enhancement of field-effect mobility in pentacene-based thin-film transistors. The field-effect mobility increases from 0.243 cm²/V s to 0.62 cm²/V s. Besides, the threshold voltage of device shifts from −7 V to −3.88 V and the on/off current ratio increases from 4.0 × 10³ to 8.7 × 10³.     

Improved pentacene device characteristics with sol–gel SiO2 dielectric films

The interfacial interactions between semiconductors and gate dielectrics have a profound influence on the device characteristics of field effect transistors (FETs). This paper reports on the concept of introducing a sol–gel SiO₂ as inorganic capping layer to significantly improve device characteristics of pentacene-based FETs. The smoother film surfaces of sol–gel SiO₂ (1.9 Å root-mean-square) induced larger pentacene grain sizes, and led to hole mobilities of 1.43 cm²/Vs, on–off ratio of 10⁷, and a subthreshold swing of 102 mV/decade when operating at −20 V.     

Versatile threshold voltage control of OTFTs via discontinuous pn-heterojunction formation

We demonstrate the versatility of the threshold voltage control for organic thin-film transistors (OTFTs) based on formation of discontinuous pn-heterojunction on the active channel layer. By depositing n-type dioctyl perylene tetracarboxylic diimide molecules discontinuously onto base p-type pentacene thin films (the formation of the discontinuous pn-heterojunction), a positive shift of the threshold voltage was attained which enabled realizing a depletion-mode transistor from an original enhancement-mode pristine pentacene transistor. Careful control of the threshold voltage based on this method led assembling a depletion-load inverter comprising a depletion-mode transistor and an enhancement-mode transistor connected in series that yielded tunable signal inversion voltage approaching 0 V. In addition, the tunability could be applied to improve the program/erase signal ratio for non-volatile transistor memories by more than 4 orders of magnitude compared to reference memory devices made of pristine pentacene transistors.     

Influence of 2-mercapto-5-nitrobenzimidazole treatment on the electronic characteristics of bottom-contact organic field-effect transistors

The treatment of the Au electrodes of an organic bottom-contact thin film transistor with 2-mercapto-5-nitrobenzimidazole (MNB) led to improved current–voltage characteristics. X-ray diffraction, atomic force microscopy, soft X-ray emission spectroscopy, and ultraviolet photoelectron spectroscopy were used to investigate the structure-function relationship in the device components MNB and pentacene. By treating the Au contacts with MNB prior to the pentacene deposition, the morphological and structural properties of the pentacene come to resemble the ideal case of pentacene deposited onto SiO₂. The action of the MNB is therefore to remove the transition region at the Au/pentacene interface, leading to improved charge carrier injection.     

Controllable Shifts in Threshold Voltage of Top‐Gate Polymer Field‐Effect Transistors for Applications in Organic Nano Floating Gate Memory

Organic field‐effect transistor (FET) memory is an emerging technology with the potential to realize light‐weight, low‐cost, flexible charge storage media. Here, solution‐processed poly[9,9‐dioctylfluorenyl‐2,7‐diyl]‐co‐(bithiophene)] (F8T2) nano floating gate memory (NFGM) with a top‐gate/bottom‐contact device configuration is reported. A reversible shift in the threshold voltage (V_Th) and reliable memory characteristics was achieved by the incorporation of thin Au nanoparticles (NPs) as charge storage sites for negative charges (electrons) at the interface between polystyrene and cross‐linked poly(4‐vinylphenol). The F8T2 NFGM showed relatively high field‐effect mobility (µ_FET) (0.02 cm² V^?1 s^?1) for an amorphous semiconducting polymer with a large memory window (ca. 30 V), a high on/off ratio (more than 10⁴) during writing and erasing with an operation voltage of 80 V of gate bias in a relatively short timescale (less than 1 s), and a retention time of a few hours. This top‐gated polymer NFGM could be used as an organic transistor memory element for organic flash memory.