一种疲劳驾驶检测系统中快速人眼检测方法

疲劳驾驶是导致交通事故的主要原因之一,因此,以人眼检测为核心的疲劳驾驶检测受到了普遍地关注。目前传统的疲劳驾驶检测方法采用"人脸-人眼"模型,即先定位人脸,随后再进行人眼检测。在Ada Boost算法的基础上,使用变模板匹配方法进行人眼检测,并改进了"人脸-人眼模型",采用多特征的分类器来有选择的跳过人脸检测步骤,从而快速准确地定位人眼。在DM642芯片上进行实验,人眼识别率达到了90%以上,且平均每秒能处理40帧图片,证明了该方法的高效性和实用性。     

便携式LCD显示系统的多线寻址驱动电路

介绍STN LCD多线寻址驱动方式的优点，及使用多线寻址驱动电路时的要求。     

一种车载疲劳驾驶监测仪

针对目前私驾车的不断增加，对于安全驾驶的问题也越来越重视，除了自觉遵守交规以外，还要对日常驾驶过程中遇到的问题如疲劳驾驶进行监控和预警。以往只有高档车才有的功能如何用到中低挡车辆上，目前市面上有很多方案，在此介绍了一个低成本的设计方案，较好地实现车载疲劳驾驶监测。并介绍一种被动监测的方法来监测驾驶员的疲劳状态，通过采用一个低成本的手机模块组成的监测系统，实现对驾驶员眼睛状态的监控，以便确定驾驶员是否处于疲劳状态。同时通过声光报警提醒驾驶员，从而达到减少发生道路交通事故的目的。     

基于复杂驾驶环境下面部特征识别技术的防疲劳驾驶系统

本课题阐述基于面部特征识别技术的防疲劳驾驶系统研究、开发.通过后台管理系统进行大数据分析,研究驾驶员疲劳规律、预测驾驶员可能出现的疲劳,方便管理人员有针对性的重点关注"常疲劳"的驾驶员,实现精细化管理,尽早预防、尽量避免疲劳驾驶,为行车安全把好关.     

基于多感官协同疲劳驾驶预警方案的研究

疲劳驾驶已成为社会的一个绝症"毒瘤",严重威胁人们的生命和财产安全。以驾驶员为研究对象,结合交通心理学、车辆人机工程学相关理念,利用驾驶员听觉、触觉、嗅觉,设计一套三位一体多感官协同的预警方案。方案从微观出发,注重本体感受,结构简单、便捷,并充分利用车上的设备,经济性好,适合市场的推广。     

A novel ion imager for secondary ion mass spectrometry

An area detector for a secondary ion mass spectrometry (SIMS) ion microscope and its performance are described. The operational principle is based on detecting the change in potential of a floating photodiode caused by the ion-induced secondary-electron emission and the incoming ion itself. The experiments demonstrated that 10¹-10⁵ aluminum ions per pixel can be detected with good linear response. Moreover, relative ion sensitivities from hydrogen to lead were constant within a factor of 2. The performance of this area detector provides the potential for detection of kiloelectronvolt ion images with current ion microscopy     

A triaxial accelerometer and portable data processing unit for theassessment of daily physical activity

The present study describes the development of a triaxial accelerometer (TA) and a portable data processing unit for the assessment of daily physical activity. The TA is composed of three orthogonally mounted uniaxial piezoresistive accelerometers and can be used to register accelerations covering the amplitude and frequency ranges of human body acceleration. Interinstrument and test-retest experiments showed that the offset and the sensitivity of the TA were equal for each measurement direction and remained constant on two measurement days. Transverse sensitivity was significantly different for each measurement direction, but did not influence accelerometer output (<3% of the sensitivity along the main axis). The data unit enables the on-line processing of accelerometer output to a reliable estimator of physical activity over eight-day periods. Preliminary evaluation of the system in 13 male subjects during standardized activities in the laboratory demonstrated a significant relationship between accelerometer output and energy expenditure due to physical activity, the standard reference for physical activity (r=0.89). Shortcomings of the system are its low sensitivity to sedentary activities and the inability to register static exercise. The validity of the system for the assessment of normal daily physical activity and specific activities outside the laboratory should be studied in free-living subjects     

非均匀温度场下红外热成像仪温控系统设计

为降低外界环境温度和内部发热元件形成的非均匀温度场对红外热成像仪的成像性能影响。通过Proe和Ansys ICEPARK建立红外热成像仪的有限元模型,在红外镜头表面进行黑色阳极氧化、喷砂处理增强辐射换热,以及安装风扇增强对流换热保证高温环境时的散热,低温环境时采用热电阻进行温升设计,并仿真分析红外热成像仪在不同温度环境下整机内部温度分布和红外镜头温度分布情况,并利用在高低温箱的红外热成像仪来观察平行光管中的靶标图的成像质量,验证温控设计的高效性。结果表明:所采用温度控制电路板对风扇与热电阻能进行温度控制,当环境温度下降至0℃和升高至30℃时,启动温控系统使红外热成像仪光学系统温度正常,保证红外热成像仪的成像质量。     

一种基于局部熵的海背景红外目标检测算法

介绍了一种新的红外目标检测方法。在对图像中值滤波之后,用3×3的窗口计算图像局部熵,从而使由局部熵映射的灰度图像中的目标边缘更加清晰,在此基础上使用适应性更强的Canny算子进行边缘检测。实验证明,对于海面目标和海面背景的灰度对比度比较小的红外图像,此方法提高了检测概率。     

A photoelectric conversion-characteristic control method for interline transfer CCD imager

There are generally two approaches to dynamic range expansion for a solid-state imager. One is output-noise decrease. Another approach is a maximum signal-charge increase. An interline transfer CCD imager has an advantage in regard to low output noise, while its maximum amount of signal charges is lower than that for the other kinds of imagers, MOS, CPD, etc. Using a new operation mode, dynamic-range expansion for the interline transfer CCD imager has been achieved. There is a knee point in the photoelectric conversion characteristic.     

便携式脉冲调制型医用半导体激光器的驱动电源及光学透镜系统的设计

针对脉冲激光器穴位照射治疗的特点,对半导体激光二极管（LD）的驱动电路及光学镜头系统的设计进行了研究。本文设计了一款新型的锂电池供电便携式脉冲医用激光器,介绍了采用脉冲调制恒流驱动的原理以及采用透镜组和电路调整的方法改变激光照射功率密度的光学镜头的设计方法。该款脉冲激光器适用于激光体外穴位照射,对激光临床应用有一定的意义。     

A ferroelectric DRAM cell for high-density NVRAMs

The operation of a ferroelectric DRAM (dynamic random access memory) cell for nonvolatile RAM (NVRAM) applications is described. Because polarization reversal only occurs during nonvolatile store/recall operations and not during read/write operations, ferroelectric fatigue is not a serious endurance problem. For a 3-V power supply, the worst-case effective silicon dioxide thickness of the unoptimized lead zirconate titanate film studied is less than 17 Å. The resistivity and endurance properties of ferroelectric films can be optimized by modifying the composition of the film. This cell can be the basis of a very-high-density NVRAM with practically no read/write cycle limit and at least 10¹⁰ nonvolatile store/recall cycles     

A stacked-CMOS cell technology for high-density SRAM's

A stacked-CMOS SRAM cell technology for high-density SRAMs has been developed. It has been found that the increase of the on-current of the thin-film transistor (TFT) load leads not only to the increase of the cell noise margin, but also to the reduction of the cell area. The improvement of the electrical characteristics of the TFT load has been achieved by enlarging the grains of the polysilicon film through the use of a novel solid-phase growth technique. As a result, TFT loads with on/off current ratio of 10⁵ and off-current of 0.07 pA/μm, both promising for high-density SRAMs, have been obtained     

A flexible redundancy technique for high-density DRAMs

The limitations of conventional redundancy techniques are pointed out and a novel redundancy technique is proposed for high-density DRAMs using multidivided data-line structures. The proposed technique features a flexible relationship between spare lines and spare decoders, as well as lower probability of unsuccessful repair. With this technique the yield improvement factor of 64-Mb DRAMs and beyond is estimated to be more than twice that with the conventional technique in the early stages of production     

A generic multielement microsystem for portable wirelessapplications

An open-architecture microsystem that can be populated with a variety of sensors and actuators is described. The microsystem is designed for low-power wireless applications where small size and high sensor accuracy are important. It consists of an in-module microcontroller connected to multiple front-end transducers through an intramodule sensor bus. An external interface allows internally processed data to be output through either a hard-wired input/output port or a radio-frequency transmitter. The present microsystem is configured for environmental monitoring and measured temperature, barometric pressure, relative humidity, and acceleration/vibration. It occupies less than 10 cc, consumes an average of 530 μW from 6 V, and transmits data up to 50 m. System features such as active power management, the intramodule sensor bus, generic bus interface circuitry, and in-module sensor compensation based on bivariate polynomials are discussed     

Copper trace fatigue models for mechanical cycling, vibration and shock/drop of high-density PWAs

When assessing the mechanical durability of electronic assemblies, the focus is generally on the solder interconnects. However, in many package styles, such as ball grid arrays (BGAs), land grid arrays (LGAs), micro lead frame (MLFs) and quad flat no-lead (QFNs), the Cu trace emanating from the solder pad may be the weakest failure site, especially if the solder joint is copper-defined rather than mask defined. This is particularly true in situations with cyclic mechanical loading, such as cyclic quasi-static bending, vibration and repetitive drop/shock.This study focuses on quasi-static mechanical cycling durability of LGA assemblies with copper-defined pads. Specimens were cycled to failure under zero-to-max, three-point bending and failure statistics were collected. The failure mode was confirmed to be fatigue cracks in copper traces emanating from the corner solder pads, just at the edge of the solder mask where the solder joint ends. The cracks were identified by lateral polishing after desoldering the component.The cyclic bending of this assembly was modeled with 3D, elastic-plastic, large deformation finite element analysis. Due to the complexity of the geometry, a global-local approach was used to identify the strain history and the mean stress at the failure site.A generalized strain-based fatigue model was used to characterize these failures, and preliminary model constants were iteratively estimated by ensuring that they were simultaneously compatible with both the durability test data and the copper stress-strain curves used in the FEA (finite element analysis).These preliminary model constants were then refined by separately modeling the initiation and progression history of fatigue damage in the cyclic bend tests. Damage progression was modeled in this study by using a technique of ‘successive initiation’ developed earlier by this research group. In this method, finite element simulations are used to progressively ‘kill’ elements that have accumulated sufficient fatigue damage to lose their load-carrying capacity. When the killed elements span the entire cross-section of the copper trace, the trace is assumed to electrically fail.This calibrated model is then used to demonstrate its ability to predict copper trace failures in other situations such as quasi-static four-point bending of LGA assemblies and vibration of BGA assemblies. More important, we demonstrate its use for re-designing of BGA assemblies to prevent copper trace failures under drop/shock loading.The important impact of this study includes insight into copper trace failures in Printed Wiring Assemblies (PWAs) under mechanical cycling, a quantitative model to predict its occurrence, and validated guidelines to prevent it by design.     

A C-switch cell for low-voltage and high-density SRAMs

We propose a novel static random access memory (SRAM) cell named complementary-switch (C-switch) cell. The proposed SRAM cell features: (1) C-switch in which an n-channel bulk transistor and a p-channel TFT are combined in parallel; (2) single-bit-line architecture; (3) gate-all-around TFT (GAT) with large ON-current of μA order. With these three features, the proposed cell enjoys stability at 1.5 V and is 16% smaller in size than conventional cells. The C-switch cell is built with only a triple poly-Si and one metal process using 0.3 μm design rules     

A dynamic three-state memory cell for high-density associativeprocessors

A dynamic associative processor cell is described. The cell stores three states (0, 1, and X) and performs read, match, and masked-write functions. Five MOS transistors are used, including two overlapping dual-gate structures available in MIT's CCD/CMOS technology. Dual-gate CCD transistors are used to reduce the charge-spooning current, which can discharge the storage node through the write transistors. The use of the cell in an associative processor is described, and experimental results are presented     

A double-epitaxial process for high-density DRAM trench-capacitor isolation

A new double-epi structure for isolating deep (>5 µm) trench capacitors with 1 µm or less spacing is described. This technique consists of a thin lightly doped upper epilayer on top of a thicker and more heavily doped bottom layer of epi. The low resistivity bottom epilayer is designed to isolate trench capacitors of any depth. The upper layer with high resistivity is used for the CMOS periphery and can be selectively doped to achieve a near-uniform concentration to isolate trench capacitors in the core. Isolation between deep trenches at 1.0-µm spacing has been demonstrated to be applicable for 4 Mbit and greater DRAM integration levels.