Ultrathin gate oxide reliability: physical models, statistics, andcharacterization

The present understanding of wear-out and breakdown in ultrathin (t_ox < 5.0 nm) SiO₂ gate dielectric films and issues relating to reliability projection are reviewed in this article. Recent evidence supporting a voltage-driven model for defect generation and breakdown, where energetic tunneling electrons induce defect generation and breakdown will be discussed. The concept of a critical number of defects required to cause breakdown and percolation theory will be used to describe the observed statistical failure distributions for ultrathin gate dielectric breakdown. Recent observations of a voltage dependent voltage acceleration parameter and non-Arrhenius temperature dependence will be presented. The current understanding of soft breakdown will be discussed and proposed techniques for detecting breakdown presented. Finally, the implications of soft breakdown on circuit functionality and the applicability of applying current reliability characterization and analysis techniques to project the reliability of future alternative gate dielectrics will be discussed     

On the optimum thickness to test dielectric reliability, in an integrated technology of power devices

This paper deals with the extensive characterization of dielectric films with thicknesses from 20 to 65 nm. Thick dielectric reliability has been investigated with time dependent dielectric breakdown (TDDB). TDDB tests are conducted under constant current injection. Assuming that the logarithm of the median time-to-failure is described by a linear electric field dependence, a generalized empirical law for the long-term reliability of the dielectric is proposed. This law takes into account the applied electric field and the dielectric thickness. This reliability law is available for dielectric thicknesses greater than 10 nm. A procedure to test dielectrics of various thicknesses is given in order to predict their reliability in power integrated devices.     

Design of field-plate terminated 4H-SiC Schottky diodes using high-k dielectrics

Silicon carbide (SiC) field-plate terminated Schottky diodes using silicon dioxide (SiO₂) dielectric experience high electric field in the insulator and premature dielectric breakdown, attributed to the lower dielectric constant of the oxide. To alleviate this problem we explore the use of high-k dielectrics, silicon nitride (Si₃N₄) and sapphire (Al₂O₃), on 4H-SiC by numerical simulations using Medici. The simulation results show significant improvement in blocking voltages by as much as 30% and much lower electric field within the dielectrics. There is also a slight reduction in the specific-on resistance (R_sp-on) and a small increase in the forward current density due to the formation of an accumulation layer in SiC where the metal overlaps the dielectric. This effect is enhanced with increasing dielectric constant and decreasing dielectric thickness for a given dielectric.     

强电场作用下的固体电介质中电子填充陷阱动力学

本文阐述了用表面电位测量法研究固体电介质在强电场下电子填充陷阱的动力学特性。改进的一级捕获动力学方程定性地解释了陷阱填充过程以及电子填充陷阱稳态值随电场的变化而出现峰值的现象。由此分析指出在接近击穿的电场范围内,导带中的自由电子要与陷阱化电子发生碰撞电离,当这种碰撞电离退陷阱化达到一定程度时,介质便发生电击穿。     

Degradation of thin oxides during electrical stress

A bond-breaking phenomenon responsible for oxide degradation during electrical stress is considered as a multi-step process that includes generation of precursor breakdown defects by the injected electrons directly in the bulk oxide and the subsequent breakdown of the defect's bonds. Precursor defect generation is attributed to the capture/scattering of the injected electrons by the localized gap states associated with oxide structural imperfections. These precursor defects, represented by significantly elongated Si–O bonds or Si–Si bonds are shown to be unstable due to their vibrational excitation and polarization induced by temperature and an applied electric field, respectively; breakdown of the weak precursor defect's bonds results in the formation of the E^′ centers. The proposed model suggests that new precursor defects are preferentially created in the vicinity of the previously generated E^′ centers. This leads to the formation of defect clusters, which can grow and coalesce throughout the oxide, contributing to oxide leakage current and eventual oxide breakdown. The model describes the charge-to-breakdown dependence on the electron fluence and energy, electric field, temperature and oxide thickness.     

MIMC reliability and electrical behavior defined by a physical layer property of the dielectric

Metal–insulator–metal capacitor (MIMC) reliability and electrical properties are defined by the TDDB lifetime, breakdown voltage and leakage current. In this article, the correlation is determined between these electrical properties and the physical and chemical properties of the SiN dielectric layer. It is demonstrated how a SiN dielectrics with a high refractive index have high Si content and show an increased initial leakage current. However, contradictory to the high leakage current, these dielectrics also show high lifetimes. It is shown that SiN dielectrics with a high Si content contain high numbers of charge trapping centers. Over time, a high concentration of trapped charges is build up to such an extend that the local electric field over the dielectric is significantly decreased. This results in the observed reliability improvement of the dielectric. The final intrinsic quality and reliability of MIMC capacitors can therefore be determined by measurable physical properties of the MIMC dielectric at the time of the deposition of this layer.     

TDDB击穿特性评估薄介质层质量

与时间相关电介质击穿(TDDB)测量是评估厚度小于20nm薄栅介质层质量的重要方法.氧化层击穿前,隧穿电子和空穴在氧化层中或界面附近产生陷阱、界面态,当陷阱密度超过临界平均值 _bd时,发生击穿.击穿电量Q_bd值表征了介质层的质量.Q_bd值及其失效统计分布与测试电流密度、电场强度、温度及氧化层面积等有定量关系.TDDB的早期失效分布可以反映工艺引入的缺陷.TDDB可以直接评估氧化、氮化、清洗、刻蚀等工艺对厚度小于10nm的栅介质质量的影响.它是硅片级评估可靠性和预测EEPROM擦写次数的重要方法.     

Electrical characteristics of ferroelectric PZT thin films for DRAMapplications

Ferroelectric lead zirconate titanate (PZT) films with as much as 2.5 times the storage capacity of the best reported silicon oxide/nitride/oxide (ONO) stacked dielectrics have been fabricated. A 2000-Å film with an effective SiO₂ thickness of 10 Å is demonstrated. Because of the extremely high dielectric constant (ϵ_r≳>1000), even larger storage capacities can be obtained by scaling the ferroelectric film thickness, whereas the thickness of ONO films is limited by direct tunneling through the film. Electrical conduction in the PZT films studied is ohmic at electric fields below 250 kV/cm and follows an exponential field dependence at higher fields, which is shown to be consistent with a simple model for electronic hopping through the film. Leakage current as low as 9×10^-8 A/cm² at 2.5 V for a 4000-Å film is obtained with the addition of La and Fe to compensate for Pb and O vacancies in the film. Further improvement in both leakage current and time-dependent dielectric breakdown characteristics are necessary to ensure reliable DRAM operation     

Temperature effect on gate leakage currents in gate dielectric films of GaAs MOSFET

The gate dielectrics of Ga₂O₃(As₂O₃) of the GaAs MOSFET were prepared by a low-cost and low-temperature liquid-phase chemically enhanced oxidation method. The temperature and oxide thickness dependence of gate dielectric films on GaAs MOSFET have been investigated. The leakage current and dielectric breakdown field were both studied. Both gate leakage current density and breakdown electrical field were found to depend on the oxide thickness and operating temperature. The increasing trend in gate leakage current and the decreasing trend in breakdown electrical field were observed upon reducing oxide thickness from 30 to 12 nm and increasing operating temperature from −50°C to 200°C.     

Reliability and performance limitations in SiC power devices

Despite silicon carbide’s (SiC’s) high breakdown electric field, high thermal conductivity and wide bandgap, it faces certain reliability challenges when used to make conventional power device structures like power MOS-based devices, bipolar-mode diodes and thyristors, and Schottky contact-based devices operating at high temperatures. The performance and reliability issues unique to SiC discussed here include: (a) MOS channel conductance/gate dielectric reliability trade-off due to lower channel mobility as well as SiC–SiO₂ barrier lowering due to interface traps; (b) reduction in breakdown field and increased leakage current due to material defects; and (c) increased leakage current in SiC Schottky devices at high temperatures.Although a natural oxide is considered a significant advantage for realizing power MOSFETs and IGBTs in SiC, devices to date have suffered from poor inversion channel mobility. Furthermore, the high interface state density presently found in the SiC–SiO₂ system causes the barrier height between SiC and SiO₂ to be reduced, resulting in increased carrier injection in the oxide. A survey of alternative dielectrics shows that most suffer from an even smaller conduction band offset at the SiC–dielectric interface than the corresponding Silicon–dielectric interface and have a lower breakdown field strength than SiO₂. Thus, an attractive solution to reduce tunneling such as stacked dielectrics is required.In Schottky-based power devices, the reverse leakage currents are dominated by the Schottky barrier height, which is in the 0.7–1.2 eV range. Because the Schottky leakage current increases with temperature, the SiC Schottky devices have a reduction in performance at high temperature similar to that of Silcon PN junction-based devices, and they do not have the high temperature performance benefit associated with the wider bandgap of SiC.Defects in contemporary SiC wafers and epitaxial layers have also been shown to reduce critical breakdown electric field, result in higher leakage currents, and degrade the on-state performance of devices. These defects include micropipes, dislocations, grain boundaries and epitaxial defects. Optical observation of PN diodes undergoing on-state degradation shows a simultaneous formation of mobile and propagating crystal stacking faults. These faults nucleate at grain boundaries and permeate throughout the active area of the device, thus degrading device performance after extended operation.     

Ultrathin Supported Lipid Monolayer with Unprecedented Mechanical and Dielectric Properties

The development of ultrathin dielectrics for low power electronics operations, flexible and printed electronics, and field‐effect‐transistor‐based sensors is still a challenge. Here, monolayers of engineered lipids supported on silicon are reported presenting exceptional mechanical and dielectric properties. The lipid monolayers are stabilized using a simple procedure based on a two‐stage reticulation process in both their aliphatic chains and their head‐group. With a thickness lower than 3 nm, such layers are demonstrated to offer exceptional mechanical and dielectric stability with unprecedented low leakage current and dielectric strength. Surprisingly, the mechanical and dielectric pressures required to rupture/breakdown the monolayers are shown to be similar. These results suggest the presence of a strong correlation between mechanical and dielectric properties, as well as between the mechanisms of rupture and breakdown.     

Electric breakdowns and breakdown mechanisms in ultra-thin silicon oxides

It was found that the breakdown times measured using time-dependent-dielectric-breakdown (TDDB) distributions could be shifted to shorter times when the amount of energy available during the breakdown event was increased. The TDDB distributions were non-unique and breakdown models must account for both electrical breakdowns and dielectric breakdown. A novel approach for obtaining breakdown distributions will be presented. This approach uses a small number of oxides to obtain a time-dependent-electric-breakdown (TDEB) distribution, which will be shown to provide complementary information to that obtained from (TDDB) distributions. While the observation of dielectric breakdown in ultra-thin dielectrics may be difficult using standard test conditions, it will be shown that electric breakdowns are relatively easy to observe.     

Electron fluence driven,Cu catalyzed,interface breakdown mechanism for BEOL low-k time dependent dielectric breakdown

During technology development, the study of low-k time dependent dielectric breakdown (TDDB) is important for assuring robust chip reliability. It has been proposed that the fundamentals of low-k TDDB are closely correlated with the leakage conduction mechanism of low-k dielectrics. In addition, low-k breakdown could also be catalyzed by Cu migration occurring mostly at the interface between capping layer and low-k dielectrics. In this paper, we first discuss several important experimental results including leakage modulation by changing the capping layer without changing the electric field, TDDB modulation by Cu-free and liner-free interconnect builds, 3D on-flight stress-induced leakage current (SILC) measurement, and triangular voltage sweep (TVS) versus TDDB to confirm the proposed electron fluence driven, Cu catalyzed interface low-k breakdown model. Then we review several other low-k TDDB models that consider only intrinsic low-k breakdown, especially the impact damage model. Experimental attempts on validation of various dielectric reliability models are discussed. Finally, we propose that low-k breakdown seems to be controlled by a complicated competing breakdown process from both intrinsic electron fluence and extrinsic Cu migration during bias and temperature stress. It is hypothesized that the amount of Cu migration during TDDB stress strongly depends on process integration. The different roles of Cu in low-k breakdown could take different dominating effects at different voltages and temperatures. A great care must be taken in evaluating low-k dielectric TDDB as its ultimate breakdown kinetics could be strongly dependent on interconnect space, process, material, stress field, and stress temperature.     

Intra-level voltage ramping-up to dielectric breakdown failure on Cu/porous low-k interconnections in 45 nm ULSI generation

The degradation of reliability for intra-level voltage-breakdown in the 45 nm generation node has become an increasingly important issue with the introduction of porous low-k dielectrics. The dominant failure mechanism for lower voltage ramping-up to dielectric breakdown and higher leakage current was that more electrons easily transported through the percolation path in intra-level porous low-k interconnections damaged from HF corrosion. An optimal ultraviolet curing process and a less NH₃ plasma pre-treatment on porous low-k dielectrics before the SiCN capping layer are developed to improve performance in both of these cases. The stiff configuration of the reconstruction of Si-O network structures and less HF corrosion is expected to have high tolerance to electrical failure. As a result, the proposed model of this failure facilitates the understanding of the reliability issue for Cu/porous low-k interconnections in back-end of line (BEOL) beyond 45 nm nodes.     

Effects of radiation and charge trapping on the reliability of high-κ gate dielectrics

The radiation response and long term reliability of alternative gate dielectrics will play a critical role in determining the viability of these materials for use in future space applications. The total dose radiation responses of several near and long term alternative gate dielectrics to SiO₂ are discussed. Radiation results are presented for nitrided oxides, which show no change in interface trap density with dose and oxide trapped charge densities comparable to ultra thin thermal oxides. For aluminum oxide and hafnium oxide gate dielectric stacks, the density of oxide trapped charge is shown to depend strongly on the film thickness and processing conditions. The alternative gate dielectrics discussed here are shown to have effective trapping efficiencies that are up to 15 to 20 times larger than thermal SiO₂ of equivalent electrical thickness. A discussion of single event effects in devices and ICs is also provided. It is shown that some alternative gate dielectrics exhibit excellent tolerance to heavy ion induced gate dielectric breakdown. However, it is not yet known how irradiation with energetic particles will affect the long term reliability of MOS devices with high-κ gate dielectrics in a space environment.     

Field Acceleration Model for TDDB: Still a Valid Tool to Study the Reliability of Thick SiO2-Based Dielectric Layers?

The aim of this paper is to investigate the reliability of thick oxides that are dedicated to the power integrated device fabrication. The field dependence of defect-related time-dependent dielectric breakdown (TDDB) mode over a wide range of oxide thickness T_OX and electric field E, using multiple wafer fabrication lots, is investigated. TDDB tests are conducted under constant current injection using structures with different areas. For that, we have applied a new electric field model based on a 1/E model (reciprocal field dependence) that is proposed recently in the literature. We show that when the dielectric thickness increases, this electric field acceleration model gives an erroneous prediction of the long-term reliability. We conclude that it is too early to give a generalized law of dielectric to predict their reliability without taking into account the influence of thicknesses. Consequently, the 1/E model may therefore have to be revised.     

Prediction of dielectric reliability from I–V characteristics: Poole–Frenkel conduction mechanism leading to √E model for silicon nitride MIM capacitor

Two assumptions lead to a correlation between the leakage mechanism of a dielectric and dielectric reliability: the degradation of the dielectric is a direct cause of the leakage current flowing through the dielectric and breakdown occurs after a critical charge has been forced through the dielectric. The field and temperature dependence of the leakage current mechanism then determine the voltage acceleration factor and the activation energy of TDDB experiments. This simple physical model describes the reliability of metal insulator metal (MIM) capacitors with PECVD SiN remarkably well. The current conduction mechanism is described by Poole–Frenkel theory, leading to a √E dependence of the time to breakdown on the applied electric field. The model predicts correctly the voltage acceleration factor and its temperature dependence and the activation energy.     

Time-Dependent Dielectric Breakdown of 4H-SiC MOS Capacitors and DMOSFETs

Time-dependent dielectric breakdown measurements were performed at 200 $^{ circ}hbox{C}$ on 4H-SiC MOS capacitors and vertical DMOSFETs with 50-nm-thick nitrided oxides in order to better understand the physical mechanisms of failure and to predict the component reliability. Oxide breakdown locations are shown to have no correlation to defects in the SiC epitaxial layer. Characterization of the electric-field acceleration of failures indicates that failure modes differ at low and high electric fields. Specifically, extrapolations from measurements at electric fields greater than 8.5 MV/cm predict anomalously high reliability at normal operating fields. Thus, we have shown that SiC MOS reliability characterization must ensure that electric field stresses be performed at low electric fields in order to accurately predict failure times.      

Low electric field breakdown of thin SiO2 films understatic and dynamic stress

A comprehensive study of Time-Dependent Dielectric Breakdown (TDDB) of 6.5-, 9-, 15-, and 22-nm SiO₂ films under dc and pulsed bias has been conducted over a wide range of electric fields and temperatures. Very high temperatures were used at the wafer level to accelerate breakdown so tests could be conducted at electric fields as low as 4.5 MV/cm. New observations are reported for TDDB that suggest a consistent electric field and temperature dependence for intrinsic breakdown and a changing breakdown mechanism as a function of electric field. The results show that the logarithm of the median-test-time-to failure, log (t₅₀), is described by a linear electric field dependence with a field acceleration parameter that is not dependent on temperature. It has a value of approximately 1 decade/MV/cm for the range of oxide thicknesses studied and shows a slight decreasing trend with decreasing oxide thickness. The thermal activation E_a ranged between 0.7 and 0.95 eV for electric fields below 9.0 MV/cm for all oxide thicknesses. TDDB tests conducted under pulsed bias indicate that increased dielectric lifetime is observed under unipolar and bipolar pulsed stress conditions, but diminishes as the stress electric field and oxide thickness are reduced. This observation provides new evidence that low electric field aging and breakdown is not dominated by charge generation and trapping