Nonuniform threshold voltage instabilities in p-channel silicon-gate m.o.s. transistors

To account for the changes in the Cgs/Vgs and Ids/Vgs characteristics of silicon-gate m.o.s. transistors after a period of b.t stress, a theoretical model is proposed in which charge trapped at the Si?SiO2 interface is distributed nonuniformly along the length of the channel.     

Current instabilities in GaN-based devices

Current dispersion effects have been experimentally investigated in a variety of AlGaN/GaN heterostructure FETs with large signal and switching measurements including HEMTs with doped and undoped barrier layer. A range of dispersion frequencies from 10^-3 Hz to 10 GHz were observed, where the output current amplitude is drastically reduced. Through this effect the full channel charge of an AlGaN/GaN heterostructure FET may be completely depleted under specific bias conditions. This indicates that this phenomena cannot be related to deep traps alone, but is also connected to piezorelated charge states and conduction to these states     

Tradeoff between threshold voltage and breakdown in high-voltage double-diffused MOS transistors

The design of junction isolated DMOS transistors suitable for monolithic integration has been studied. The purpose of this correspondence is to describe one of the key tradeoffs when designing these devices for high breakdown voltages (200 V for our example). It is a tradeoff primarily between threshold voltage and the punchthrough voltage of the channel diffusion, however, the avalanche breakdown voltage, on-resistance, and source-to-substrate punchthrough voltage are also affected. As an example, the design of a device for 200-V operation is described. The discussion is, however, general and can be applied to other DMOS designs as well.     

Influence of impact-ionization-induced instabilities on the maximumusable output voltage of Si-bipolar transistors

The onset of impact-ionization-induced instabilities limits the operating range of Si-bipolar transistors, especially in power stages. Therefore, analytical relations which characterize the onset of instabilities are derived for different driving conditions (mainly V_BE=const. and I_E=const.) and arbitrary transistor geometries. They allow the designer and technologist to calculate the maximum usable dc output voltage in dependence on transistor dimensions and technological parameters. As a consequence, the voltage range above BV_CE0 can now be more intensively and reliably used and thus the performance potential of a given technology can be better exploited. However, the reduction of the maximum tolerable output voltage with increasing emitter (or collector) current must be carefully considered. The presented theory and analytical results are verified by three-dimensional (3-D) transistor simulations and by measurements     

An SRAM design using dual threshold voltage transistors and low-power quenchers

Static random access memories (SRAM) are widely used in computer systems and many portable devices. In this paper, we propose an SRAM cell with dual threshold voltage transistors. Low threshold voltage transistors are mainly used in driving bit-lines while high threshold voltage transistors are used in latching data voltages. The advantages of dual threshold voltage transistors can be used to reduce the access time and maintain data retention at the same time. Also, the unwanted oscillation of the output bitlines of memories caused by large currents in bitlines is reduced by adding two back-to-back quenchers. The proposed quenchers not only prevent oscillation, but also reduce the idle power consumption when the memory cells are not activated by wordline signals. Meanwhile, a large noise margin is provided such that the gain of the sense amplifier will not be reduced to avoid the oscillation. Hence, high-speed and low-power readout operations of the SRAMs are feasible.     

Temperature dependence of hot-carrier degradation in silicon-on-insulator dynamic threshold voltage MOS transistors

The authors analyze the influence of temperature on hot-carrier degradation of silicon-on-insulator (SOI) dynamic threshold voltage MOS (DTMOS) devices. Both low and high stress gate voltages are used. The temperature dependence of the hot-carrier effects in DTMOS devices is compared with those in SOI partially depleted (PD) MOSFETs. Possible physical mechanisms to explain the obtained results are suggested. This work shows that even if the stress gate voltage is low, the degradation of DTMOS devices stressed at high temperature could be significant.     

Effects of high field stresses on threshold voltage of CMOS transistors

In this paper, the threshold voltage instabilities of CMOS transistors under gate bias stress at high gate oxide electric fields have been investigated. It is shown that in presence of the negative gate bias stress threshold voltage of n-channel MOSTs decreases, while threshold voltage of p-channel MOSTs increases. These results are explained by positive fixed oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps. On the other hand, it is shown that in the presence of the positive gate bias stress threshold voltage of n-channel MOSTs decreases at the beginning as well, but after a certain time period starts to increase, while threshold voltage of p-channel MOSTs continuously increases. The initial threshold voltage behaviour is explained by positive fixed oxide charge increase as well; however, in this case it is caused by the electron tunneling from oxide electron traps into oxide conduction band. The later threshold voltage increase of n-channel MOSTs is explained by surface state charge increase due to tunnel current flowing through the oxide.     

Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment

High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping level makes it possible to attain a threshold voltage of GaN transistors close to V _th = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to V _th = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.     

Quantum size impacts on the threshold voltage in nanocrystalline silicon thin film transistors

Based on the analysis of Poisson equation, an analytical threshold voltage model including quantum size effect of nc-TFTs (nanocrystalline silicon thin film transistor) has been proposed in this paper. The results demonstrate that the proposed simplified expression of threshold voltage agree perfectly with numerical calculation. The threshold voltage in nc-TFTs strongly depends on the size of silicon grain when the size of silicon grain is less than 20 nm. Such a strong dependent relation results from the large changes in the bandgap and dielectric constant due to quantum size effects when the size of silicon grain is in the regime of nano-scale. The theoretical investigation also demonstrates that the grain boundary trap density compared to the active dopant density gives a main contribution to the threshold voltage. This implies that the grain size must be larger than 30 nm in order to avoid threshold voltage variation from different technological processes.     

Model for the temperature dependence of the threshold voltage of modulation-doped field-effect transistors

A model for the temperature dependence Of the threshold voltage of modulation-doped FET's caused by traps in doped AlGaAs is presented. The model takes into account the charge distribution in the depletion region determined by the temperature and time-dependent occupation of traps. The theory shows excellent agreement with experiment in the temperature range 77 to 400 K.     

Impact of preanneal process on threshold voltage of MOS transistors for trench DRAM

As the first step of DRAM manufacture, preanneal process plays an important role in determining the threshold voltage variation. It is found that the higher trans-1,2-dichloroethene flow in pad oxide growth and the higher nitrogen flow in high-temperature annealing step would respectively engender a lower boron segregation coefficient and higher nitridation of the oxide, both modify the boron distribution in the substrate and consequently the behavior of the threshold voltage. As the feature size of DRAM devices enter nanometer regime, besides gate oxidation, ion implantation and related thermal processes, the impact of preanneal process condition should be prudentially taken into consideration for rigorous control of the threshold voltage in the advanced DRAM production.     

Analytical model for threshold voltage of double gate bilayer graphene field effect transistors

A new model for threshold voltage of double-gate Bilayer Graphene Field Effect Transistors (BLG-FETs) is presented in this paper. The modeling starts with deriving surface potential and the threshold voltage was modeled by calculating the minimum surface potential along the channel. The effect of quantum capacitance was taken into account in the potential distribution model. For the purpose of verification, FlexPDE 3D Poisson solver was employed. Comparison of theoretical and simulation results shows a good agreement. Using the proposed model, the effect of several structural parameters i.e. oxide thickness, quantum capacitance, drain voltage, channel length and doping concentration on the threshold voltage and surface potential was comprehensively studied.     

Temperature dependence of apparent threshold voltage of silicon MOS transistors at cryogenic temperatures

Measurements of apparent threshold voltages for conduction of bothn-p-nandp-n-pMOS-     

Analysis of the threshold voltage and its temperature dependence in electrolyte-insulator-semiconductor field-effect transistors (EISFET's)

A first-order theoretical model is developed that allows the temperature dependence of the threshold voltage of an electrolyte-insulator-semiconductor field-effect transistor (EISFET) to be determined. Specifically, a detailed analysis is presented for a representative cell consisting of a Ag/AgCI reference electrode, a simple 1:1 electrolyte, and an ISFET. In addition, an insulator is assumed for which the site-binding model is applicable. All temperature-dependent parameters are identified and quantitatively described. Results are computed for SiO2and Al2O3insulators over a pH range from 1 to 12, and a temperature range from 20 to 80°C. Graphs of the surface-site occupancies versus the pH are shown to provide useful physical insight in interpreting the results. The threshold-voltage temperature coefficient is shown to be highly dependent on the pH; however, for Al2O3, over a 20-80°C range, the variation is roughly linear.     

An efficient method for determining threshold voltage, seriesresistance and effective geometry of MOS transistors

An accurate and robust method of extracting the threshold voltage, the series resistance and the effective geometry of MOS transistors is presented. The method is based on efficient nonlinear optimization using an iterative linear regression procedure which usually converges in less than four rounds. Thereby extracted parameters are obtained from analytical expressions for the solutions to a linear system of equations whereby time consuming numerical differentiations are avoided. MOSFET parameters are explicitly identified as parameters of an underlying widely used device model that is a good approximation for operation in the linear region. The method is particularly suitable for process characterization and can be used on as few as twelve data points (three data points from each of four different size transistors). By connecting external resistors in series with the transistors, we show that the extracted values of the parameters are independent of the series resistance     

A method of threshold voltage and current gain factor estimation for CMOS IC input transistors

A statistical technique for input transistor characteristic extraction and transistor threshold voltage and current gain factor estimation for a CMOS IC is presented. The technique is based on the sequential approach to segmented curve estimation. The method enables IC customers to make their own assessment of instability mechanisms in CMOS ICs without using special test device structures.     

The effects of interconnect process and snapback voltage on the ESDfailure threshold of NMOS transistors

The electrostatic discharge (ESD) failure threshold of NMOS transistors in a shelf-aligned TiSi₂ process has been identified to be sensitive to both interconnect processes and device structures. For a consistently good ESD protection level, there is a maximum limit of TiSi₂ thickness formed on a shallow junction. The thickness is less than that required to ensure a low junction leakage current. The effect of contact processes on ESD is also studied. Both the size and quantity of contacts on the source-drain area of NMOS transistors have important effects on the ESD failure threshold of the NMOS transistor. The ESD failure threshold voltage an NMOS transistor is strongly correlated with the snapback voltage of its lateral parasitic bipolar transistor. The ESD pass voltage or the highest current that an NMOS transistor can withstand is a decreasing function of its parasitic bipolar snapback voltage. This finding explains why an abrupt junction device has a higher ESD failure threshold voltage than a graded-junction device. The gate potential of an NMOS transistor also has important effects on its failure threshold voltage     

Gate leakage current in GaN-based mesa- and planar-type heterostructure field-effect transistors

The excessive gate leakage current of the planar- and mesa-type InAlN/GaN heterostructure field-effect transistors (HFETs) is evaluated. It is found that the gate current of the mesa-type HFETs is higher than that of the planar devices, particularly at low biases. Analyses of the gate current considering different transport mechanisms yielded identical thermionic currents (i.e., an identical Schottky barrier height) but a significantly higher leakage component in the mesa-type HFETs than in the planar devices. This additional current component observed in the mesa-type devices shows a nearly ohmic behavior. Mapping by the electron-beam induced current technique confirms an enhanced current located under the expanded gate contact and on the part of the mesa-sidewall, where the gate contact is placed. Two-dimensional simulation of the device structure shows that considerable part of the gate leakage current flows through the GaN buffer layer. These results underline the importance of a proper design of the device structure and layout (i.e., the use of planar structure with device insulation prepared by ion implantation rather than by mesa technique), and of the preparation of the GaN buffer (it should be semi-insulating) in order to fabricate reliable, low leakage current GaN-based HFETs.     

The influence of constructive parameters on the threshold voltage of nanodimensional p-Channel SOI MOS transistors

The influence of the thickness of the silicon film and hole concentration in the p-channel nanodimensional MOS transistor based on the SOI structure is considered. The formulas for the computation of these dependences are derived and graphic dependences are presented.