A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

The wafer warpage problem, mainly originated from coefficient of thermal expansion mismatch between the materials, becomes serious in wafer level packaging as large diameter wafer is adopted currently. The warpage poses threats to wafer handling, process qualities, and can also lead to serious reliability problems. In this paper, a novel mechanical diced trench structure was proposed to reduce the final wafer warpage. Deep patterned trenches with a depth about 100 μm were fabricated in the Si substrate by mechanical dicing method. Both experiment and simulation approaches were used to investigate the effect of the trenches on the wafer warpage and the influence of the geometry of the trenches was also studied. The results indicate that, by forming deep trenches, the stress on the individual die is decoupled and the total wafer warpage could be reduced. The final wafer warpage is closely related to the trench depth and die width. Trenched sample with a depth of 100 μm can decrease the wafer warpage by 51.4%.     

Influence of the Viscoelastic Properties of the Polyimide Dielectric Coating on the Wafer Warpage

Polyimide is widely used as the dielectric material in wafer level packaging. One potential problem with its application is the warpage and stress generated in the curing process. This paper investigated the material properties of polyimide and its influence on the wafer warpage. The viscoelastic properties of polyimide film were measured and a mathematical model of the properties was developed. Finite element analysis of the wafer warpage was performed and this indicates that the viscoelastic material model gave the best prediction. To better understand the causation of the warpage, curvature evolution of the polyimide-coated silicon wafer during its curing process was measured by a multi-beam optical sensor system. It was found that the warpage was mainly induced by the coefficient of thermal expansion mismatch and that the cure shrinkage of polyimide had little effect. Additionally, the effect of the cooling rate on the wafer warpage was also studied. Both simulation and experiment results showed that a slower cooling rate in the temperature range around the glass transition temperature (T _g) of polyimide will help to reduce the final wafer warpage.     

Warpage evolution of overmolded ball grid array package during post-mold curing thermal process

Two of the main driving forces for warpage deformation and residual stress in electronic packages are the thermal expansion mismatch between dissimilar package constituents and the crosslinking reaction of polymers during packaging thermal processes. For the purpose of quantitatively characterizing these two driving forces and assessing the process effect on warpage deformation, experimental and numerical analyses were applied to study the warpage evolution of overmolded ball grid array (BGA) package under post-mold curing (PMC) thermal histories. From in situ shadow Moiré warpage analyses on bimaterial and package specimens, it was observed that, during the isothermal curing condition, a significant increase in specimen warpage occurred as a result of molding compound shrinkage. A numerical modeling procedure that incorporates the models for the thermochemical cure kinetics, the curing- and chemical aging-induced shrinkage strains, and the cure-dependent viscoelastic relaxation modulus for the molding compound was then applied to simulate and compare to the experimentally obtained warpage evolutions. It can be seen from the analysis results that the evolution of package warpage over multiple thermal histories can be superpositioned by the thermal expansion mismatch-driven warpage change during non-isothermal stages and the chemical shrinkage-induced warpage evolution during isothermal aging at temperatures above the material glass transition point.     

In situ fault detection of wafer warpage in microlithography

Wafer warpage is common in microelectronics processing. Warped wafers can affect device performance, reliability and linewidth control in various processing steps. We proposed in this paper an in situ fault detection technique for wafer warpage in microlithography. Early detection will minimize cost and processing time. Based on first principle thermal modeling, we are able to detect warpage fault from available temperature measurements. Experimental results demonstrate the feasibility and repeatability of the approach. The proposed approach is applicable to other semiconductor substrates.     

扇出型晶圆级封装中圆片翘曲研究

在扇出型晶圆级封装工艺中,由于芯片材料与塑封料之间的热膨胀系数差异,晶圆塑封过程中必然会形成一定的翘曲.如何准确预测晶圆的翘曲并对翘曲进行控制是扇出型晶圆级封装技术面临的挑战之一.在讨论圆片翘曲问题时引入双层圆形板弯曲理论与复合材料等效方法,提出一套扇出型晶圆级封装圆片翘曲理论模型,并通过有限元仿真与试验测试验证了该翘...     

Numerical modeling of warpage induced in QFN array molding process

Warpage is a critical issue for QFN array molding process. In this paper, a cure-dependent viscoelastic constitutive model is established to model the cure-induced warpage in array molding process. For the relaxation modulus functions of the packaging polymer, the equilibrium moduli are modeled with a model based on scaling analysis and the relaxation behavior of the transient part is described by the cure-dependent relaxation amplitude and reduced relaxation times which are based on the time-conversion superposition principle. The cure-dependent parameters are characterized by using an integrated approach of dynamical mechanical analysis (DMA) and differential scanning calorimetry (DSC) measurements. Finite element modeling is carried out for three configurations of a carrier package map mould and the warpage induced during the curing process and cooling down is predicted. The results show that warpage induced during the curing process has significant contribution on the total warpage of the map.     

Mechanism of warpage orientation rotation due to viscoelastic polymer substrates during thermal processing

The warpage orientation, which refers to the direction of maximum and minimum curvatures in a cylindrical warpage, was observed to have changed by flipping from a concave to a convex shape during thermal processing. In this paper, the mechanism of the warpage orientation rotation is demonstrated through analyzing the stress state and curvatures of the specimens using finite element method (FEM) simulations and experiments. It is revealed that the warpage transition temperature, where the curvature changes to other shapes, corresponds to the stationary point of the stress-temperature curve and the curvature change of the minimum direction precedes the curvature change of the maximum direction during the warpage orientation rotation. This precedence results from the stress relaxation of the fiber reinforced polymer (FRP) substrate. Because the curvature of minimum direction flips backward in advance of maximum direction, the cylindrical warpage shape converts to a saddle shape and it induces the rotation of the warpage orientation. The simulation without the viscoelastic properties of the FRP substrate is conducted and used for comparison in order to verify the stress relaxation effect of the warpage orientation rotation phenomenon. In conclusion, it is demonstrated that the viscoelastic properties of the FRP substrate are a critical factor in analyzing the warpage orientation rotation and its behavior.     

Study of thinned Si wafer warpage in 3D stacked wafers

3D (three-dimensional) wafer stacking technology has been developed extensively recently. One of the many technical challenges in 3D stacked wafers, and one of the most important, is wafer warpage. Wafer warpage is one of the root causes leading to process and product failures such as delamination, cracking, mechanical stresses, within wafer (WIW) uniformity and even electrical failure. In this study, the wafer warpage of thinned Si wafers in stacked wafers has been evaluated. Si wafer or glass was used as a thick substrate, and Cu or polyimide was used as the bonding material. The top Si wafer in the bonded stack was ground down to 20–100 μm, and wafer curvature was measured. Wafer curvature and how it relates to bonding material, substrate material of the stacked layers, and thickness of thinned Si wafer will be discussed.     

Thermal design of hot plate for 300-mm wafer heating in post-exposure bake

Temperature uniformity of a wafer during post-exposure bake (PEB) in lithography is an important factor in controlling critical dimension (CD) uniformity. In this study, a new hot plate system for the PEB of a 300-mm wafer was analyzed and designed. First, temperature deviation on the wafer caused by warpage was investigated, and the heater pattern of the multi-zone hot plate in the bake system was numerically analyzed. Then, a new heater pattern to enhance the temperature uniformity was proposed and tested experimentally. As a result, temperature uniformity within 0.087 °C on a 300-mm wafer was achieved.     

Time-domain viscoelastic constitutive model based on concurrent fitting of frequency-domain characteristics

A numerical procedure for constructing the multiaxial viscoelastic model for polymeric packaging material over a wide range of temperature is presented. By using the proposed best-fitting procedure, experimentally measured frequency-domain Young's and shear storage moduli are used to calculate the time-domain bulk and shear relaxation moduli which describe the three-dimensional constitutive behavior of a viscoelastic solid. The numerical procedure incorporates restrictions that ensure that the derived time-domain material function is physics compatible. The proposed procedure was applied to construct the viscoelastic constitutive models of epoxy molding compounds (EMCs), and compared to results obtained by using approximate-formula based direct conversion procedure. It was shown that, without using the proposed procedure, the directly calculated time-dependent Poisson's ratio oscillates significantly in the rubbery regime and is physically inadmissible. To validate the constitutive model constructed by using the proposed procedure, a numerical finite element model that incorporates the viscoelastic constitutive model of the EMC was applied to simulate warpage of an overmolded package under the solder reflow process and compared to experimental shadow Moiré measurements.     

Determination of residual strains of the EMC in PBGA during manufacturing and IR solder reflow processes

Even though recently published results indicated that residual strains of the epoxy molding compound (EMC) play a key role on the warpage values and shapes of the plastic ball grid array (PBGA) packages, it is still unknown about how these residual strains build up and change during the manufacturing and infrared (IR) solder reflow processes. The purpose of this study is to quantify the residual strains of the EMC in the PBGA packages during the aforementioned processes using a combination of experimental, theoretical and numerical approaches. In the experiments, a full-field shadow moiré is used for measuring their real-time out-of-plane deformation (warpage), during heating and cooling conditions, of two types of the PBGA specimens (without a silicon chip inside) with the same EMC but different substrates (with glass transition temperature T_g = 172 and 202 °C). Furthermore, Timoshenko’s bi-material theory associated with the measured and temperature-dependent elastic moduli and coefficients of thermal expansion for the EMC and substrates is applied for extracting residual strains of the EMC from shadow moiré results. In the analysis, the finite element method cooperating with those determined residual strains is employed to numerically simulate the thermal-induced deformations of the PBGA specimens, in order to verify mechanics. The full-field warpage of the specimens from shadow moiré is documented before and after post-mold curing, solder reflow and during the temperature cycling (from room temperature to 260 °C). The residual strains of the EMC for the specimens with low-T_g and high-T_g substrates after post-mold curing are found to be 0.059% and 0.134%, respectively, which double those before post-mold curing, and further down to 0.035% and 0.08% after the first thermal cycling. After the first cycling, the residual strains remain almost constant during heating and cooling processes. This phenomenon is also observed at lead-free solder reflow processes. Therefore, the residual strains of the EMC induced by the chemical shrinkage of the EMC curing and possibly mold flow pressure are different between the specimens with low-T_g and high-T_g substrates, and these residual strains could change during post-mold curing and the first solder reflow processes.     

A model for wafer scale variation of material removal rate in chemical mechanical polishing based on viscoelastic pad deformation

It is well known that within-wafer nonuniformity (WIWNU) due to the variation in material removal rate (MRR) in chemical mechanical polishing (CMP) significantly affects the yield of good dies. The process control for a batch CMP operation is further complicated by wafer-to-wafer nonuniformity (WTWNU) caused by MRR decay when a number of wafers are polished with the same unconditioned pad. Accordingly, the present work focuses on modeling the WIWNU and WTWNU in CMP processes. Various material removal models suggest that the MRR is strongly influenced by the interface pressure. It is also well known that the viscoelastic properties of the pad play an important role in CMP. In the present work, an analytical expression for pressure distribution (and its associated MRR) at the wafer-pad interface for a viscoelastic pad is developed. It is observed that under constant load, which is typical during main polishing in CMP, the spatial distribution of the interface pressure profile may change with time from edge-slow to edge-fast, depending on the combination of wafer curvature, down pressure, and pad properties. For constant displacement operations, the pressure profile retains its edge-slow or edge-fast characteristics over time. The analytical model predictions of MRR based on viscoelastic pad properties also correlate very well to existing experimental observations of MRR decay when an unconditioned pad is used to polish a number of wafers. Based on these observations, it may be conjectured that the viscoelastic material properties of the pad play a primary role in causing the observed MRR decay. The analytical results obtained in the present work can also provide an estimation of evolution of thickness removal distribution over the entire wafer. This may be used for determining the optimum thickness of the overburden material and its polishing time, and for effective control of CMP processes.     

Prediction of defect onset conditions in heat cycling based on athermoelastic wafer model

A thermoelastic wafer model is proposed for predicting defect onset conditions during heat cycling in a furnace. This model is formulated for application to the plane stress state under thermal loading. The wafer temperature is calculated by a wafer temperature model proposed in a previous work. Predictions are tested by comparison with the thermal stresses resolved on the slip systems of the silicon crystal under the process conditions (i.e. furnace temperature, insertion velocity, and wafer spacing). When the proposed model is applied to 125-mm diameter and 150-mm-diameter wafers, it is shown that the thermal stress level is reduced to about a half by increasing the wafer spacing by a factor of two or three. Accordingly, the predicted defect onset results based on this model are in reasonable agreement with experiments     

Characterization of chip scale packaging materials

The mechanical stability of Chip Scale Packages (CSP) used in surface mount technology is of primary concern. The dominant issues are package warpage and solder fatigue in solder joints under cyclic loads. To address these issues, molding compound and die attach film were characterized with finite element method which employed a viscoelastic and viscoplastic constitutive model. The model was verified with experiments on package warpage, PCB warpage and solder joint reliability. After the correlation was observed, the effect of molding compound and die attach film on package warpage and solder joint reliability was investigated. It was found that package warpage tremendously affected solder joint reliability. Furthermore, a die attach film was developed based on results of the modeling. CSP with the developed die attach film are robust and capable of withstanding the thermal stresses, humidity and high temperatures encountered in typical package assembly and die attach processes. Also, a lead free solder is discussed based on the results of creep testing. This paper presents the viscoelastic and viscoplastic constitutive model and its verification, the optimum material properties, the experimental and simulated reliability and performance results of the u*BGA packages, and the lead free solder creep.     

Experimental identification of thermal induced warpage in polymer–metal composite films

Composite thick films consisting of multi-layered polymers and metals are widely used in integrated circuits(IC) and its packaging, and it arises intricate stress and warpage problems due to complex inner stress distribution and evolution. The wafer warpage origination and evolution of multi-layered polyimide (PI)/Cu composite film is measured in-situ by a Multi-beam Laser Optical Sensor (MOS) system. It's found that PI has an intricate influence on wafer warpage evolution and Cu plastic deformation due to viscoelasticity and glass-transition, and the influence differs in different structures and at different temperatures. Nonlinearity of the curvature–temperature curve of the composite occurs at much lower temperature than in single PI or Cu film, showing mutual effect of PI and Cu. Unlike bare or capping PI film that totally stress relaxed at high temperature, bottom PI coated by Cu film sustains a medium compressive stress, indicating that Cu coating film has restrained stress relaxation of PI. The warpage evolution during heating is different from that during cooling, perhaps due to different deformation mechanism.     

An In Situ Approach to Real-Time Spatial Control of Steady-State Wafer Temperature During Thermal Processing in Microlithography

We proposed an in situ method to control the steady-state wafer temperature uniformity during thermal processing in microlithography. Thermal processing of wafer in the microlithography sequence is conducted by the placement of the wafer on the bake-plate for a given period of time. A physical model of the thermal system is first developed by considering energy balances on the system. Next, by monitoring the bake-plate temperature and fitting the data into the model, the temperature of the wafer can be estimated and controlled in real-time. This is useful as production wafers usually do not have temperature sensors embedded on it, these bake-plates are usually calibrated based on test wafers with embedded sensors. However, as processes are subjected to process drifts, disturbances, and wafer warpages, real-time correction of the bake-plate temperatures to achieve uniform wafer temperature at steady state is not possible in current baking systems. Any correction is done based on run-to-run control techniques which depends on the sampling frequency of the wafers. Our approach is real-time and can correct for any variations in the desired steady-state wafer temperature. Experimental results demonstrate the feasibility of the approach     

Thermal uniformity of 12-in silicon wafer during rapid thermalprocessing by inverse heat transfer method

Through an inverse heat transfer method, this paper presents a finite difference formulation for determination of incident heat fluxes to achieve thermal uniformity in a 12-in silicon wafer during rapid thermal processing. A one-dimensional thermal model and temperature-dependent thermal properties of a silicon wafer are adopted in this study. Our results show that the thermal nonuniformity can he reduced considerably if the incident heat fluxes on the wafer are dynamically controlled according to the inverse-method results. An effect of successive temperature measurement errors on thermal uniformity is discussed. The resulting maximum temperature differences are only 0.618, 0.776, 0.981, and 0.326°C for 4-, 6-, 8- and 12-in wafers, respectively. The required edge heating compensation ratio for thermal uniformity in 4-, 6-, 8and 12-in silicon wafers is also evaluated     

Prediction of thermo-mechanical integrity of wafer backend processes

More than 65% of IC failures are related to thermal and mechanical problems. For wafer backend processes, thermo-mechanical failure is one of the major bottlenecks. The ongoing technological trends like miniaturization, introduction of new materials, and function/product integration will increase the importance of thermomechanical reliability, as confirmed by the ITRS (International technology roadmap for semiconductors; [1]). Since most of the thermomechanical problems initiate in the design phase, failure prevention-designing for reliability, is strongly desired. To support wafer backend process development, it is necessary to develop reliable and efficient methodologies (both testing and modeling) to predict the thermal and mechanical behavior of backend processes.This paper presents our research results covering the backend process reliability modeling considering both thermal and mechanical (CMP) loading. The emphasis is particularly on the effect of using Cu/SiLK low-dielectric-constant (low-k) structure instead of the traditional Al/SiO₂. SiLK is a particular polymeric low-k material developed by the Dow Chemical Company [2] [Adv. Mater. 12 (2002) 1767].Our results shows that Cu/SiLK structures exhibit significantly different reliability characteristics than their aluminum predecessors, and that they are more critical from several design aspects. This not only makes the stress management in the stacks more difficult, but also strongly impacts packaging.     

Scheduling single-armed cluster tools with reentrant wafer flows

A cluster tool for semiconductor manufacturing consists of several single-wafer processing chambers and a wafer-handling robot in a closed environment. The use of cluster tools is extended to reentrant processes such as atomic layer deposition, where a wafer visits a processing chamber more than once. Such a reentrant wafer How complicates scheduling and control of the cluster tool and often causes deadlocks. We examine the scheduling problem for a single-armed cluster tool with various reentrant wafer flows. We develop a convenient method of modeling tool operational behavior with reentrant wafer flows using Petri nets. By examining the net model, we then develop a necessary and sufficient condition for preventing a deadlock. We also show that the cycle time for the asymmetric choice Petri net model for a reentrant wafer How can be easily computed by using the equivalent event graph model. From the results, we systematically develop a mixed integer programming model for determining the optimal tool operation sequence, schedule, and cycle time. We also extend a workload measure for cluster tools with reentrant wafer flows. Finally, we discuss how our results can be used for engineering a cluster tool. We compare two proposed strategies, sharing and dedicating, of operating the parallel processing chambers for identical process steps.     

Prediction of cure induced warpage of micro-electronic products

Prediction of residual stresses in micro-electronic devises is an important issue. Virtual prototyping is used to minimize residual stresses in order to prevent failure or malfunction of electronic products.Already during encapsulation stresses build up due to polymerization induced shrinkage of the molding compound. Differences in coefficient of thermal expansion of the involved materials cause additional stresses during cooling down from molding to ambient temperature. Since industry is availed by reliable prediction methods, detailed material models are required. In electronic packaging, mechanical properties of most of the involved materials have constant mechanical properties. However, the viscoelastic properties of the encapsulation material depends highly on temperature and degree of cure. Reliable predictions of residual stresses require simulation models which take into account the effect of temperature and conversion level.In this paper, properties of molding compound are discussed which are relevant for the prediction of warpage of micro-electronics products. The models for the individual properties are combined to one single model suitable for finite element simulations. The numerical implementation in finite element code is not standard and is done by using user-subroutines.Validation experiments are performed in order to verify the developed material model which is done by measuring and predicting the warpage of a mold map. A Topography and Deformation Measurement (TDM) device is used to measure the deformations at elevated temperatures in a non-intrusive way such that the developed material model could be validated in a broad range of temperature.Finally, simulations are carried out with simplified material models of molding compound. The results of these simulations are compared with results obtained with the cure dependent viscoelastic model and real warpage data. From these comparisons it is concluded that for reliable prediction of warpage, the cure dependent viscoelastic model is has to be used.