A subgap density of states modeling for the transient characteristics in oxide-based thin-film transistors

The modeling of the transient subgap density of states (DOS) for the investigation of trap densities in the oxide-based thin-film transistors is proposed. The study is based on both transient measurements and physical modeling. In history, the subgap DOS modeling of trap densities have been studied according to the static-state current–voltage characteristics or the capacitance–voltage curves. However, the subgap DOS modeling for the transient curves is seldom proposed. In this study, the transient model of subgap DOS is discussed for amorphous In–Ga–Zn–O (a-IGZO) thin films. This model suggests the subgap DOS exhibits a transient behavior with an exponential distribution on the band edge and a Gaussian distribution in the deep gap level. This study could be helpful to understand and optimize the transient electrical properties of a-IGZO TFTs.     

Applications of the pulsed current-voltage (I-V) and capacitance-voltage (C-V) techniques for high-resistive gates in MOSFETs

Most modern semiconductor laboratories are equipped with scanning electron or atomic force microscopes based nanoprobing systems for electrical measurement of advanced technology node devices. These nanoprobing systems use a scanning electron or an atomic force microscope in their design to image and make electrical connection to the nanoscale contacts on these devices to perform DC electrical tests and examine their electric properties. While the conventional sweep DC I-V curves can reveal most failures in MOSFETs (metal-oxide-semiconductor field-effect-transistors), DC I-V tests have been found to be insufficient for identifying high-resistive gate faults. New techniques based on the pulsed I-V and high-frequency C-V measurements have been recently developed for detecting these high-resistive gate defects in these devices. In this paper, several test samples were manufactured and later measured using both the pulsed I-V and C-V methods to confirm their applicability. Finally, several real resistive gate device failure cases were examined using these same methods.     

Electrical transport and current properties of rare-earth dysprosium Schottky electrode on p-type GaN at various annealing temperatures

The electrical and current transport properties of rapidly annealed Dy/p-GaN SBD are probed by I-V and C-V techniques. The estimated barrier heights (BH) of as-deposited and 200℃ annealed SBDs are 0.80 eV (I-V)/0.93 eV (C-V) and 0.87 eV (I-V)/1.03 eV (C-V). However, the BH rises to 0.99 eV (I-V)/ 1.18 eV(C-V) and then slightly deceases to 0.92 eV (I-V)/1.03 eV (C-V) after annealing at 300℃ and 400℃. The utmost BH is attained after annealing at 300℃ and thus the optimum annealing for SBD is 300℃. By applying Cheung''s functions, the series resistance of the SBD is estimated. The BHs estimated by I-V, Cheung''s and Ψ_S-V plot are closely matched; hence the techniques used here are consistency and validity. The interface state density of the as-deposited and annealed contacts are calculated and we found that the N_SS decreases up to 300℃ annealing and then slightly increases after annealing at 400℃. Analysis indicates that ohmic and space charge limited conduction mechanisms are found at low and higher voltages in forward-bias irrespective of annealing temperatures. Our experimental results demonstrate that the Poole-Frenkel emission is leading under the reverse bias of Dy/p-GaN SBD at all annealing temperatures.     

/sup 60/Co gamma irradiation effects on n-GaN Schottky diodes

The effect of /spl gamma/-ray exposure on the electrical characteristics of nickel/n-GaN Schottky barrier diodes has been investigated using current-voltage (I-V), capacitance-voltage (C-V), and deep-level transient spectroscopy (DLTS) measurements. The results indicate that /spl gamma/-irradiation induces an increase in the effective Schottky barrier height extracted from C-V measurements. Increasing radiation dose was found to degrade the reverse leakage current, whereas its effect on the forward I-V characteristics was negligible. Low temperature (/spl les/50) post-irradiation annealing after a cumulative irradiation dose of 21 Mrad(Si) was found to restore the reverse I-V characteristics to pre-irradiation levels without significantly affecting the radiation-induced changes in C-V and forward I-V characteristics. Three shallow radiation-induced defect centers with thermal activation energies of 88 104 and 144 meV were detected by DLTS with a combined production rate of 2.12 /spl times/ 10/sup -3/ cm/sup -1/. These centers are likely to be related to nitrogen-vacancies. The effect of high-energy radiation exposure on device characteristics is discussed taking into account possible contact inhomogeneities arising from dislocations and interfacial defects. The DLTS results indicate that GaN has an intrinsically low susceptibility to radiation-induced material degradation, yet the effects observed in the Schottky diode I-V and C-V characteristics indicate that the total-dose radiation hardness of GaN devices may be limited by susceptibility of the metal-GaN interface to radiation-induced damage.     

Roughness of ZnS:Pr,Ce/Ta2O5 interface andits effects on electrical performance of alternating current thin-filmelectroluminescent devices

Roughness effects of neighboring dielectrics on electrical characteristics of thin-film electroluminescent devices were investigated in order to improve the understanding of physics for the devices. Atomic force microscopy analysis reveal that thicker bottom layer of Ta₂O₅ shows rougher surface resulting in the rougher surface of ZnS:Pr,Ce layer. It can be easily seen that the dc leakage current increases rapidly with increase of surface roughness. Furthermore, it is notable that the initiation field of Poole-Frenkel current conduction is lowered by increasing surface roughness of Ta₂O₅ thin film. Internal charge-phosphor field (Q _int-F_p) analysis and capacitance-ac voltage (C-V) analysis for ITO-Ta₂O₅-ZnS:Pr,Ce-Al and ITO-Ta₂O₅-ZnS:Pr,Ce-Ta₂O₅-Al show that the steady state phosphor field is smaller and C-V curve in transition region is less steep with increase of root-mean-square roughness between lower dielectric and phosphor layer in the alternating current thin-film electroluminescent (ACTFEL) devices. Therefore, we conclude that interface roughness is one of the physical factors to change the electrical performance of ACTFEL device     

Comparative physical and electrical metrology of ultrathin oxidesin the 6 to 1.5 nm regime

In this work, five methods for measuring the thickness of ultra-thin gate oxide layers in MOS structures were compared experimentally on n⁺ poly-SiO₂-p-Si structures. Three methods are based on electrical capacitance-voltage (C-V) and current-voltage (I-V) data and the other two methods are HRTEM and optical measurement. MOS capacitors with oxide thickness in the range 17-55 Å have been used in this study. We found that thickness extracted using QM C-V and HRTEM agree within 1.0 Å over the whole thickness range when a dielectric constant of 3.9 was used. Comparison between thickness extracted using quantum interference (QI) I-V technique and optical measurement were also within 1.0 Å for thickness 31-47 Å. However, optical oxide thickness was consistently lower than the TEM thickness by about 2 Å over the thickness range under consideration. Both optical measurement and QM C-V modeling yield the same thickness as the nominal oxide thickness increases (>50 Å)     

InP基异质结界面暗电流C-V测试分析

采用电化学C-V测试方法,测量分析了InP/InGaAs/InP外延结构的I-V特性,对异质结界面的电学性质进行了表征和分析.采用LP-MOCVD生长技术,对不同界面生长条件的三种样品进行了I-V和XRD测试,得到了InP向InGaAs界面转换采用中断生长、InGaAs向InP界面转换采用As/P直接切换的优化生长方式.用逐层化学腐蚀的方法,对比分析了I-V特性与XRD测试结果的关系,论证了I-V测试结果的有效性,指出了表征异质结界面电学质量的简洁方法.     

RF功率对非晶铟镓锌氧薄膜和器件电学特性的影响

The influence of radio frequency(RF) power on the properties of magnetron sputtered amorphous indium gallium zinc oxide(a-IGZO) thin films and the related thin-film transistor(TFT) devices is investigated comprehensively.A series of a-IGZO thin films prepared with magnetron sputtering at various RF powers are examined.The results prove that the deposition rate sensitively depends on RF power.In addition,the carrier concentration increases from 0.91 x 1019 to 2.15 x 1019 cm-3 with the RF power rising from 40 to 80 W,which may account for the corresponding decrease in the resistivity of the a-IGZO thin films.No evident impacts of RF power are observed on the surface roughness,crystalline nature and stoichiometry of the a-IGZO samples.On the other hand,optical transmittance is apparently influenced by RF power where the extracted optical band-gap value increases from 3.48 to 3.56 eV with RF power varying from 40 to 80 W,as is supposed to result from the carrierinduced band-filling effect.The rise in RF power can also affect the performance of a-IGZO TFTs,in particular by increasing the field-effect mobility clearly,which is assumed to be due to the alteration of the extended states in a-IGZO thin films.     

基于表面势的非晶IGZO薄膜晶体管分析模型

报道了一种适于模拟n沟道非晶IGZO薄膜晶体管(a-IGZO TFT)的直流I-V特性的分析模型。该模型充分考虑了深能级类受主态对自由电子的捕获,并将表面势的概念引入a-IGZO TFT结构。在分析器件能带结构和载流子输运的基础上,参考Si基MOSFET中表面势模型的分析方法,利用半导体-绝缘体界面电荷的泊松方程表达,并结合能带-电压关系,导出了器件饱和区和非饱和区的I-V解析表达式。通过Matlab编程模拟了a-IGZOTFT的转移特征曲线和输出特征曲线,对文献中实验数据进行拟合发现,提出的模型与实验数据均能很好地吻合。该模型结构简明,所包含的参数物理意义明确,有很强的实用性。     

Electrical characteristics of a 6H-SiC epitaxial layer grown by chemical vapor deposition on porous SiC substrate

Porous SiC (PSC) has been proposed as a buffer layer for reducing defects in epitaxial SiC layers. In this study, electrical characteristics of a 6H-SiC epitaxial layer grown by chemical vapor deposition on a porous SiC substrate (SiC-on-PSC) have been compared to those simultaneously grown on a standard SiC substrate (SiC-on-STD). Schottky barrier diodes (SBDs) have been fabricated on both epitaxial layers and then investigated with temperature-dependent current-voltage (I-V), capacitance-voltage (C-V), and deep-level transient spectroscopy (DLTS) measurements. The SBDs on both SiC-on-PSC and SiC-on-STD show about the same I-V and C-V characteristics, and at least four electron traps, i.e., B (0.75 eV), C (0.63 eV), D (0.40 eV), and E (0.16 eV), can be identically found in both SBDs by DLTS measurements. Thus, we conclude that the electrical quality of SiC-on-PSC is comparable to that of SiC-on-STD, and that the higher breakdown voltages observed in SBDs on SiC-on-PSC are not obviously related to a different defect structure.     

A new approach to determine the effective channel length and thedrain-and-source series resistance of miniaturized MOSFET's

A new decoupled C-V method is proposed to determine the intrinsic (effective) channel region and extrinsic overlap region for miniaturized MOSFET's. In this approach, a unique channel-length-independent extrinsic overlap region is extracted at a critical gate bias, so bias-independent effective channel lengths (L_eff) are achieved. Furthermore, the two-dimensional (2D) charge sharing effect is separated from the effective channel region. Based on this L_eff and the associated bias-dependent channel mobility, μ_eff , the drain-and-source series resistance (R_DS) can be derived from the I-V characteristics for each device individually. For the first time, the assumption or approximation for R_DS and μ_eff can be avoided, thus the difficulties and controversy encountered in the conventional I-V method can be solved. The 2D charge sharing effect is incorporated into the bias-dependent R_DS. This bias dependence is closely related to the drain/source doping profile and the channel dopant concentration. The proposed L_eff and R_DS extraction method has been verified by an analytical I-V model which shows excellent agreements with the measured I-V characteristics     

基于紫外图谱的盘式绝缘子放电强度径向分布研究

为研究盘式绝缘子积污放电的紫外图谱特征,提出了一种基于图像分割的光斑面积计算方法。首先,基于C-V模型,开展积污绝缘子紫外图像径向分布的研究。接着,与红外温度场曲线进行对比研究,验证其合理性。最后,研究不同电阻率、风速情况下积污绝缘子的紫外图谱特征。研究结果表明：C-V模型应用于图像处理中,具有较强的抗干扰性,适用于盘式绝缘子径向放电强度的研究;随着表面电阻率的降低,盘式绝缘子紫外光斑面积会增大;风速对盘式绝缘子放电强度有明显的影响;研究结果可为盘式绝缘子径向放电强度的评估提供一定的参考。     

Experimental comparison of RF power LDMOSFETs on thin-film SOI andbulk silicon

Simultaneously fabricated RF power LDMOSFETs on thin-film SOI and bulk silicon wafers. This work compares their DC current-voltage (I-V), capacitance-voltage (C-V), S-parameter, and 1.9-GHz load-pull characteristics and explains differences between them. The SOI LDMOSFET performance is shown to be largely similar to the performance of an equivalent bulk silicon LDMOSFET, but there are important differences. The SOI LDMOSFET has moderately lower on-state breakdown voltage due to increased body resistance. It also has significantly improved power-added efficiency due to reduced parasitic pad losses     

Investigation into sand mura effects of a-IGZO TFT LCDs

The reliability of liquid crystal display (LCD) panels based on amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) is investigated. It is revealed that the a-IGZO TFT LCDs also have sand mura issue at high operation temperature. Analysis shows that the sand mura is caused by the positive V_th shift of the a-IGZO TFTs. To suppress the V_th shift, fabrication process of the a-IGZO TFTs is optimized with a-IGZO channel layer annealed at 300 °C and etch-stop layer deposited at 250 °C. The process optimization lessens the absorbed and non-bonded oxygen atoms in the a-IGZO channel layer and desorbed water molecules on the back channel surface. The results show that the V_th shift is significantly alleviated and the sand mura is thus effectively minimized with the optimized process.     

无坑洞n-3C-SiC/p-Si(100)的LPCVD外延生长及其异质结构特性

在MBE/CVD高真空系统上,利用低压化学气相淀积(LPCVD)方法在直径为50mm的单晶Si(100)衬底上生长出了高取向无坑洞的晶态立方相碳化硅(3C-SiC)外延材料,利用反射高能电子衍射(RHEED)和扫描电镜(SEM)技术详细研究了Si衬底的碳化过程和碳化层的表面形貌,获得了制备无坑洞3C-SiC/Si的优化碳化条件,采用霍尔(Hall)测试等技术研究了外延材料的电学特性,研究了n-3C-SiC/p-Si异质结的I-V、C-V特性及I-V特性对温度的依赖关系.室温下n-3C-SiC/p-Si异质结二极管的最大反向击穿电压达到220V,该n-3C-SiC/p-Si异质结构可用于制备宽带隙发射极SiC/Si HBTs器件.     

Fast Thin-Film Transistor Circuits Based on Amorphous Oxide Semiconductor

Five-stage ring oscillators (ROs) composed of amorphous In/Ga/Zn/O (a-IGZO) channel thin-film transistors (TFTs) with the channel lengths of 10 mum were fabricated on a glass substrate. The a-IGZO layer was deposited by RF magnetron sputtering onto the unheated substrate. The RO operated at 410 kHz (the propagation delay of 0.24 mus/stage), when supplied with an external voltage of +18 V. This is the fastest integrated circuit based on oxide-semiconductor channel TFTs to date that operates faster than the ROs using conventional hydrogenated amorphous silicon TFTs and organic TFTs     

Electrical characterization of ultrathin oxides of silicon grown by N2O plasma assisted oxidation

The ultrathin (2.0–3.5 nm) oxides of silicon have gained renewed importance in view of ultra large scale integration (ULSI) of the silicon devices. In the present investigation, the ultrathin oxides are grown on (100) oriented p-type single side polished silicon using N₂0 plasma assisted oxidation in a PECVD reactor at 200°C. The oxide growth as a function of oxidation time is studied. The oxidation growth conforms to the reaction limited regime. In order to understand the electrical quality of Si/ultrathin SiO₂ interface, Al-thin SiO₂-Si tunnel capacitors are fabricated and their capacitance-voltage (C-V) and current-voltage (I–V) characteristics are studied. The effect of annealing on these oxides (termed as “post oxidation annealing”) has also been studied. The C-V characteristics of tunnel capacitors with “as grown” oxide showed a frequency dependence, possibly due to the presence of large fast interface state density. These fast interface states are observed to decrease with increasing oxidation time. The tunnel capacitors that the oxides undergone “post oxidation annealing” (POA) at 350°C in N₂ ambient for 20 minutes have shown practically no frequency dependence of the C-V characteristics; this observation along with the data on I-V characteristics confirms that POA reduces the interface state density considerably. The forward and reverse currents of POA capacitors are observed to decrease considerably indicating the reduction in the trap assisted tunneling transport process across the tunnel insulator.     

Investigation of Anomalous Inversion C–V Characteristics for Long-Channel MOSFETs With Leaky Dielectrics: Mechanisms and Reconstruction

This paper investigates anomalous inversion capacitance-voltage (C-V) attenuation for MOSFETs with leaky dielectrics. We propose to reconstruct the inversion C-V characteristic based on long-channel MOSFETs using the concept of intrinsic input resistance (R_ii). The concept of R_ii has been validated by segmented BSIM4/SPICE simulation. Our reconstructed C-V characteristics show poly-depletion effects, which are not visible in the two-frequency three-element method and agree well with the North Carolina State University-CVC simulation results. The intrinsic input resistance dominates the overall gate-current-induced debiasing effect (~95% for L = 20 mum) and can be extracted directly from the I-V characteristics. Due to its simplicity, our proposed R_ii approach may provide an option for regular process monitoring purposes.     

Parameter estimation and screening of solar cells

The aggregation (sorting) of the individual solar cells into an array is commonly based on a single operating point on the current-voltage (I-V) characteristic curve. an alternative approach for cell performance prediction and cell screening is provided by modelling the cell using an equivalent electrical circuit, in which the parameters involved are related to the physical phenomena in the device. These analytical models may be represented by a double exponential I-V characteristic with seven parameters, by a double exponential model with five parameters or by a single exponential equation with four or five parameters. In this article we address issues concerning methodologies for the determination of solar cell parameters based on measured data points of the I-V characteristic, and introduce a procedure for screening solar cells for arrays. We show that common curve-fitting techniques, e.g. least-squares, may produce many combinations of parameter values while maintaining a good fit between the fitted and measured I-V characteristics of the cell. Therefore, techniques relying on curve-fitting criteria alone cannot be used directly for cell parameterization. We propose a consistent procedure that takes into account the entire set of parameter values for a batch of cells. This procedure is based on a definition of a mean cell representing the batch, and takes into account the relative contribution of each parameter to the overall goodness of fit. the procedure is demonstrated on a batch of 50 silicon cells for Space Station Freedom.     

Effect of KOH treatment on the schottky barrier height and reverse leakage current in Pt/n-GaN

The effect of potassium hydroxide (KOH) treatment was investigated for Pt/n-GaN Schottky diodes using current-voltage (I-V) and capacitance-voltage (C-V) characteristics. Atomic force microscopy (AFM) showed that the surface profile did not change significantly as a result of KOH treatment. The Schottky barrier height increased for both I-V and C-V measurements. The reverse leakage current was also reduced by KOH treatment. By fitting these data to the reverse current based on the thermionic field emission (TFE) model, it was shown that the experimental results are consistent with the presence of high densities of surface states, which were reduced appreciably by KOH treatment. The similar behavior of Pt/n-GaN samples grown by hydride vapor phase epitaxy (HVPE) suggests that the KOH treatment is effective in improving the rectifying characteristics of Schottky barriers to n-GaN grown by both organometallic vapor phase epitaxy (OMVPE) and HVPE.