A review on thermal cycling and drop impact reliability of SAC solder joint in portable electronic products

Currently, the portable electronic products trend to high speed, light weight, miniaturization and multifunctionality. In that field, solder joint reliability in term of both drop impact and thermal cycling loading conditions is a great concern for portable electronic products. The transition to lead-free solder happened to coincide with a dramatic increase in portable electronic products. Sn–Ag–Cu (SAC) is now recognized as the standard lead free solder alloy for packaging interconnects in the electronics industry. The present study reviews the reliability of different Ag-content SAC solder joints in term of both thermal cycling and drop impact from the viewpoints of bulk alloy microstructure and tensile properties. The finding of the study indicates that the best SAC composition for drop impact performance is not necessarily the best composition for optimum thermal cycling reliability. The level of Ag-content in SAC solder alloy can be an advantage or a disadvantage depending on the application, package and reliability requirements. As a result, most component assemblers are using at least two (and in many cases even more) lead-free solder sphere alloys to meet various package requirements.     

Mechanical, thermal, and electrical analysis of a compliant interconnect

Ball grid array (BGA) package styles use solder balls as electrical interconnects between packages and application boards. Solder balls are rigid and tend to fracture under thermal fatigue and/or shock loading. Metalized polymer spheres (MPS) offer a more compliant interconnect, compared to solder balls, thereby increasing the thermal cycling fatigue life. A reduction in thermal and electrical performance may be expected for MPS interconnects as a result of its higher thermal and electrical resistances. A 5% and an 8% increase in MPS thermal resistance was measured for a carrier array ball grid array (CABGA) package and a plastic ball grid array (PBGA) package, respectively, compared to eutectic solder balls. However, this small reduction was offset by large gains in the solder joint life. A 1.6 times increase in the mean thermal fatigue life was measured for a CABGA using MPS interconnects compared to eutectic solder balls. A first-order model showed that eutectic solder balls provide greater process margins, compared to MPS interconnects, due to the ball collapse during reflow.     

Effect of substrate flexibility on solder joint reliability. Part II: finite element modeling

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue life significantly. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique and finite element modeling. The reliability of solder joints in real flip chip assembly with both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Finite element simulations were conducted to study the reliability of solder joints in flip chip on flex assembly (FCOF) and flip chip on rigid board assembly (FCOB) applying Anand model. Based on the finite element analysis results, the fatigue lives of solder joints were obtained by Darveaux’s crack initiation and growth model. The thermal strain/stress in solder joints of flip chip assemblies with different substrates were compared. The results of finite element analysis showed a good agreement with the experimental results. It was found that the thermal fatigue lifetime of FCOF solder joints was much longer than that of FCOB solder joints. The thermal strain/stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

Effect of substrate flexibility on solder joint reliability

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue lifetime significantly. The reliability of solder joint in flip chip assembly for both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Experimental results strongly showed that the thermal fatigue lifetime of solder joints in flip chip on flex assembly was much improved over that in flip chip on rigid substrate assembly. Debonding area of solder joints in flip chip on rigid board and flip chip on flex assemblies were investigated, and it was found that flex substrate could slow down solder joint crack propagation rate. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique. TMA results showed that flex substrate buckles or bends during temperature cycling and this phenomenon was discussed from the point of view of mechanics of the flip chip assembly during temperature cycling process. It was indicated that the thermal strain and stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

Sensitivity Design of DL-WLCSP Using DOE With Factorial Analysis Technology

Newer, faster, and smaller electronic packaging approaches with high I/O counts and more complex semiconductor devices are emerging steadily and rapidly. Wafer-level chip scaling package (WLCSP) has a high potential for future electronic packaging. However, the solder joint reliability for a large chip size of about 100 mm² without underfill remains a troubling issue that urgently requires a solution. To this end, a double-layer WLCSP (DL-WLCSP) with stress compliant layers and dummy solder joint is adopted in this research in order to study the design parameters of enhancing the solder joint fatigue life. To ensure the validity of the analysis methodology, a test vehicle of Rambus DRAM is implemented to demonstrate the applicability and reliability of the proposed DL-WLCSP. The results of the thermal cycling in the experimental test show good agreement with the simulated analysis. Furthermore, to investigate the reliability impact of the design parameters, including solder volume, the arrangement of the die-side and substrate-side pad diameter, second compliant layer thickness, die thickness, and the printed circuit board (PCB) thickness, a design of experiment (DOE) with factorial analysis is adopted to obtain the sensitivity information of each parameter by the three-dimensional nonlinear finite-element models (FEMs). The statistics results of the analysis of variance reveal that the thickness of the second stress compliant layer and the volume of the solder joint can effectively reduce the stress concentration phenomenon, which occurs around the outer corner of the solder joint. In addition, the evident interaction between design parameters can also be obtained. The smaller thermal strains can be achieved through a better combination of design parameters of the geometry so as to provide the actual requirement of the physical information prior to manufacturing     

Materials characterization of the effect of mechanical bending on area array package interconnects

The mechanical integrity of solder joint interconnects in PWB assemblies with micro-BGA, chip scale, and land grid array packages is being questioned as the size and pitch decrease. Some consumer products manufacturers have mechanically reinforced fine pitch package interconnects with an adhesive underfill, and others are evaluating the need for underfill on a case-by-case basis. Three-point cyclic bend testing provides a useful tool for characterizing the expected mechanical cycling fatigue reliability of PWB assemblies. Cyclic bend testing is useful for characterizing bending issues in electronic assemblies such as repetitive keypad actuation in cell phone products. This paper presents the results of three-point bend testing of PWB assemblies with fine pitch packages. The solder joints on ceramic components performed better than a laminate interposer component in bend testing, because of the stiffening effect of the ceramic packaging materials. The methodology of materials analyses of the metallurgy of solder interconnects following mechanical bending and thermal cycle testing is described. The microstructure and fracture surfaces of solder joint failures in bend test samples differed significantly from thermal cycle test samples.     

Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology

As the industry keeps moving towards further miniaturization of electronic devices, even smaller sizes, a lower economical cost, and higher reliability are not only convenient but have become a necessity of the design. A well-designed package structure can effectively restrain the solder joint fatigue failure induced by material coefficient of thermal expansion (CTE) mismatch. Wafer level chip scaling package (WLCSP) has a high potential for future advanced packaging. However, the solder joint reliability for large chip sizes of up to 100 mm² without underfill is still an issue that needs to be resolved. For solving this problem, a double-layer WLCSP (DL-WLCSP) with both a stress compliant layer and dummy solder joints is proposed in this research to enhance the solder joint fatigue life. Moreover, a hybrid method is employed to predict the profile of solder joint after reflow process. To ensure the correctness of the methodology of the analysis, a Rambus DRAM layout is implemented as the test vehicle to demonstrate the applicability and reliability of the DL-WLCSP. The results of the thermal cycling experimental test show good agreement with the simulated analysis. In addition, besides the geometrical design parameters of the silicon die thickness and the thickness of the stress compliant layer, the reliability impact for the arrangement of die-side and substrate-side pad diameter is investigated by means of the design of experiment (DOE). In addition, the Response Surface Methodology (RSM) with central composite designs (CCD) is adopted to obtain the parameter sensitivity information by the three-dimensional nonlinear finite element analysis (FEA). Analysis of variance (ANOVA) is conducted to determine the significance of the fitted regression model. The analytic results reveal that the stress compliant layer and the dummy joints can effectively reduce the stress concentration phenomenon, which occurs around the outer-corner of the solder joint. The smaller thermal strains can be controlled through better size combination between die-side and substrate-side pad diameter.     

Tri-Layer Structures Subjected to Combined Temperature and Mechanical Loadings

Thermal stress has been a concern in electronic packaging for decades. More recently, mechanical bending of printed circuit board (PCB) assembly has attracted increased interest due to the drop impact failure of interconnects in mobile products. Analytical solutions are available in the literatures for a PCB assembly modeled as a tri-layer structure, consisting of IC components, PCBs, and an interconnect layer, subjected to either thermal stress or mechanical bending, but there are no known reports for combined loadings. This paper presents a comprehensive treatment for a PCB assembly subjected to combined temperature and mechanical loadings, taking into account the axial, shear, and flexural deformation of the interconnects. Solutions are provided for two types of interconnect layer: one in which the interconnect layer is made of a continuous element such as adhesive, and another in which the interconnect layer is made of discrete elements such as solder joints. The solutions were successfully validated with finite-element analysis, and design analyses were performed for both types of interconnect layers.      

LCCC封装器件热疲劳失效分析及结构优化研究

针对LCCC封装器件在温度循环载荷下焊点开裂的问题,首先分析其失效现象和机理,并建立有限元模型,进行失效应力仿真模拟。为降低焊点由封装材料CTE不匹配引起的热应力,提出了两种印制板应力释放方案,并分析研究单孔方案中不同孔径和阵列孔方案中不同孔数量对热疲劳寿命的影响。之后,为降低对PCB布局密度的影响,提出一种新型的叠层焊柱应力缓冲方案,进行了不同叠层板厚度和焊柱间距的敏感度分析。结果表明,更大的开孔面积、更小的叠层板厚度、更密的焊柱可有效降低焊点应力,提高焊点热疲劳寿命,使得LCCC封装器件焊点热疲劳可靠性得到有效提高。     

Thermal-Mechanical Process Simulation of an Advanced NCF Technology

The paper introduces an advanced nonconductive film (NCF) typed FC technology employing a novel compliant composite interconnect structure. The interconnect reliability and bondability of the technology are demonstrated through experimental thermal humidity (TH) test in conjunction with a two-point daisy chain resistance measurement. The alternative goal of the study aims to look into the insight of the thermal-mechanical behaviors of the novel packaging technology during NCF bonding process and thermal testing through numerical modeling and experimental validation. For effectively simulating the bonding process, a process-dependent finite-element (FE) simulation methodology is performed. The validity of the proposed methodology is verified through several experimental methods, including a Twyman-Green (T/G) interferometry technique for warpage measurement, and a four-point probe method for contact resistance measurement. At last, a design guideline for improved process-induced thermal-mechanical behaviors is presented through parametric FE analysis. Both numerical and experimental results demonstrate the feasibility in applying the novel compliant interconnects to achieve a proper contact stress at various temperature environments so as to hold a low and stable connection resistance at elevated temperature. Most importantly, the novel interconnects survive the 85degC/85%RH TH test for 500 hours.     

Thermal cycling analysis of flip-chip solder joint reliability

The reliability concern in flip-chip-on-board (FCOB) technology is the high thermal mismatch deformation between the silicon die and the printed circuit board that results in large solder joint stresses and strains causing fatigue failure. Accelerated thermal cycling (ATC) test is one of the reliability tests performed to evaluate the fatigue strength of the solder interconnects. Finite element analysis (FEA) was employed to simulate thermal cycling loading for solder joint reliability in electronic assemblies. This study investigates different methods of implementing thermal cycling analysis, namely using the "dwell creep" and "full creep" methods based on a phenomenological approach to modeling time independent plastic and time dependent creep deformations. There are significant differences between the "dwell creep" and "full creep" analysis results for the flip chip solder joint strain responses and the predicted fatigue life. Comparison was made with a rate dependent viscoplastic analysis approach. Investigations on thermal cycling analysis of the temperature range, (ΔT) effects on the predicted fatigue lives of solder joints are reported     

Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging

This paper presents modeling and simulation results of a modified copper-column-based flip-chip interconnect with ultrafine pitch for wafer-level packaging, and the process and prototyping procedure are described as well. This interconnect consists of multiple copper columns which are electrically in parallel and supporting a solder bump. A simple analytical model has been developed for correlation between the interconnect geometry and the thermal fatigue life. In comparison to the conventional single-copper-column (SCC) interconnects, numerical analysis reveals that the multi-copper-column (MCC) interconnect features enhanced compliances and, hence, higher thermomechanical reliability, while the associated electrical parasitics (R, L, and C) at dc and moderate frequencies are still kept low. Parametric studies reveal the effects of geometric parameters of MCC interconnects on both compliances and electrical parasitics, which in turn facilitate design optimization for best performance. By using coplanar waveguides (CPWs) as feed lines on both chip and package substrate, a high-frequency (up to 40 GHz) S-parameter analysis is conducted to investigate the transmission characteristics of the MCC interconnects within various scenarios which combines various interconnect pitches and common chip and package substrates. An equivalent lumped circuit model is proposed and the circuit parameters (R, L, C, and G) are obtained throughout a broad frequency range. Good agreement is achieved for the transmission characteristics between the equivalent lumped circuit model and direct simulation results.     

High-Reliability Low-Ag-Content Sn-Ag-Cu Solder Joints for Electronics Applications

Sn-Ag-Cu (SAC) alloy is currently recognized as the standard lead-free solder alloy for packaging of interconnects in the electronics industry, and high- Ag-content SAC alloys are the most popular choice. However, this choice has been encumbered by the fragility of the solder joints that has been observed in drop testing as well as the high cost of the Ag itself. Therefore, low-Ag-content SAC alloy was considered as a solution for both issues. However, this approach may compromise the thermal-cycling performance of the solders. Therefore, to enhance the thermal-cycling reliability of low-Ag-content SAC alloys without sacrificing their drop-impact performance, alloying elements such as Mn, Ce, Ti, Bi, In, Sb, Ni, Zn, Al, Fe, and Co were selected as additions to these alloys. However, research reports related to these modified SAC alloys are limited. To address this paucity, the present study reviews the effect of these minor alloying elements on the solder joint reliability of low-Ag-content SAC alloys in terms of thermal cycling and drop impact. Addition of Mn, Ce, Bi, and Ni to low-Ag-content SAC solder effectively improves the thermal-cycling reliability of joints without sacrificing the drop-impact performance. Taking into consideration the improvement in the bulk alloy microstructure and mechanical properties, wetting properties, and growth suppression of the interface intermetallic compound (IMC) layers, addition of Ti, In, Sb, Zn, Al, Fe, and Co to low-Ag-content SAC solder has the potential to improve the thermal-cycling reliability of joints without sacrificing the drop-impact performance. Consequently, further investigations of both thermal-cycling and drop reliability of these modified solder joints must be carried out in future work.     

Shock impact reliability characterization of a handheld product in accelerated tests and use environment

The effect of mechanical shock impacts is a key factor in the reliability of modern handheld products. Due to differences in product enclosures, impact orientations, strike surfaces and mountings of component boards, the loading conditions induced in a true product drop differ from those encountered in standardized board-level tests. In order to better understand the correlation between board-level drop testing and actual drops of a complete device, series of board and product-level drop tests were conducted using specialized test boards.The mechanical shock impact response of the commercial handheld device component board was characterized with the help of acoustic excitation laser vibrometry and finite element analysis. The results were used to design the mechanically compatible specialized test board for both 4-point supported board-level and unsupported product-level drop tests. Special care was taken to ensure that the vibration behavior of the test board accurately represented the vibration behavior of the commercial component board. Additional board-level drop tests were conducted using a JEDEC JESD22-B111 compliant component board for comparison.The drop test results showed that, even though the test board design and supporting method have a marked influence on the strain conditions and lifetime of solder interconnections, the primary failure mode and mechanism under the product-level drop tests is comparable to that typically encountered in the standard JEDEC JESD22-B111 board-level drop tests. More detailed analyses suggest that the comparability of the shock impact loading conditions affecting solder interconnections can be characterized using three metrics: (1) the maximum component board strain rate, (2) the maximum board strain amplitude and (3) the damping of the component board.     

Vibration fatigue experiments of SMT solder joint

The low-cycle fatigue induced by thermal cycling is the major concern in the reliability of SMT for electronic packaging; however, dynamic loading effects on solder joint fatigue life have not been thoroughly investigated. In fact, the high-cycling fatigue induced by vibration can also contribute a significant effect. In certain circumstances it can become a dominant failure case when semiconductor devices are used in vibration environment. In this paper, a series of vibration fatigue experimental vehicles including PBGA256 assembly and FCBGA1521 assembly were conducted. After these experiments, a new phenomenon of cracks of solder joints have been detected and given a reasonable reason, which could lead to a new concept of solder joints' fatigue.     

Experimental analysis of Sn-3.0Ag-0.5Cu solder joint board-level drop/vibration impact failure models after thermal/isothermal cycling

Sn-3.0Ag-0.5Cu board-level lead-free solder joint drop (1000g, 1 ms)/vibration (15g, 25–35 Hz) reliability after thermal (− 40–125 °C, 1000 cycle)/isothermal (150 °C, 500 h) cycling was reported in this study. The failure performance of solder joint and testing life were analyzed under design six testing conditions (1. Single drop impact, 2. Order thermal cycling and drop impact, 3. Order isothermal cycling and drop impact, 4. Single vibration 5. Order thermal cycling and vibration 6. Order isothermal cycling and vibration). The results revealed that the pre-cracks initiation during thermal cycling do not affect the solder joint drop impact reliability, but decrease the vibration reliability. The formation of voids weaken both drop and vibration reliability of solder joint. After thermal cycling, the crack initiated from β-Sn near IMC layer, and continued propagation through the same path when under second in order vibration impact. But propagation path turn to IMC layer when under second in order drop impact. The drop life increases from 41 times to 49 times, and vibration life decrease from 77 min to 45 min. After isothermal cycling, the formation of voids let the cracks occurred at IMC layer under second in order no matter drop impact or vibration. The drop and vibration life is 19 times and 62 min respectively.     

Design and Control of a Piezoelectric Driven Fatigue Testing System for Electronic Packaging Applications

Failure of solder joints for electronic packaging is an important issue for controlling the reliability of semiconductor devices. However, the complicated coupling between mechanical stressing and temperature and time dependent material properties makes it difficult to explore the fundamental failure control mechanisms using the existing accelerated thermal cycling methods. In addition, the testing speed is also severely restricted by the thermal time constant of the characterization system. In order to decouple the mechanical stress effect from other factors as the first step toward exploring the control mechanisms of failure, a piezoelectric-based fatigue characterization system is developed to replace the thermal cycling and provide fast and purely mechanical stressing cycles. A self-tuning based (STR) adaptive controller is also developed to provide accurate process control during experiments for compensating stiffness variation due to fatigue crack growth. It is found that this STR regulator is more robust than the traditional PID controller. The bandwidth of the system is approximately 70 Hz and is currently restricted by the equivalent time constant of the piezoelectric material. Nevertheless, this speed is sufficient for conducting a successful fatigue testing of solder joints. Finally, preliminary fatigue experiments have been performed on Sn₆₃Pb ₃₇ solders and the reduction of stiffness due to crack growth is clearly visible while the actuation performance is consistent and stable during the entire testing period. In the future, it is possible to operate in conjunction with a temperature control unit and a creep testing scheme to explore both the temperature and time dependent nature of solders in order to fully understand the failure control mechanisms of packaging     

倒装芯片焊点可靠性的有限元模拟法综述

随着集成电路封装技术的发展,倒装芯片技术得到广泛的应用。由于材料的热膨胀失配,使倒装焊点成为芯片封装中失效率最高的部位,而利用快捷又极具参考价值的有限元模拟法是研究焊点可靠性的重要手段之一。介绍了集成电路芯片焊点可靠性分析的有限元模拟法,概括了利用该方法对芯片焊点进行可靠性评价常见的材料性质和疲劳寿命预测模型。     

Design optimization of one-turn helix: a novel compliant off-chip interconnect

As the rapid advances in integrated circuit (IC) design and fabrication continue to challenge and push the electronic packaging technology, in terms of fine pitch, high performance, low cost, and good reliability, compliant interconnects show great potential for next-generation packaging. One-turn helix (OTH) interconnect, a compliant chip-to-next level substrate or off-chip interconnect, is proposed in this work, and this interconnect can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The interconnect has high mechanical compliance in the three orthogonal directions, and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and an organic substrate. The fabrication of the helix interconnect is similar to the standard IC fabrication, and the wafer-level packaging makes it cost effective. In this paper, we report the fabrication of an area array of helix interconnects on a silicon wafer. Also, we have studied the effect of interconnect geometry parameters on its mechanical compliance and electrical parasitics. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed for the design of OTH interconnect. An optimization technique using response surface methodology has been applied to select the optimal structure parameters. The optimal compliant OTH interconnect will have a total standoff height of about 100 /spl mu/m, a radius of about 35 /spl mu/m and a cross section area of about 430 /spl mu/m/sup 2/.     

Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput