Effects of substrate design on underfill voiding using the low cost, high throughput flip chip assembly process and no-flow underfill materials

The formation of underfill voids is an area of concern in the low cost, high throughput, or "no-flow" flip chip assembly process. This assembly process involves placement of a flip chip device directly onto the substrate pad site covered with pre-dispensed no-flow underfill. The forced motion of chip placement causes a convex flow front to pass over pad and solder mask-opening features promoting void capture. This paper determines the effects of substrate design on the phenomena of underfill voiding using the no-flow process. A full-factorial design experiment analyzes several empirically determined factors that can affect void capture in no-flow processing. The substrate design parameters included pad height, solder mask opening height, pad/solder mask opening separation, and pad pitch. The process parameters include chip placement velocity and underfill viscosity. The process robustness is measured in terms of the number of voids created during chip placement, and is further analyzed for the location and any visible modes of void formation. The goal of the work is to determine improved substrate designs to minimize voiding in flip chip processing using no flow underfills.     

Comparative studies on solder joint reliability of CTBGA assemblies with various adhesives using the array-based package shear test

This paper discusses the influences of various adhesives on board-level shear strength of ChipArray® Thin Core Ball Grid Array (CTBGA) assemblies through an innovative reliability evaluation approach, i.e. array-based package (ABP) shear test. It is found that the adhesives do enhance the shear strength for all the test categories as compared with the assemblies without adhesives (w/o A), but the degree of improvements between different strategies vary quiet a lot. The specific shear strength is affected by a number of factors, in which dispending patterns and material properties of the adhesives used influences it obviously. In general, the adhesives with high storage modulus and large dispensing volume are preferred, for example, stiff full or partial capillary flow underfills. In order to further understand the failure mechanism of the CTBGA during the ABP shear test, failure analysis on tested devices are also conducted using side view optical microscopy, scanning electron microscope (SEM) and energy dispersive X-ray (EDX), the results indicate that the predominant failure mode changes from PCB pad lift/cratering to fracture at package side intermetallic compound (IMC)/solder interface with increasing dispensing volume and storage modulus, which basically improves the solder joint reliability of CTBGA assemblies.     

An analysis of the reliability and design optimization of aluminium ribbon bonds in power electronics modules using computer simulation method

Ribbon bonding technique has recently been used as an alternative to wire bonding in order to improve the reliability, performance and reduce cost of power modules. In this work, the reliability of aluminium and copper ribbon bonds for an Insulated Gate Bipolar Transistors (IGBT) power module under power cycling is compared with that of wire bonds under power and thermal cycling loading conditions. The results show that a single ribbon with a cross section of 2000 μm × 200 μm can be used to replace three wire bonds of 400 μm in diameter to achieve similar module temperature distribution under the same power loading and ribbon bonds have longer lifetime than wire bonds under cyclic power and thermal cycling conditions. In order to find the optimal ribbon bond design for both power cycling and thermal cycling conditions, multi-objective optimization method has been used and the Pareto optimal solutions have been obtained for trade off analysis.     

Static and transient latchup simulation of VLSI-CMOS with an improved physical design model

We are presenting an improved latchup design model for static and transient latchup simulation of VLSI CMOS devices. The model is based on a decomposition of the CMOS structure into a network of analytically described current elements for both majority and minority carriers. Average doping densities and geometrical parameters are the physically based input data. For the modeling of the 2-D majority-carrier flow, transmission-line elements are introduced, especially in the inhomogeneously doped transition region between the substrate and an epitaxial layer. For modeling the transient current behavior, diffusion and space-charge capacitances are used. The model yields very good agreement with measurements both for static and transient triggering modes. Due to the physically reasonable assumptions used in the model equations, the influence of design variations on latchup characteristics can be predicted adequately without new parameter fitting.     

Influence of interfacial reaction layer on reliability of chip-scale package joint from using Sn-37Pb and Sn-8Zn-3Bi solder

The microstructure of Sn-37Pb and Sn-8Zn-3Bi solders and the full strength of these solders with an Au/Ni/Cu pad under isothermal aging conditions were investigated. The full strengths tended to decrease as the aging temperature and time increased, regardless of the properties of the solders. The Sn-8Zn-3Bi had higher full strength than Sn-37Pb. In the Sn-37Pb solder, Ni₃Sn₄ compounds and irregular-shaped Pb-rich phase were embedded in a β-Sn matrix. The Ni₃Sn₄ compounds were observed at the interface between the solder and pad. The microstructure of the as-reflowed Sn-8Zn-3Bi solder mainly consists of the β-Sn matrix scattered with Zn-rich phase. Zinc first reacted with Au and then was transformed to the AuZn compound. With aging, Ni₅Zn₂₁ compounds were formed at the Ni layer. Finally, a Ni₅Zn₂₁ phase, divided into three layers, was formed with column-shaped grains, and the thicknesses of the layers were changed.     

Modeling the effect of barrier thickness and low-k dielectric on circuit reliability using 3D model

The continuous scaling down of the device size and escalating circuit speed drives the requirement for EM-resistant Cu interconnect with diffusion barrier and the low-k dielectric. The study of barrier layer thickness and low-k dielectric effect in a complete 3D circuit is necessary as the actual physical implementation of an integrated circuit in a wafer is indeed 3D in nature. This paper investigates the effect of barrier layer thickness and low-k dielectric on the circuit reliability of a complete 3D circuit model. It was found that the maximum atomic flux divergence (AFD) value increases with decreasing barrier layer thickness, which implied a shorter EM lifetime with thinner barrier. Low-k dielectric will give a higher maximum AFD due to higher stress gradient, and thus a shorter EM lifetime.     

Evaluation of the impact of the physical dimensions and material of the semiconductor chip on the reliability of Sn3.5Ag solder interconnect in power electronic module: A finite element analysis perspective

This paper primarily focuses on an evaluation study for the temperature cycling capability of tin silver solder interconnect in power electronic applications by the impact of die dimensions and die material properties. The study was investigated on finite element analysis perspective on chip/solder/substrate structure. A commercially available chip was chosen in the finite element analysis (FEA) as the nominal base die. Two thermal cycle profiles were utilised. The effect of die area, die thickness and material properties (Si and SiC) on the thermal cycling capability of the solder layer was investigated from FEA perspective. From the FEA, it was concluded that decrease in die thickness resulting in increment of thermal cycling capability of solder layer for both material (Si and SiC). Increase in die area increases the thermal cycling capability of solder. For higher ΔT thermal cycle, solder under SiC die perform better than solder under Si die in terms of thermal cycling capability. When the die thickness become smaller than a threshold value of the thermal cycle regime, solder under Si die have better thermal cycling capability than solder under SiC die. Additionally a parametric study was undertaken for a SiC chip/substrate structure under high ∆ T temperature cycling profile for solder layer geometric parameter (wetting angle, titling angle and thickness). From the parametric study which utilised design of experiments (DoE), a wavelet radial basis surrogate model was generated. A sensitivity analysis was performed on surrogate model in order to identify the most influencing parameter. From the sensitivity analysis, it was concluded that wetting angle and solder layer thickness of solder layer have significant impact on the thermal cycling capability of the solder layer.