MOS Integrated Circuit Reliability

This paper presents information on the reliability of MOS integrated circuits based on p-channel enhancement-mode transistors, and describes their failure modes and mechanisms. The principal failure mechanisms were ion migration at the surface and oxide shorting. The results of experimental studies of the effects of variations in construction, processing, and levels of stress are presented, and are compared with other available information on MOS integrated circuit reliability. The failure rate for commercially available complex MOS arrays is on the order of 0.001 to 0.01 per 1000 h of operating life at 125°C for arrays containing approximately 600 p-channel transistors. This corresponds to a failure rate on the order of 5 × 10?6 to 5 × 10?5 per equivalent gate per 1000 h. The effects of device complexity, operating temperature, and other factors are discussed. A reliability prediction equation for MOS integrated circuits is derived from available information. An overall activation energy for functional failure mechanisms of approximately 5 kcal/mole (?0.2 eV/molecule) is considered applicable to typical MOS integrated circuits. Thus, the failure rate of MOS devices operated at 50°C ambient temperature can be predicted to be on the order of 10?6 to 10?5 per equivalent gate per 1000 h.     

铁氧体驱动与双路功率MOS单片集成电路研究

介绍了一种集成低压铁氧体驱动器和功率MOS管的单片集成电路。其内建驱动器工作电压9 V,功率MOS管极限电压大于80 V,工作电流3 A。该电路内含D/A转换器、双路比较器、触发器和组合逻辑电路,以及过频过压保护等功能,采用键合SOI深槽的CMOS/LDMOS工艺制作。     

A monolithic 200-V CMOS analog switch

A new high-voltage CMOS technology is described which can increase the operating voltage of these circuits to more than 200 V. This represents approximately an order of magnitude improvement over present-day commercially available CMOS devices. The technology is straightforward to implement and uses n-channel MOS transistors and high-voltage p-channel devices. As an example of the capability of the technology, a monolithic quad CMOS analog switch has been fabricated which can handle 200-V, 0.3-A analog signals, with a dynamic range in excess of 150 dB.     

Mixed body bias techniques with fixed V/sub t/ and I/sub ds/ generation circuits

There remains a need to improve sub-1-V CMOS VLSIs with respect to variation in transistor behavior. In this paper, to minimize variation in delay and the noise margin of the circuits in processors, we propose several mixed body bias techniques using body bias generation circuits. In these circuits, either the saturation region of the current between source and drain (I/sub ds/) or the threshold voltage (V/sub t/) of PMOS/NMOS is permanently fixed, regardless of temperature range or variation in process. A test chip that featured these body bias generation circuits was fabricated using a 130-nm CMOS process with a triple-well structure. The mixed body bias techniques which keep the I/sub ds/ of the MOS in the decoder and I/O circuits of a register file fixed and maintain the V/sub t/ of the MOS in both the memory cell and domino circuits of the register file fixed resulted in positive temperature dependence of delay from -40 /spl deg/C to 125 /spl deg/C, 85% reduction of the delay variation compared with normal body bias (NBB) at V/sub DD/ = 0.8 V. In addition, the results using these techniques show a 100-mV improvement in lower operating voltage compared with NBB at -40 /spl deg/C on a 4-kb SRAM.     

Reliability evaluation of plastic packaged devices for long life applications by THB test

The reliability of transistors, bipolar and CMOS integrated circuits encapsulated in different types of plastic packages was investigated by using the 85°C/85% R.H. test with applied bias and the results compared with a long term operating life test. Particular attention was devoted to pointing out the influence of technology, process control and working conditions on device reliability and failure mechanisms.In micropackaged transistors the importance of surface passivation in protecting the devices against gold corrosion was forcused, while the need of good process control was confirmed by the results of the test on micropackaged linear integrated circuits.In dual-in-line CMOS integrated circuits silicon nitride and polymide give, in general, a superior protection, but good results were obtained also with normal P-glass passivation when a clever arrangement of layout design rules was adopted. Results obtained exhibit a significant improvement in the reliability of plastic packaged devices, with the best figures showing no failures after 15,000 hours at 85°C/85% R.H. test with bias.     

Quality assurance system and reliability testing of LSI circuits

The development of LSI circuits as well as their quality and reliability assurance in the current production require, due to the specified high quality levels, a precisely defined Quality Assurance System. Such a System was presented in the first two Sections.For the predictions of field failure rate generally the time-temperature acceleration in accordance with the Arrhenius model has to be applied. Field reliability at lower operating temperatures has to be determined from the results and defectives of sampling life-tests at elevated temperatures. Obviously for LSI circuits the time-temperature acceleration depends very strongly on different failure mechanisms involved. For this reason an efficient and correct failure rate prediction can only be performed, if the failure mechanisms in the defective chips are exactly known and classified.     

A Reliability Evaluation of Plastic Packaged Semiconductor Components

Qualification testing programs have been developed for assessing the reliability of commercial grade discrete semiconductors for use in office business machines. These programs include accelerated stresses of high temperature storage (HTS) and high temperature reverse bias (HTRB) for 1000 hours, and a sequence test of thermal cycle and thermal shock followed by storage at 85°C and 85% RH (85/85) for 1000 hours. Both hermetic and plastic encapsulated parts have been tested more than 15 million part hours. HTRB and 85/85 are about twice as effective as HTS in identifying potentially unreliable parts. Plastic packaged semiconductors are inherently capable of withstanding 85/85 for 1000 hours without parameter degradation. The value of qualification testing against the 85/85 environment is demonstrated by the observed correlation of machine failure rates in the field with the relative humidity in the use environment. The observed failure rate of plastic parts is not more than 3.2 times that of hermetic parts. Plastic parts are capable of reliable operation, but the marked differences in reliability between different vendors and between different part types from the same vendor require increased process and materials control in order to achieve the potential of which plastic parts are capable.     

Trimming analog circuits using floating-gate analog MOS memory

A floating-gate MOS analog memory circuit that can be electrically programmed for positive and negative voltage changes and that can be fabricated in a standard CMOS IC process is described. Unlike existing electrically erasable floating-gate memory circuits, this circuit does not require special fabrication techniques like ultrathin tunneling oxides or textured polysilicon. Instead, mask geometry is used to cause field-enhanced Fowler-Nordheim tunneling of electrons from a floating gate. Retention measurements at elevated temperatures indicate that the loss of floating-gate charge should be less than 0.1% over a ten-year period at temperatures below 100°C. One limitation of this structure is that the rate of change of the floating-gate voltage can be quite small (e.g. 10 mV/s). A general trimming circuits, whose novel feature is that any number of trimming circuits can be independently and simultaneously adjusted across an entire IC, has been incorporated into a prototype CMOS op amp to decrease its input offset voltage from 10 mV to less than 0.5 mV     

Process integration and device performance of a submicrometerBiCMOS with 16-GHz ft double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n⁺ buried layer, and n-channel MOSFETs were built in a p-well on a p⁺ buried layer. Deep trenches with depths of 4 μm and widths of 1 μm isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C_L=0 pF and 300 ps for C_L=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 μm were maintained at almost the same ratio     

微纳米CMOS VLSI电路可靠性仿真与设计

介绍了CMOS VLSI的可靠性建模和仿真技术的发展历史、相应的仿真工具、失效机理等效电路和算法,重点总结了当前最新的CMOS超大规模集成电路可靠性建模仿真技术,为促进我国集成电路可靠性设计水平起到积极的作用。     

一种CMOS IC片上电源ESD保护电路

随着集成电路工艺的高速发展,特征尺寸越来越小,静电放电对CMOS器件可靠性的危害也日益增大,ESD保护电路设计已经成为IC设计中的一个重要部分.讨论了两种常见的CMOS集成电路电源系统ESD保护电路,分析了它们的电路结构、工作原理和存在的问题,进而提出了一种改进的电源动态侦测ESD保护电路.使用HSPICE仿真验证了该电路工作的正确性,并且在一款自主芯片中使用,ESD测试通过士3000 V.     

All-pass filter for rich cascadability options easy IC implementation and tunability

This paper presents two current-mode all-pass sections, employing only grounded components, which is important from the integrated circuit (IC) implementation point of view. The use of the grounded capacitor allows the IC implementation with standard CMOS technologies. The circuits can be made electronically tunable due to grounded resistors that can be realized by using voltage controlled MOS based resistors. In addition, the circuits have both low input impedance and high output impedance for easy cascadability. The stability analysis proves that the circuits are stable. SPICE simulations and experimental results are in close agreement with the theory.     

VMOS reliability

Whenever a new technology such as VMOS emerges, one key element to its success is the reliability of the products manufactured in that technology. The results of a reliability study to examine the fundamental VMOS device stability, high-temperature operating life (HTOL) failure rates, and electrostatic protection are presented for the VMOS technology. Experimental data for more than five (5) million device-hours of HTOL predict a reliability failure rate of less than 0.01 percent/1000 h at 70°C for products fabricated in the VMOS technology. In addition, an electrostatic protection capability greater than 1800 V is possible with specially designed VMOS input protection devices.     

A 70 ns high density 64K CMOS dynamic RAM

A 64K /spl times/ 1 CMOS dynamic RAM has been developed in a double-poly n-well CMOS technology with device scaling to the HMOS III level. A p-channel memory array with n-well protection reduced the operating soft error rate to less than one FIT. Periphery complexity is simplified due to CMOS circuits resulting in a size of 30,464 mil/SUP 2/ with a redundancy efficiency of 68%. The RAM has a typical access time of 70 ns and a CMOS standby power of 25 /spl mu/W. In addition, a static column design offers 35-ns data cycle time for high-bandwidth application.     

Integrated-circuit digital logic families III?ECL and MOS devices

This final installment of a three-part article is devoted to emitter-coupled logic (ECL) devices as well as to metal oxide semiconductor (MOS) logic devices of the p-channel (P-MOS) and complementary (CMOS) types. The concluding portion presents a summary chart comparing the major parameters of the various IC digital families discussed in the three installments, plus a useful check list of available functions.     

A GHz MOS adaptive pipeline technique using MOS current-mode logic

This paper describes an adaptive pipeline (APL) technique, which is a new pipeline scheme capable of compensating for device-parameter deviations and for operating-environment variations. This technique can also compensate for clock skew and eliminate excessive power dissipation in current-mode logic (CML) circuits. The APL technique is here applied to a 0.4-μm MOS 1.6-V 1-GHz 64-bit double-stage pipeline adder, and this paper shows that the adder can operate accurately on condition that the clock has 20% skew. The APL technique uses MOS current-mode logic (MCML) circuits, whose propagation delay time can be varied by the control ports. MCML circuits can operate with lower signal voltage swing and higher operating frequency at lower supply voltage than CMOS circuits can. This paper also shows that MCML circuits are suitable for a low-noise variable delay circuit. Measurement results show that jitter of MCML circuits is about 65% that of CMOS circuits     

CMOS integrated circuit reliability

This paper summarizes recently published data on CMOS integrated circuit failure rates, and provides information on the effects of voltage, temperature, device complexity, and packaging on CMOS failure rates. Other factors which can affect failure rate are also indicated, including designs, materials, processes, in-process controls, screening tests, and product maturity. Data on failure rates of NMOS and PMOS integrated circuits are provided to enable comparison with CMOS data. It is concluded that available data do not indicate any consistent reliability difference for CMOS versus NMOS or PMOS integrated circuits. Because of the many advantages of CMOS integrated circuit technology, continued increase in usage of CMOS circuits has been forecast, accompanied by further increases in CMOS integrated circuit reliability.     

Failure in CMOS circuits induced by hot carriers in multi-gatetransistors

The problem of vertical isolation in circuits fabricated using shallow n-well epitaxial CMOS technology is analyzed. Unexpectedly high substrate current resulting in circuit failure has been observed during accelerated reliability tests. The substrate current is a result of enhanced hole injection from multi-gate p-channel transistors with interdigitated source and drain. The electron current generated from impact ionization near the drain forward biases the source junctions, causing hole injection to the substrate. The current is sensitive to the supply voltage and temperature. Consequently, unanticipated failures may occur at the high voltages and temperatures encountered during burn-in. Design and process solutions are discussed     

Impact of anomalous short-channel MOS transistors on VLSI circuit reliability

In VLSI and ULSI circuits, a major reliability concern is that completed, fully functional, in-specification integrated circuits may contain one or more anomalous transistors with substantially closer source-to-drain spacing than the minimum-design-rule devices, and that such transistors will be more susceptible to degradation or failure due to hot-carrier effects, total-dose-radiation effects or other instabilities. A further concern is that such vulnerable transistors will not be detected during conventional electrical testing or during typical high-reliability integrated circuit burn-in procedures such as static or dynamic burn-in at 125°C, since hot carrier effects tend to anneal out at elevated temperatures, as well as having a negative temperature acceleration factor.Experimental studies have shown that fully functional nMOS transistors with shorter-than-normal channel lengths can have many orders of magnitude greater susceptibility to hot-electron-induced threshold voltage shifts, compared to transistors with minimum-design-rule dimensions of 1.2μm. Total-dose radiation tests showed that anomalous n-channel MOS transistors can have orders-of magnitude higher post-total-dose radiation leakage than nominal devices made by the same process.Several possible types of screening techniques that can be considered for detecting integrated circuits containing anomalous transistors are discussed, including a low-dissipation dynamic stress test at room temperature or at −55°C, with parts electrically characterized before and after the stress test. A large change (delta) of certain critical parameters would be used to predict future failure. Quiescent CMOS supply-current testing could also be used to detect the presence of anomalous transistors in some types of integrated circuits.     

Aging Effects in Gold Thermocompression Bonds to Complex Metallizations

The times to failure of Au thermocompression bonds to Au-Mo-Al and to Au-Ti-Al multilayer films were determined as a function of temperature over the range of 125-400°C and compared with the time to failure of gold bonds to aluminum films. A 500-? Ti intermediate film was found to be ineffective as a barrier to reaction between gold and aluminum. On the other hand, a 500-? Mo film was effective, providing increased time to failure over that observed for bonds to Au-Ti-Al and Al films. No failures were observed after 2000 hours at 400°C when gold wire bonds were made to an Au/Mo/Al metallization having 1000 ? of molybdenum as the intermediate layer.