Linking simulation with formal verification at a higher level

We use simulation to bridge the gap between specification and formal verification of high-level models and simulation of RTL models. The authors apply their practical, two-phase procedure for defining the refinement map to the Alpha 21364 multiprocessing hardware. The methodology and tools they present can improve simulation coverage. Our technique verifies that a hardware design described at the RTL is a correct implementation of an algorithm-level, executable formal specification. We use a high-level formal specification as the basis for monitoring functional correctness, measuring simulation coverage, and generating test cases.     

基于软件模拟的SoC功能验证技术研究进展

软件模拟验证在SoC设计中得到了广泛的研究和应用,是目前SoC功能验证的主要方法.文中从高度抽象化、可重用和自动化三个方面梳理和综述了基于软件模拟的SoC功能验证技术的研究进展.同时,基于断言的验证在SoC的功能验证技术中起到重要的辅助性作用,文中阐述了断言技术的研究进展.最后,对软件模拟验证技术的发展趋势进行了展望.     

Enhanced equivalence checking: toward a solidarity of functional verification and manufacturing test generation

This article, from the Motorola (now Freescale) PowerPC design group, presents an interesting synergy among test, equivalence verification, and constraints. The authors use RTL, gate, and switch models of a design in two different flows one for test and one for functional verification to show that rectifying constraints and merging tests between the-two flows saves significant presilicon debug effort.     

通用CPU设计验证中的等价性检验方法

针对传统的模拟验证方法需要大量的时间且难以获得完全的覆盖率的局限性,提出了目前应用最广泛的一种形式验证方法——等价性检验在一款通用CPU设计验证中的应用方案,包括寄存器传输级(RTL)设计与门级网表、门级网表与门级网表、RTL设计与RTL设计之间的功能等价性验证．此外,给出了验证过程中一些常见问题的解决办法．验证结果表明了该方法的可行性,显著地减少了门级模拟的时间．     

AMBA片内总线结构的设计

对AMBA片内总线通讯协议进行简要介绍之后，采用Top-Down设计方法完成了AMBA片内总线结构所有控制部件的RTL级硬件建模，并通过逻辑综合、优化得到了门级电路网表。经验证，符合AMBA规范，频率达100MHz。     

A layered adaptive verification platform for simulation, test, and emulation

This adaptive architecture for structuring testbenches accommodates various models of a design, from transaction to silicon. Moreover, the adapter-based architecture supports the execution of design models on different simulators (high level, RTL, gate level, and switch level), hardware emulators (the testbench runs entirely on the emulator), and even testers. Here, we present a modular, layered testbench (MLTB) approach to building a testbench. This approach is similar to platform-based design. It consists of a generic testbench kernel (TBK), connected through a bus to testbench elements. Our verification platform also satisfies another meaning of platform: a set of connected tools or a powerful tool environment, normally with an attached database, that acts as a platform for verification.     

Applied Boolean equivalence verification and RTL static sign-off

The author explores applying formal Boolean equivalence verification to the RTL design flow, and introduces an effective equivalence-checking usage model that ensures optimal benefits in an RTL static sign-off methodology     

A novel formal verification approach for RTL hardware IP cores

We present a promising formal verification methodology based on the inductive approach using the imPROVE-HDL tool. This methodology is dedicated for RTL IPs or IP-based digital/logic hardware designs to prove the correctness of their temporal properties related to the control-dominated architecture model. Each temporal property can be checked through the IP interface where all properties have to be proved or disproved. We developed a new methodology to generate the appropriate environment of the IP interface according to the design context (master, slave, arbiter and decoder) before starting the verification of all properties one by one. When all temporal properties are verified, we generate some test sequences that contain a complex scenario to check the compatibility between all properties. We implemented our methodology to generate the appropriate environment and applied the inductive approach to verify various properties of two real IP designs using the imPROVE-HDL tool developed by TNI-Valiosys. The first design is an RTL IP-based digital hardware dedicated for real time video processing, where the second one performs an AHB to AHB Bridge. On these designs, we successfully proved few properties and discovered a design violation.     

事务级形式验证技术及8051验证模型

提出一种基于事务的用于电路系统的形式验证方法(TBFV)．应用该方法，验证工程师可以在行为级对系统进行验证，无需了解设计的细节．为了对该方法进行示范，验证了8051的RTL级实现，并给出了8051指令集的TBFV模型．     

用于RTL设计验证的静态错误检测方法

为快速有效地对集成电路设计中潜在的常见错误进行检测,提出一种基于静态分析的错误检测方法。该方法可以自动地提取待测寄存器传输级(RTL)设计的行为信息,检测出设计中常见的错误,如状态机死锁、管脚配置错误。实验结果表明,静态检测相对于其他验证方法自动化程度高、检测速度快、检测准确度高、检测代码可重用,可以在模拟之前发现设计中的错误。     

Functional Equivalence Verification Tools in High-Level Synthesis Flows

Editor's note:High-level synthesis facilitates the use of formal verification methodologies that check the equivalence of the generated RTL model against the original source specification. The article provides an overview of sequential equivalence checking techniques, its challenges, and successes in real-world designs.—Andres Takach, Mentor Graphics     

Specification and encoding of transaction interaction properties

Transaction-level modeling is used in hardware design for describing designs at a higher level compared to the register-transfer level (RTL) (e.g. Cai and Gajski in CODES+ISSS ’03: proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, pp. 19–24, 2003; Chen et al. in FMCAD ’07: proceedings of the formal methods in computer aided design, pp. 53–61, 2007; Mahajan et al. in MEMOCODE ’07: proceedings of the 5th IEEE/ACM international conference on formal methods and models for codesign, pp. 123–132, 2007; Swan in DAC ’06: proceedings of the 43rd annual conference on design automation, pp. 90–92, 2006). Each transaction represents a unit of work, which is also a useful unit for design verification. In such models, there are many properties of interest which involve interactions between multiple transactions. Examples of this are ordering relationships in sequential processing and hazard checking in pipelined circuits. Writing such properties on the RTL design requires significant expertise in understanding the higher-level computation being done in a given RTL design and possible instrumentation of the RTL to express the property of interest. This is a barrier to the easy use of such properties in RTL designs.     

Verification Approach of Metropolis Design Framework for Embedded Systems

In this paper, we focus on the verification approach of Metropolis, an integrated design framework for heterogeneous embedded systems. The verification approach is based on the formal properties specified in Linear Temporal Logic (LTL) or Logic of Constraints (LOC). Designs may be refined due to synthesis or be abstracted for verification. An automatic abstraction propagation algorithm is used to simplify the design for specific properties. A user-defined starting point may also be used with automatic propagation. Two main verification techniques are implemented in Metropolis the formal verification utilizing the model checker Spin and the simulation trace checking with automatic generated checkers. Translation algorithms from specification models to verification models, as well as algorithms of generated checkers are discussed. We use several case studies to demonstrate our approach for verification of system level designs at multiple levels of abstraction.     

Reasoning in a Restricted Temporal Logic

We consider RTL, a linear time propositional temporal logic whose only modalities are the [formula] (eventually) operator and its dual [formula] (always). Although less expressive than the full temporal logic, RTL is the fragment of temporal logic that is used most often and in many verification systems. Indeed, many properties of distributed systems discussed in the literature are RTL properties. Another advantage of RTL over the full temporal logic is in the decidability procedure; while deciding satisfiability of a formula in full temporal logic is a PSPACE complete procedure, doing so for an RTL formula is in NP. We characterize the class of ω-regular languages that are definable in RTL and show simple translations between ω-regular sets and RTL formulae that define them. We explore the applications of RTL in reasoning about communication systems. Finally, we relate variants of RTL (when interpreted over a real line segments) to several fragments of Interval Modal Logic and show that the satisfiability problem for RTL when interpreted over a real line is NP-complete.     

利用UML-RT序列图支持基于事务的SoC系统级功能验证

SoC基于事务的验证方法面临的一个重要问题是如何设计验证系统级复杂交互行为的事务测试序列。基于场景的序列图是设计人员捕获系统级功能规约的良好方法。本文提出了一种利用UML-RT序列图捕获SoC各个IP核之间的通信协作行为,为基于事务的验证建立高层规约,指导系统级测试序列生成的方法。我们自行开发了一个基于构件的事务验证环境SoC-CBTVE,并在该环境中利用本文的方法对一个典型的SoC设计进行了验证和分析。实验结果表明,利用UML-RT序列图能够捕获SoC系统级IP核之间的复杂通信行为,有效支持SoC系统级功能验证。     

面向soc芯片的跨时钟域设计和验证

随着高性能、低功耗芯片的发展,多时钟域和跨时钟域(Clock Domain Crossing, CDC)设计越来越多,CDC设计和验证越来越重要。阐述了5种常用的同步器设计模板。验证方法提出了层次化的验证流程:结构化检查,基于断言的验证(assertion-based verification, ABV),对关键模块进行形式化验证。CI)C设计应用于研发的一款65nm工艺SOC芯片(最高主频1GHz,10个时钟域设计、多种工作模式),该芯片已流片回来。经测试,芯片的功能正确,说明设计和验证方法是完备的。     

Verifying Communication Protocols Using Live Sequence Chart Specifications

The need for a formal verification process in System on Chip (SoC) design and Intellectual Property (IP) integration has been recognized and investigated significantly in the past. A major drawback is the lack of a suitable specification language against which definitive and efficient verification of inter-core communication can be performed to prove compliance of an IP block against the protocol specification. Previous research has yielded positive results of verifying systems against the graphical language of Live Sequence Charts (LSCs) but has identified key limitations of the process that arise from the lack of support for important constructs of LSCs such as Kleene stars, subcharts, and hierarchical charts. In this paper we further investigate the use of LSCs as a specification language and show how it can be formally translated to automata suitable for input to a model checker for automatic verification of the system under test. We present the translation for subcharts, Kleene stars, and hierarchical charts that are essential for protocol specification and have not been translated to automata before. Further, we successfully translate the BVCI protocol (point to point communication protocol) specification from LSC to an automaton and present a case study of verifying models using the resulting automaton.