Single-inductor dual-output (SIDO) DC–DC converters for minimized cross regulation and high efficiency in soc supplying systems

A compact size and high efficiency single-inductor dual-output (SIDO) DC–DC converter is proposed. The proposed SIDO DC–DC converter not only provides dual output sources (one buck and one boost outputs) but also has minimized cross regulation without using any external compensation components. Generally speaking, it is important to minimize the number of components and footprint area in the design of SIDO converters. However, usually large external compensation resistors and capacitors are required to stabilize DC–DC converters. Importantly, our proposed hysteresis mode operation can effectively avoid the oscillation problems that may exist in many SIMO designs. Furthermore, the dynamic dc current level like that in the continuous conduction mode (CCM) operation can make the proposed SIDO DC–DC converter achieve high conversion efficiency at light loads owing to small conduction loss. Experimental results show a high efficiency from 85% at light loads to 94% at heavy loads.     

便携应用DC-DC轻负载高效率的实现

提出了一种新颖的DC-DC环路控制结构.轻负载时芯片自动进入省电模式,通过检测反馈电压使其在待机状态与固定峰值状态切换工作,平均静态功耗以及开关功耗大大减小,提高了轻负载效率,延长了便携应用电池的使用时间.内部同步整流消除了肖特基二极管的使用,进一步提高了效率.该结构在一款0.5μm CMOS工艺的降压型DC-DC中进行了投片验证.输入电压3.6V,输出电压1.8V条件下,待机状态静态电流仅为25μA,0.1mA负载下效率高达62%.最高效率为96%.     

A pseudo-CCM/DCM SIMO switching converter with freewheel switching

This paper presents a single-inductor multiple-output (SIMO) converter operating in pseudo-continuous conduction mode (PCCM) and/or discontinuous conduction mode (DCM). With the proposed freewheel switching control, this converter can handle large load currents with a much smaller current ripple, while retaining low cross regulation. It can also work in DCM for high efficiency at light loads. A prototype of a single-inductor dual-output (SIDO) boost converter was fabricated with a standard 0.5-/spl mu/m CMOS n-well process. The two outputs are regulated at 2.5 and 3.0 V, respectively. At an oscillator frequency of 1 MHz, the efficiency reaches 89.4% at a total output power of 320 mW. Compared with prior designs, both current and voltage ripples are reduced. This design can be extended to have multiple outputs and for different types of dc-dc conversions, or be applied to single-output converters for fast transient response.     

A 0.5-V power-supply scheme for low-power system LSIs using multi-V/sub th/ SOI CMOS technology

This paper proposes a novel power-supply scheme suitable for 0.5-V operating silicon-on-insulator (SOI) CMOS circuits. The system contains an on-chip buck DC-DC converter with over 90% efficiency, 0.5-V operating logic circuits, 100-MHz operating flip-flops at 0.5-V power supply, and level converters for the interface between the 0.5-V operating circuit and on-chip digital-to-analog (D/A) converters or external equipment. Based on the theory, the values of on-resistance and threshold voltage of SOI transistors are clarified for the 0.5-V/10-mW output DC-DC converter, which satisfies both high efficiency and low standby power. The proposed flip-flop can hold the data during the sleep with the use of the external power supply, while maintaining high performance during the active. The level converter comprises dual-rail charge transfer gates and a CMOS buffer with a cross-coupled nMOS amplifier to operate with high speed even in a conversion gain of higher than 6, where the conversion gain is defined as the ratio of the output and input signal swings. The test chip was fabricated for the 0.5-V power supply scheme by using multi-V/sub th/ SOI CMOS technology. The experimental results showed that the buck DC-DC converter achieved a conversion efficiency of 91% at 0.5-V/10-mW output with stable recovery characteristics from the sleep, and that the dual-rail level converter operated with a maximum data rate of 300 Mb/s with the input signal swing of 0.5 V.     

A Single-Inductor Step-Up DC-DC Switching Converter With Bipolar Outputs for Active Matrix OLED Mobile Display Panels

A single-inductor step-up DC-DC switching converter with bipolar outputs is implemented for active-matrix OLED mobile display panels. The positive output voltage is regulated by a boost operation with a modified comparator control (MCC), and the negative output voltage is regulated by a charge-pump operation with a proportional-integral (PI) control. The proposed adaptive current-sensing technique successfully supports the implementation of the proposed converter topology and enables the converter to work in both discontinuous-conduction mode (DCM) and continuous-conduction mode (CCM). In addition, with the MCC method, the converter can guarantee a positive output voltage that has both a fast transient response of the comparator control and a small output voltage ripple of the PWM control. A 4.1 mm$^{2}$ converter IC fabricated in a 0.5 $mu$m power BiCMOS process operates at a switching frequency of 1 MHz with a maximum efficiency of 82.3% at an output power of 330 mW.      

Load-Independent Control of Switching DC-DC Converters With Freewheeling Current Feedback

A new control scheme of freewheeling current control is proposed for switching DC-DC converters. The output voltage is regulated by a comparator operation, and in the main current loop, the freewheeling current is feedback-controlled to a reference level in average. The converter control loop is no longer dependent on the values of the inductor, output capacitor, or the load equivalent resistance. The design of a loop compensator is therefore greatly simplified and the loop response can be very fast approaching that of a hysteresis converter. As an example, a single-inductor bipolar-output DC-DC converter with the proposed freewheeling current control is implemented in a 0.5 $mu{hbox{m}}$ BiCMOS process. The converter has one positive output of 4 V and one negative output of $-$4.8 V. A maximum efficiency of 81% is achieved at a total output power of 250 mW with a switching frequency of 800 kHz.      

一种车用恒流/恒压模式的四开关Buck-Boost变换器控制策略研究

对一种车用恒流/恒压模式的四开关Buck-Boost变换器的控制策略进行了研究。在输入输出电压接近时引入Buck-Boost模式,从而在不同输入输出电压大小关系下,通过检测功率管占空比大小,实现Buck模式、Boost模式和Buck-Boost模式之间的平滑切换,提高了系统的稳定性。通过设计最大值选择电路,使变换器在充电应用中自动从恒流模式切换到恒压模式,模式切换平滑稳定。仿真结果表明,在24 V输出电压下,变换器从Buck模式切换到Buck-Boost模式时,输出电压下冲为9.2 mV,变换器从Boost模式切换到Buck-Boost模式时,输出电压下冲为92 mV。变换器在Buck模式与Boost模式下均能实现恒流/恒压模式的自动平滑切换。     

Buck or boost tracking power converter

A cascade of buck and boost converter is presented here. The control operates in a manner that the converter is either in buck or boost (BOB) mode on a cycle by cycle basis. It transitions between the modes seamlessly to provide a tracking power conversion function for modulating the power supply of a variable envelope radio frequency (RF) power amplifier. The control algorithm and its implementation using switched capacitor circuits is described. Simulation and measured experimental results including converter efficiency, tracking accuracy, and spectrum at the output of the RF power amplifier are provided. This control technique allows seamless transition between the buck and boost modes while tracking RF envelopes with bandwidth greater than 100 kHz, and maintaining extreme accuracy and extremely low ripple. The efficiency of this converter operating at 1.68 MHz is close to 90% over a wide range of conversion ratios. The area of the power converter is extremely small allowing this to be integrated into a cellular telephone. The controller was integrated as part of a larger power management IC as well as a discrete IC.     

A high-efficiency,low-noise power solution for a dual-channel GNSS RF receiver

A high-efficiency low-noise power solution for a dual-channel GNSS RF receiver is presented.The power solution involves a DC-DC buck converter and a followed low-dropout regulator(LDO).The pulsewidth -modulation(PWM) control method is adopted for better noise performance.An improved low-power highfrequency PWM control circuit is proposed,which halves the average quiescent current of the buck converter to 80μA by periodically shutting down the OTA.The size of the output stage has also been optimized to achieve high efficiency under a light load condition.In addition,a novel soft-start circuit based on a current limiter has been implemented to avoid inrush current.Fabricated with commercial 180-nm CMOS technology,the DC-DC converter achieves a peak efficiency of 93.1%under a 2 MHz working frequency.The whole receiver consumes only 20.2 mA from a 3.3 V power supply and has a noise figure of 2.5 dB.     

一种新型交错并联同相降压升压DC/DC转换器

为了有效降低电流纹波和提高转换器效率,提出一种新型交错并联同相降压升压DC/DC转换器。提出的结构通过采用输入/输出（I/O）磁耦合交错并联和阻尼网络技术,降低了开关的电压应力、内部电压振荡和I/O电流纹波,并提升了转换器的效率。采用状态空间平均法,在连续导通模式下分析了提出转换器的稳态运行,从理论上证明了其优势。样机的功率设置为360W,输出电压为36 V,模拟结果以及实验结果显示,当输出电流为6A时,转换效率最高达到96%,最大输入电流纹波百分比仅为9.4%,相较于其他类似转换器,提出的转换器具有效率较高和I/O电流纹波较低的优势。     

A dual-mode fast-transient average-current-mode buck converter without slope-compensation

A dual-mode fast-transient average-current-mode buck converter without slope-compensation is proposed in this paper. The benefits of the average-current-mode are fast-transient response, simple compensation design, and no requirement for slope-compensation, furthermore, that minimizes some power management problems, such as EMI, size, design complexity, and cost. Average-current-mode control employs two loop control methods, an inner loop for current and an outer one for voltage. The proposed buck converter using the current-sensing and average-current-mode control techniques can be stable even if the duty cycle is greater than 50%. Also, adaptively switch between pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is operated with high conversion efficiency. Under light load condition, the proposed buck converter enters PFM mode to decrease the output ripple. Even more, switching PWM mode realizes a smooth transition under heavy load condition. Therefore, PFM is used to improve the efficiency at light load. Dual-mode buck converter has high conversion efficiency over a wide load conditions. The proposed buck converter has been fabricated with TSMC 0.35 μm CMOS 2P4M processes, the total chip area is 1.45×1.11 mm². Maximum output current is 450 mA at the output voltage 1.8 V. When the supply voltage is 3.6 V, the output voltage can be 0.8-2.8 V. Maximum transient response is less than 10 μs. Finally, the theoretical analysis is verified to be correct by simulations and experiments.     

一种分段输出PWM Buck DC-DC转换器设计

为了解决PWMDC-DC在轻负载时转换效率骤降的问题,设计了一种分段输出级PWM DC-DC电路结构,用以优化轻负载时的转换效率.该设计引入了负载电流检测电路,对输出电流进行采样并检测.在重载情况下,所有功率MOSFET同时输出.当负载电流减小,逐级关闭各段功率MOSFET,直至在最轻载情况下用最小尺寸的功率MOSFE...     

用降压型单电感多输出DC-DC变换器输出高电压

本文发现并证明了降压型单电感多输出DC-DC变换器当电感工作于连续导通模式下能够产生高于电源电压的输出。这个发现将降低需要同时输出高压和低压的DC-DC变换器的结构复杂性。本文实现了一个降压型结构的单电感双输出的直流变换器,供电电压3.3V,输出为1V和4V。实验结果很好的证明了本文的结论。     

Energy-Efficient Peak-Current State-Machine Control With a Peak Power Mode

The peak-current control that is modeled in this paper is a novel variable-frequency control that maintains regulation in a flyback converter by enabling and disabling cycles instead of modulating the pulse width, which allows for elimination of feedback compensation and can provide for peak power three times higher than the rated full-load power without increasing the power supply component sizes. A state machine sets the peak current of each enabled cycle, based on the load requirements. The variable-frequency nature of this control scheme reduces switching losses significantly at light loads, while the lowering of the peak current by the state machine reduces the output ripple and audible excitations of the transformer. The state-machine control is completely modeled for the first time, including new modeling for the maximum power deliverable in continuous conduction mode (CCM), the peak-current ratio between states, the number of states required for stability, the minimum number of counts for state transitions required for stability, and modeling for a new peak state with double the maximum switching frequency, which provides peak power during brief peak loads, without requiring an overrated transformer . Characterization of a supply that was designed around the monolithic IC that uses this control scheme is provided.      

DCM,FSM,dead time and width controllers for a high frequency high efficiency buck DC-DC converter over a wide load range

This paper presents a width controller,a dead time controller,a discontinuous current mode(DCM) controller and a frequency skipping modulation(FSM) controller for a high frequency high efficiency buck DC-DC converter. To improve the efficiency over a wide load range,especially at high switching frequency,the dead time controller and width controller are applied to enhance the high load efficiency,while the DCM controller and FSM controller are proposed to increase the light load efficiency.The proposed D...     

Design and analysis of power-CMOS-gate-based switched-capacitor boost DC-AC inverter

A multistage power CMOS-transmission-gate-based (CMOS-TG) quasi-switched-capacitor (QSC) boost DC-AC inverter is proposed and integrated with a boost DC-DC converter for a step-up application with AC or DC load. In this paper, using CMOS-TG as a bidirectional switch, the various topologies can be integrated in the same configuration for achieving two functions: boosting and alternating; boosting for getting a sinusoidal output in which the peak is the result of a many times step-up of the input; alternating to realize the positive/negative half sinusoidal of the output. The inverter does not require any inductive elements as inductor and transformer, so integrated circuit (IC) fabrication will be promising for realization. By using the state-space averaging technique, the large-signal state-space model of the inverter is proposed, and then both the static analysis and dynamic small-signal analysis are derived to form a unified formulation for inverter/converter. Based on this formulation, there are presented for theoretical analysis/control design, including steady-state power, conversion efficiency, voltage conversion ratio, output ripple percentage, capacitance selection, closed-loop control and stability, and total harmonic distortion (THD), etc. Finally, a six-stage QSC boost DC-AC inverter is simulated by PSPICE, and the simulations are discussed for some cases, including: 1) steady-state AC output, ripple percentage, and power efficiency; 2) transient response of the regulated inverter for load variation; 3) a practical capacitive load: electromagnetic luminescent (EL) lamp, and 4) efficiency, ripple percentage, and THD for different loads. The results are illustrated to show the efficacy of the proposed inverter.     

Light-Load Efficiency Optimization Method

In this paper, a method of maintaining high power-conversion efficiency across the entire load range and its circuit implementations are described. The proposed method substantially increases the conversion efficiency at light loads by minimizing switching and driving losses of semiconductor switches, as well as core losses of magnetic components. These losses are minimized by periodically turning off and on the power converter, and by controlling the converter so that when the converter is on, it operates at the power level that exhibits the maximum efficiency. The performance of the proposed method was evaluated on a 500-W, 400-V/12-V dc–dc converter and a 1-kW ac–dc boost power-factor-correction front-end.      

一种提高单电感双输出升/降压型转换器轻载效率的设计策略

为了提高单电感双输出升/降压型直流-直流转换器在轻载下的效率,设计实现了适用于不同转换条件的非连续导通模式(DCM)功能和脉冲频率调制(PFM)控制。前者降低了电感电流的均方根值,减少了导通损耗;后者降低了开关频率,减少了开关损耗。详细分析了在PFM控制下转换器的驱动能力、电感电流纹波和输出电压纹波之间相互制约的关系,并采取了一种可以由两路任意升/降压输出灵活复用的自适应导通时间控制方法。经0.25μm 2P4M CMOS混合信号工艺流片验证,测试结果显示DCM和PFM时序与设计方案吻合,各种转换条件下输出电压纹波在40~70 mV。通过比较发现,对轻载效率的提升可以达到30%以上。     

单片降压型DC-DC转换器的控制电路设计

基于峰值电流检测脉宽调制技术原理,设计了一种新颖的应用于单片降压型DC-DC转换器的控制电路。针对峰值电流采样和PWM比较器电路技术,提出了一种新颖的电路结构。其中,PWM比较器和逻辑及驱动电路由升压电路驱动,节省了一个电平转换电路,降低了电路功耗;PWM比较器直接对功率管和镜像管电流采样,无需使用运算放大器,简化了电路结构。采用华虹宏力BCD350GE工艺进行设计,流片测试表明,电路可实现3V到36 V宽幅输入,500 mA满载输出。在输入24 V电压,输出3.3 V电压时,纹波为2.3 mV。     

Zero-Voltage-Switching Control for a PWM Buck Converter Under DCM/CCM Boundary

A new zero-voltage-switching (ZVS) control approach is presented for pulsewidth modulation (PWM) buck converters under discontinuous conduction mode (DCM)/continuous conduction mode (CCM) boundary. This proposed technique compensates for control circuit delay, and hence, turns on power MOS at the instant exactly when drain-to-source voltage becomes zero. No complicated timing calculation circuits or additional external components are required. This proposed integrated ZVS control can be applied to other dc–dc converters as well. The corresponding circuit analysis, implementation, and die photograph are presented in this paper. Simulation and experimental results for an example circuit with $V_{{rm IN}}$ of 5 V and $V_{{rm OUT}}$ of 3.3 V reveal that buck converters with the presented ZVS technique have higher efficiency than conventional ones, especially at higher frequencies. At about 3.6 MHz operation, the measured conversion efficiency of the PWM buck converter under DCM/CCM boundary mode with the proposed ZVS approach is 11$%,$ higher.