包络跟踪的J类功率放大器设计

为了提高功率放大器的回退效率以更好地适应第五代移动通信系统的高峰均比信号的需求,文中提出了一种基于包络跟踪的J类功率放大器的设计方法,通过对电源调制器的设计来动态调制J类功率放大器的供电电压,以降低漏极直流功耗,实现提高功率放大器效率的目标.最终的测试结果表明在3.4～3.6GHz频率范围内,当采用带宽20MHz、峰均...     

A 2.4 GHz Fully Integrated Linear CMOS Power Amplifier With Discrete Power Control

A fully integrated 2.4 GHz CMOS power amplifier (PA) in a standard 0.18 $mu$m CMOS process is presented. Using a parallel-combining transformer (PCT) and gate bias adaptation, a discrete power control of the PA is achieved for enhancing the efficiency at power back-off. With a 3.3 V power supply, the PA has a peak drain efficiency of 33% at 31 dBm peak output power. By applying discrete power control, a reduction of 650 mA in current consumption can be achieved over the low output power range while satisfying the EVM requirements of WLAN 802.11g and WiMAX 802.16e signals.      

A 2.4 GHz Fully Integrated Cascode-Cascade CMOS Doherty Power Amplifier

This letter presents the first CMOS Doherty power amplifier (PA) fully integrated on chip. The "cascode-cascade" amplifier architecture is proposed to get rid of the bulky power splitter and facilitate the integration. The quarter wavelength transmission lines are replaced by the lumped component networks such that the whole amplifier circuit can be squeezed into the die size of 1.97 times 1.4 mm². Fabricated in 0.18 mum CMOS technology, the 3.3 V PA achieves 12 dB power gain. The measured output power and power added efficiency (PAE) at P₁ dB are more than 21 dBm and 14%, respectively. The PAE at 7 dB back-off from P₁ dB is above 10% and the PAE degradation is less than 29%.     

基于GaN HEMT的高线性星载Doherty功率放大器设计北大核心CSCD

在射频通信链路中,功率放大器决定了发射通道的线性、效率等关键指标。卫星通信由于是电池供电,对功率放大器的工作效率要求比较高。文章基于GaN HEMT晶体管采用对称设计完成了一款高效率的Doherty功率放大器。测试结果表明:该Doherty功放的功率增益大于29 dB;1 dB压缩点功率(P_(1 dB))大于35 dBm;在35 dBm输出时,其功率附加效率(PAE)大于47.5%,三阶交调失真(IMD3)大于35 dBc;在功率回退3 dB时,其PAE大于37%,IMD3大于32 dBc。     

A Parallel Power Amplifier With a Novel Mode Switching Control

Two parallel operating power amplifiers (PAs) are controlled by a novel mode switch for high efficiencies at both the back-off power region and high power region. The mode switch is realized by the base-collector (BC) junction diode which reuses the dc current of the low power mode amplifier. A 836 MHz CDMA PA has been demonstrated using InGaP/GaAs heterojunction bipolar transistor with fully integrated matching component for small package and low cost. It shows a 13 mA idle current, 15.4% power added efficiency (PAE), ACPR1 at 16 dBm of the low power mode operation and a 40.5% PAE, ACPR1 at 28 dBm of the high power mode operation.     

一种用于5G通信的高稳定双模功率放大器

采用国产40 nm CMOS工艺,设计了一种用于5G通信的28 GHz双模功率放大器。功率级采用大尺寸晶体管,获得了高饱和输出功率。采用无中心抽头变压器,消除了大尺寸晶体管带来的共模振荡问题。在共源共栅结构的共栅管栅端加入大电阻,提高了共源共栅结构的高频稳定性。采用共栅短接技术,解决了大电阻引起的差模增益恶化问题。在级间匹配网络中采用变容管调节,实现了双模式工作,分别获得了高功率增益和高带宽。电路后仿真结果表明,在高增益模式下,该双模功率放大器获得了20.8 dBm的饱和输出功率、24.5%的功率附加效率和28.1 dB的功率增益。在高带宽模式下,获得了20.6 dBm的饱和输出功率、22.6%的功率附加效率和12.2 GHz的3 dB带宽。     

Fully Integrated CMOS Power Amplifier With Efficiency Enhancement at Power Back-Off

This paper presents a new approach for power amplifier design using deep submicron CMOS technologies. A transformer based voltage combiner is proposed to combine power generated from several low-voltage CMOS amplifiers. Unlike other voltage combining transformers, the architecture presented in this paper provides greater flexibility to access and control the individual amplifiers in a voltage combined amplifier. In this work, this voltage combining transformer has been utilized to control output power and improve average efficiency at power back-off. This technique does not degrade instantaneous efficiency at peak power and maintains voltage gain with power back-off. A 1.2 V, 2.4 GHz fully integrated CMOS power amplifier prototype was implemented with thin-oxide transistors in a 0.13 mum RF-CMOS process to demonstrate the concept. Neither off-chip components nor bondwires are used for output matching. The power amplifier transmits 24 dBm power with 25% drain efficiency at 1 dB compression point. When driven into saturation, it transmits 27 dBm peak power with 32% drain efficiency. At power back-off, efficiency is greatly improved in the prototype which employs average efficiency enhancement circuitry.     

一种基于阻抗缓冲匹配技术的高效率Doherty放大器

为了在功率回退时满足功率放大器对高效率的要求,提出了一种采用阻抗缓冲匹配技术的Doherty功率放大器。通过负载牵引仿真,得到功放管的最佳基波和谐波负载阻抗。在此基础上,采用一种谐波控制阻抗匹配网络设计方法来设计主/辅路放大器的输出匹配网络,实现了高回退效率。为了验证该方法的有效性,设计并实现了一个1.635 GHz高效率Doherty功率放大器。测试结果表明,该放大器的饱和功率大于44 dBm,峰值效率为75%,6 dB功率回退时的效率为70%。该方法能有效提高Doherty功率放大器的回退效率。     

A +31.5 dBm CMOS RF Doherty Power Amplifier for Wireless Communications

A fully differential Doherty power amplifier (PA) is implemented in a 0.13-mum CMOS technology. The prototype achieves a maximum output power of +31.5 dBm with a peak power-added efficiency (PAE) of 36% (39% drain efficiency) with a GMSK modulated signal. The PAE is kept above 18% over a 10 dB range of output power. With a GSM/EDGE input signal, the measured peak output power while still meeting the GSM/EDGE mask and error vector magnitude (EVM) requirements is +25dBm with a peak PAE of 13% (PAE is 6% at 12 dB back-off). Instead of using a bulky lambda/4 transmission line, a passive impedance inverter is implemented as a compact lumped-element network. All circuit components are fully integrated on a single CMOS die except for an off-chip capacitor for output matching and baluns. The die size is 2.8times3.2mm² including all pads and bypass capacitors     

Analytical Design Equations for Class-E Power Amplifiers

This paper presents the analytical solution in time domain for the ideal single-ended class-E power amplifier (PA). Based on the analytical solution a coherent noniterative procedure for choosing the circuit parameters is presented for class-E PA's with arbitrary duty-cycle and finite dc-feed inductance (e.g., continuously ranging from class-E with small finite drain inductance to class-E with RF choke). The obtained analysis results link all known class-E PA design equations as well as presenting new design equations. The result of the analysis gives more degrees of freedom to designers in their design and optimization by further expanding the design space of class-E PA.     

反激式开关稳压电源传导干扰研究

开关式直流稳压电源的电磁干扰不仅对电网产生干扰,导致在同一电网上供电的其它设备不能正常工作,而且严重的谐波电压电流会在开关电源内部产生电磁干扰,从而造成开关电源内部工作不稳定,使开关电源性能降低。文中以反激式开关稳压电源为研究对象,主要分析了传导测试中,差模、共模传导两种方式噪声源的产生机理,建立了开关电源传导干扰模型,采用EMI滤波器即共模滤波和差模滤波,并详细研究了加入π型滤波器、输入x电容、共模扼流圈等对开关稳压电源传导干扰的抑制效果,得出传导干扰抑制在标准限制范围的改进措施,整改后可让传导干扰强度从100μV降低到200 nV并通过认证。研究结果表明该措施对抑制开关稳压电源传导干扰是有效的。     

准 单片连续B / J 类Doherty 功率放大器研制

文中采用准单片工艺研制了两级连续B/ J 类Doherty 功率放大器。采用非对称Doherty 架构,分析当 载波功放的阻抗逆变网络出现失配时,峰值功放非无穷输出阻抗对载波功放负载的影响,扩展了连续B/ J 类Doherty 功放的阻抗设计空间,在保持高回退效率的同时拓展带宽。该设计方法无需提取管芯的封装参数,摆脱对特定管芯 的依赖,更具有普遍性。测试结果表明,采用准单片工艺的2. 3~2. 7 GHz 频段连续B/ J 类Doherty 功率放大器输出 功率大于35 dBm,回退8 dB 漏极效率大于36%。     

Stability of grid amplifiers

We present a stability model for quasi-optical grid amplifiers. This model is useful for predicting and suppressing the common-mode oscillations that often occur in amplifier grids. Three stabilization techniques will be discussed. The first technique uses a capacitor to stabilize the grid. The second approach employs resistance to suppress the oscillations. The final technique stabilizes the grid by reducing the on-chip common-mode resistance, allowing greatly increased amplifier efficiencies. Experimental evidence will be presented to confirm the validity of our stability model.     

射频功率放大器的线性化技术

本文阐述了射频功率放大器非线性产生的原因 ,介绍了几种射频功放的线性化技术 ,以便于射频功放设计者参考     

A polarization-amplitude-phase modulation scheme for improving the power amplifier energy efficiency

To improve the power amplifier (PA) energy efficiency, a polarization–amplitude–phase modulation (PAPM) scheme in wireless communication is proposed. The proposed scheme introduces the signal’s polarization state (PS), amplitude, and phase as the information-bearing parameters. Thus, the data rate can be further enhanced on the basis of the traditional amplitude–phase modulation. Also, since the transmitted signal’s PS completely manipulated by orthogonally dual-polarized antennas is unaffected by PA, PAPM can let PA work in its nonlinear region to acquire high PA efficiency. To further optimize the PA energy efficiency based on PAPM, a constrained optimization problem regarding the output back-off value and the ratio between the data carried by the PS and the amplitude–phase is formulated, and the distribution of the optimum solutions is presented. The simulation results show that PAPM can improve the PA energy efficiency significantly.     

逆F类高效氮化镓Doherty射频功率放大器设计*

逆F 类功放在接近饱和区工作时效率很高,将其与Doherty 功放结构相结合,可以实现一种在大功率回退的情况下仍然具有很高效率的射频功率放大器。本文设计了一款基于GaN HEMT 晶体管的高效率的逆F 类Doherty 功率放大器,工作频带为910MHz-950MHz。单音信号测试结果显示,在930MHz 处,功放回退7.5dB 后漏极效率仍高达64.2%。使用3 载波WCDMA信号作为测试信号,利用数字预失真技术进行线性化后,功放输出信号的上下边带邻信道功率比(ACPR)分别为-35.39dBc 和-35.9dBc。     

新型三路Doherty功放的设计

为了提高数字电视发射机的效率,采用一种新型的三路Doherty电路。基于传输线理论和有源负载牵引理论,推导出三路Doherty的工作原理,同时利用ADS设计一个双3路Doherty电路,并用于数字电视发射机。仿真结果表明,该放大器在功率回退9.1dB时,出现第一个效率峰值点,在整个回退范围内具有3个效率峰值点。实测结果表明,在610MHz中心频率,54dBm输出功率下,该放大器的效率可达41.2%。     

Power Combining in an Array of Microwave Power Rectifiers

Microwave power rectifiers have been developed previously with greater than 85-percent RF-to-dc conversion efficiency. To obtain useful power levels for proposed free-space microwave power transmission applications, numerous rectifier outputs are interconnected in series and/or parallel to share a common dc load. This work analyzes the resultant efficiency degradation when identical rectifiers operate at different RF power Ievels as caused by the power beam taper. Both a closed-form analytical circuit model and a detailed computer-simulation model are used to obtain the output dc load line of the rectifier. The efficiency degradation is nearly identical with series and parallel combining, and the closed-form analytical model provides results which are similar to the detailed computer-simulation model.     

Heuristic Algorithms for Power Amplifier Behavioral Modeling

This letter presents the use of two heuristic search algorithms, named simulated annealing and genetic algorithms, for the extraction of power amplifier (PA) behavioral model parameters. Their application in this letter consists in determining the memory length and the most significant delays of the considered model structure. Two PA behavioral models have been considered: an augmented nonlinear moving average model and a nonlinear auto-regressive moving average model. By using WCDMA signals measured from a three-stage LDMOS class AB PA, both PA models were extracted. Finally, results presenting the advantages of using these heuristic search algorithms are provided.     

通信开关电源的电磁兼容性

为了抑制通信开关电源受到的电磁干扰,解决其电磁兼容性问题,从开关电源的电磁干扰,电磁兼容性等的特点出发,详细分析共模/差模干扰,传导干扰和辐射干扰,并根据相应的干扰问题,提出了开关电源内部PCB布线、元器件分布要求,EMI滤波电路,典型的共模/差模干扰滤波器及其改进方法。同时从电路设计,仪器设备等方面进行改进,进而达到开关电源的工作性能最优化。