CMOS scaling into the nanometer regime

Starting with a brief review on 0.1-μm (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerations. Among the issues discussed are: lithography, power supply and threshold voltage, short-channel effect, gate oxide, high-field effects, dopant number fluctuations and interconnect delays. The last part of the paper discusses several alternative or unconventional device structures, including silicon-on-insulator (SOI), SiGe MOSFET's, low-temperature CMOS, and double-gate MOSFET's, which may lead to the outermost limits of silicon scaling     

The current efficiency of MOS transconductance amplifiers

The current efficiency of several amplifiers is studied using the IDAC amplifier synthesis program. The possibilities and features of IDAC are briefly discussed and some important simulation results are presented. A current excess factor is defined to compare performance independently of gain-bandwidth product and capacitive load. Experimental results of integrated amplifiers are compared with the performances predicted by IDAC and SPICE2. Finally, it is shown how the current efficiency can be further improved.     

Independent control of transconductance gain and input linear rangein a MOS linear transconductance amplifier

A linear self-biasing MOS transconductance amplifier is presented. A linear V-I transfer characteristic is obtained by square-rooting the drain current of a MOS transistor in the saturation region. The main advantage of the circuit is that its transconductance gain and input linear range can be adjusted independently. Simulation results are included to confirm the feasibility of the technique     

Radiation induced transconductance overshoot in the 130 nm partially-depleted SOI MOSFETs

This paper presents the total ionizing dose (TID) radiation performances of core and input/output (I/O) MOSFETs from 130 nm partially-depleted silicon-on-insulator (PDSOI). Both the core NMOS and PMOS are totally hardened to 1.5 Mrad(Si), while the I/O devices are still sensitive to TID effect. The worst performance degradation is observed in I/O PMOS which is manifested as significant front gate threshold voltage shift and transconductance decrease. Contrary to PMOS, front gate transconductance overshoot is observed in short channel I/O NMOS after irradiation. A radiation induced localized damage model is proposed to explain this anomalous phenomenon. According to this model, the increments of transconductance depend on the extension distance and trapped charge density of the localized damage region in gate oxide. More trapped charge lead to more transconductance increase. These conclusions are also verified by the TCAD simulations. Furthermore, the model presents a way to extract the trapped charge density in the localized damage region.     

Short-channel MOS transistors in the avalanche-multiplication regime

Short-channel MOS transistors have been analyzed in the avalanche-multiplication regime. Ionization integrals, internal body effect, and parasitic bipolar turn-on have been investigated in dependence of channel doping profile and substrate doping level. Results of a two-dimensional numerical analysis offer a better understanding of the breakdown mechanisms. For devices with shallow channel doping and high-resistivity substrate, an avalanche-current-induced barrier lowering at the source junction edge is observed. Electron injection via this locally lowered barrier triggers parasitic bipolar action. A deep channel implant improves the source barrier and lower substrate resistivity shifts the parasitic bipolar trigger voltage to higher drain voltage (1-1.5 V).     

Programmable capacitance scaling scheme based on operational transconductance amplifiers

A new programmable capacitance scaling scheme based on the utilisation of two tunable operational transconductance amplifiers (OTAs) is presented. The capability of the OTAs allows tunable positive/negative capacitance scaling factors. The scheme has been verified with simulations and experimentally using commercial bipolar OTAs and can be implemented in CMOS technology.     

Velocity overshoot effects and scaling issues in III-V nitrides

Empirical evidence from submicrometer technology in GaAs- and InGaAs-based field-effect transistors (FETs) has led to an expectation that velocities exceeding the steady state values would be observed in III-V nitride devices. However, scaling of devices down to 0.7 and 0.25 /spl mu/m has so far not yielded any performance enhancement that may suggest an overshoot. In this paper, we examine transport in AlGaN-GaN heterojunction FETs (HFETs) to examine whether velocity overshoot effects occur. Our findings show that very high scattering rates when combined with unusual field profiles, result in a change in the local transport mechanism, and, in the source-gate region, combine to reduce/ify velocity overshoot effects. We also find that the effect of nonequilibrium phonons on transport in the channel is minimal, with the peak nonequilibrium phonon occupation being smaller than the equilibrium phonon occupation.     

Dependence of transconductance on substrate bias in ultrathin silicon-on-insulator MOS transistors

A simple model is presented to explain the dependence of the transconductance on the substrate bias in ultrathin silicon-on-insulator MOS transistors. Good agreement with experimental data is found. The model can also be used to predict the dependence of transconductance on the underlying oxide thickness.<>     

High transconductance and velocity overshoot in NMOS devices at the0.1-μm gate-length level

Transport properties are investigated in self-aligned NMOS devices with gate lengths down to 0.07 μm. Velocity overshoot was observed in the form of the highest transconductances measured to date in Si FETs, as well as in the trend of the transconductance with gate length. The measured transconductance reached 910 μS/μm at liquid-nitrogen temperature and 590 μS/μm at room temperature. Velocity overshoot, by making such transconductances possible, should extend the value of miniaturization to dimensions that are smaller than what was commonly assumed to be worthwhile to pursue     

A Power Silicon Microwave MOS Transistor

Vertical MOS silicon power transistors for microwave power applications have been fabricated using an angle evaporation technique to position the gate electrode on the side of a mesa. These devices have produced 3-W output power at 1.5 GHz as a Class B amplifier and exhibit excellent linearity and noise properties. Device modeling has shown that parasitic capacitances are the chief factor limiting the frequency response, and the prospects for useful devices at 4 GHz are good.     

Quasi-static behavior of MOS devices in the freeze-out regime

The quasi-static CV curves (low-frequency C-V curves) measured in the freeze-out regime of MOS transistors result in peaks near the accumulation or inversion regions depending on the direction of the voltage sweep. In this paper, we report a study of these peaks in n- and p-channel CMOS transistors within and outside compensating wells. The peaks in the quasi-static CV curves are attributed to the capture of minority carriers near inversion by the interface states and the capture of majority carriers by the interface states near accumulation     

A new MOS photon-counting sensor operating in the above-breakdown regime

A solid-state optical sensor based on a buried-channel charge-transfer MOS structure and operated at voltages in the above, breakdown regime is proposed. In this mode of operation the MOS photosensor performs as a photon counter with, it is suggested two significant advantages over similar sensors based on p-n junction diodes, namely: self-quenching of the avalanche discharge and possible implementation in the form of a self-scanned CCD array. In this first demonstration of the proposed device, discrete structures in silicon are investigated experimentally. It is demonstrated that internal gains of 3 × 10⁶electrons/photon are possible during operation at about 10 V above breakdown. It is also shown that, after accousting for dark generation and retriggering effects, the photon-induced count rate saturates with increasing bias above breakdown. The results are in excellent agreement with the theoretical predictions from a two-dimensional model and imply that, at 10-15 V above breakdown avalanche initiation probabilities for electrons in excess of 0.9 have been attained.     

Observation of electron velocity overshoot in sub-100-nm-channel MOSFET's in Silicon

n-channel MOSFET's with channel lengths from 75 nm to 5 µm were fabricated in Si using combined X-ray and optical lithographies, and were characterized at 300, 77, and 4.2 K. Average channel electron velocities υewere extracted according to the equationupsilon_{e}=g_{mi}/C_{ox}, where gmiis the intrinsic transconductance and Coxis the capacitance of the gate oxide. We found that at 4.2 K the average electron velocity of a 75-nm-channel MOSFET is 1.7 × 10⁷cm/s, which is 1.8 times higher than the inversion layer saturation velocity reported in the literature, and 1.3 times higher than the saturation velocity in bulk Si at 4.2 K. As channel length increases, the average electron velocity drops sharply below the saturation velocity in bulk Si. These experimental results strongly suggest velocity overshoot in a 75-nm-channel MOSFET.     

Silicon nanocrystal non-volatile memory for embedded memory scaling

In this paper, we present key features of silicon nanocrystal memory technology. This technology is an attractive candidate for scaling of embedded non-volatile memory (NVM). By replacing a continuous floating gate by electrically isolated silicon nanocrystals embedded in an oxide, this technology mitigates the vulnerability of charge loss through tunnel oxide defects and hence permits tunnel oxide and operating voltage scaling along with accompanied process simplifications. However, going to discrete nanocrystals brings new physical attributes that include the impact of Coulomb blockade or charge confinement, science of formation of nanocrystals of correct size and density and the role of fluctuations, all of which are addressed in this paper using single memory cell and memory array data.     

引入基态施主能级分裂的SiC基MOS电容模型

基态施主能级分裂因素被引入了SiC基MOS电容模型。考虑到能级分裂后,电容C-V特性曲线平带附近的Kink效应,得到有效减弱;并且能级分裂对C-V特性的影响,随掺杂浓度的增加和温度的降低而增强,同时也与杂质能级深度相关。对于耗尽区和弱积累区,由于能级分裂的影响,电容的表面电荷面密度将分别有所增加和降低。     

New channel engineering for sub-100 nm MOS devices considering bothcarrier velocity overshoot and statistical performance fluctuations

We introduce a new channel engineering design for nano-region SOI and bulk MOSFETs taking into account both carrier velocity overshoot and statistical performance fluctuations. For types of both device, in the high gate drive region, the high field carrier velocity υ_e is not degraded at channel dopant density N_a lower than 1×10¹⁷ cm^-3, according to an experimental universal relationship between υ_e and the low field mobility. On the other hand, there is a most suitable N_a condition for suppression of statistical threshold voltage fluctuations. This most suitable N_a is slightly higher for SOI devices than that for bulk MOSFETs, but it is lower than 1×10 ¹⁷ cm^-3 in both cases. Therefore, this most suitable N_a condition is consistent with the above N_a condition for carrier velocity. Consequently, new N_a conditions for nano region devices are introduced in this study. N_a should be designed to be of the order of 1×10¹⁶ cm^-3 rather than rising by the usual scaling rule, but it is necessary to suppress the short channel effects of SOI and bulk MOSFETs by scaling down the SOI thickness, and to use source/drain junction depth scaling or surface low impurity structures in bulk MOSFETs, respectively     

Surface conduction in short-channel MOS devices as a limitation to VLSI scaling

In MOS VLSI device scaling, two major limiting mechanisms are the punchthrough and source-drain breakdown. The punchthrough mechanism is generally considered a bulk-dominated effect. Drain-source avalanche breakdown is generally attributed to bipolar transistor action between drain and source, dominated by injection through the neutral substrate region. The present work includes an experimental verification and a qualitative model demonstrating that both punchthrough and drain-source avalanche breakdown limitations are surface and surface-depletion-region dominated mechanisms, respectively. The two mechanisms are treated simultaneously since both involve enhanced injection from the source due to drain-induced source-potential barrier lowering. The experimental verification is done over a wide range of relevant device parameters, channel implant concentration between 5 × 10¹⁴-1 × 10¹⁶cm^-3for punchthrough and 2 × 10¹⁵-5 × 10¹⁶cm^-3for drain-source avalanche breakdown, effective channel length of 1.0-30.0 µm for both mechanisms.     

Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor

Epitaxial delta-doped channel (EδDC) profile is a promising approach for extending the scalability of bulk metal oxide semiconductor (MOS) technology for low-power system-on-chip applications. A comparative study between EδDC bulk MOS transistor with gate length L_g = 22 nm and a conventional uniformly doped channel (UDC) bulk MOS transistor, with respect to various digital and analogue performances, is presented. The study has been performed using Silvaco technology computer-aided design device simulator, calibrated with experimental results. This study reveals that at smaller gate length, EδDC transistor outperforms the UDC transistor with respect to various studied performances. The reduced contribution of the lateral electric field in the channel plays the key role in this regard. Further, the carrier mobility in EδDC transistor is higher compared to UDC transistor. For moderate gate and drain bias, the impact ionisation rate of the carriers for EδDC MOS transistor is lower than that of the UDC transistor. In addition, at 22 nm, the performances of a EδDC transistor are competitive to that of an ultra-thin body silicon-on-insulator transistor.     

Hot-electron injection into the oxide in n-channel MOS devices

In recent years, interest in hot-electron injection current in MOS devices has increased due to advances in device concepts and technology. The injection current to the gate is the mechanism for programming FAMOS devices and determines the potential degradation of short-channel MOS devices due to electron trapping in the oxide. This work presents an accurate indirect current measurement technique based on charge transport to the floating gate in a FAMOS structure. The measurement bypasses effects of trapping and local heating, allowing full characterization of parameter, voltage, and temperature dependence down to gate current levels of 10^-16A. Based on this characterization, a new qualitative model of hot-electron injection into the oxide is proposed. The basic assumption in the model is the spherical symmetry of the momentum distribution function of the hot electrons. This assumption leads to the experimentally observed dominant role of the lateral electric field in the pinchoff region in determining gate current behavior. The model provides an explanation of gate current parameter and voltage dependence, and suggests correlation between gate current and substrate impact ionization current in a range of operating voltages. This correlation is substantiated experimentally for a range of device parameters and voltages.