Optimized design of a merged bipolar MOSFET device

Numerical techniques have been applied to predict the steady-state characteristics of lateral bipolar-MOSFET (BIMOS) power switching devices. The BIMOS has the same structure as a lateral double-diffused MOSFET (LDMOS), with the p-type channel region acting as the base of an n-p-n transistor. By merging MOSFET and bipolar transistors in a lateral configuration, a monolithic power-integrated circuit is realized which retains some of the desirable features of both types of transistors for switching applications. Specifically, the structure of a switching device with low on-resistance high voltage capability, fast switching speed, and high input impedance is derived which does not require significantly increased device fabrication complexity. A special junction isolation design was used to limit the parasitic effects involving the substrate. These parasitic effects can degrade the performance of the BIMOS by reducing the gain of the n-p-n transistor and introducing a large substrate current. An off-state model has been developed in order to study the field shaping effects which occur with the inclusion of the junction isolation. The design is optimized to obtain a high-breakdown-voltage low-on-resistance parasitic-free monolithic-power integrated circuit.     

High-voltage technology offers new solutions for interface integrated circuits

A BIMOS IC technology improving the design of interface circuits that require either high-voltage (up to 120 V) of current (up to a few amperes per output) has been developed. Both bipolar and MOS complementary components are processed together on the same chip for low- and high-voltage applications. Various BIMOS power interface circuits are now in production, e.g., a motor driver, a high-voltage plasma display driver, and a printer head driver. This paper describes the BIMOS technology and the characteristics of its components. As applications, two circuits are presented: the UEB 4732 (plasma display driver) with complementary MOS push-pull output stages (120 V), and the UAA 2081 (stepper motor driver) with power bipolar transistors (1 A per output). Both circuits have a logical part designed with low-voltage CMOS (5-12 V).     

An advanced bipolar-MOS-I2L technology with a thin epitaxial layer for analog-digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I²L) and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-µm design rule. Thin epitaxial layer (leq 2 microm) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n⁺buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.     

Computer analysis of the double-diffused MOS transistor for integrated circuits

The effective length of an MOS transistor can be made narrow by using double diffusion similar to a bipolar transistor. Computations were conducted for an n-channel double-diffused transistor with different surface concentrations, channel lengths, channel gradients, surface-states densities, and substrate concentrations. A shorter channel length and a higher surface-state density, e.g.langle1, 1, 1ranglecrystal, gave a higher drain current and transconductance. The maximum transconductance in many cases occurs at low gate voltages. The computations indicate that a gain-bandwidth product in the gigahertz range can be expected when the graded channel region is less than 1 µm. The difference between an n-type substrate and a p-type substrate is not substantial. The analysis is also useful in predicting the performance of any integrated logic circuit using the diffused enhancement transistor as the active switch and a depletion-mode transistor (without a diffused channel) as the load device. The computation indicates that satisfactory performance can be obtained using a load device with the same geometry and an ON voltage of only a fraction of a volt, This revelation indicates that double-diffused channel MOS transistors not only give higher speed but also smaller chip area for integrated circuits and a lower supply voltage (hence less power dissipation).     

An Advanced Bipolar-MOS-I/sub 2/L Technology with a Thin Epitaxial Layer for Analog-Digital VLSI

A novel Bi-MOS technology, Advanced Bipolar CMOS (ABC), is proposed. Bipolar transistors (n-p-n, p-n-p, I/sup 2/L)and MOS transistors (both n- and p-channel) have been successfully fabricated on the same chip with no decrease in performance by using a 3-/spl mu/m design rule. Thin epitaxial layer (<= 2 /spl mu/m) is used in order to obtain small-size high-performance (3-GHz) bipolar devices. Device size is reduced by using a shallow junction and self-aligning technique. n-channel MOS transistors are formed in p-well regions designed to reach p-type substrate, and p-channel MOS transistors are formed in epitaxial layer with an n/sup +/ buried layer. This technology has the potential for monolithic multifunctional analog-digital VLSI.     

BiMOS transistors: merged bipolar/sidewall MOS transistors

The concept and feasibility of merged bipolar/sidewall MOS transistors (BiMOS transistors) are demonstrated by fabricating and characterizing the structures. The NMOS-input Darlington pair was merged into an NMOS-input BiMOS Darlington transistor which occupies 1.2 times the area of a single n-p-n bipolar transistor. It should be possible to form other BiCMOS subcircuit elements such as the PMOS-input BiMOS Darlington transistor and BiCMOS static memory cell. An initial analysis of the doping requirements for the base of the n-p-n bipolar transistor and the channel of the sidewall MOS transistors suggests that the requirements are compatible     

A monolithic 70-V subscriber line interface circuit

The design of a new monolithic 70-V BIMOS line interface circuit (BLIC), developed as a direct interface to the subscriber line, is described. This is the basic analog segment of a new subscriber-line interface circuit (SLIC). The LSI chip has been designed using a 70-V BIMOS process, combining high- and low-voltage bipolar transistors (70 and 15 V) with CMOS (15-V) transistors all using the same junction depths. The LSI chip meets stringent requirements on several specifications and performs ten basic functions.     

A comparison between BIMOS device types

This paper deals with the design and comparison of three types of BIMOS transistors (cascade, cascode, and parallel combinations of MOSFET and bipolar transistors). The first section of the paper presents a technique for accurately determining the overall deviceI-Vrelations for the cascade (Darlington) combination based on the area ratio for the MOSFET and bipolar transistors. From this, one sees that the optimum area ratio varies from 1.5 for 700-V devices to 0.2 for 80- V devices. The second section of the paper deals with the design and comparison of the cascode and parallel device types. In these cases, no optimum area ratio based solely on device conduction exists and the device design and comparison is based on achieving the maximum current density limited by keeping the power dissipation to under 100 W/ cm². Included in this analysis are losses due to conduction as well as switching. The results show that a 0.5 area ratio (MOSFET to bipolar transistor) is optimum for the cascode (series) combination and a 0.3 ratio is a good compromise for the parallel combination. The last section of the paper shows an overall comparison of all of the BIMOS device types together with the MOSFET and the bipolar transistor.     

A new dynamic random access memory cell using a bipolar MOS composite structure

A new dynamic random access memory (RAM) cell which incoperates an n-p-n bipolar junction transistor with an n-channel MOSFET in a composite structure, is proposed and investigated. In this novel cell called the BIMOS cell, the collector-base junction serves as a buried storage capacitor whereas the n-MOSFET as a transfer gate. The fabrication technology is simple and compatible with that of single-polysilicon CMOS IC's and a minimum cell size of 14.875F²with a minimum feature sizeFis realizable. The write, read, and standby operations of the cell are analyzed and simulated. An experimental cell is fabricated and characterized. Dynamic test is successfully performed. The investigation on the cell performance is also made. It has shown that large storage capacitance to bit-line capacitance ratio as well as fairly good packing density, soft-error immunity and leakage characteristics are expected. Furthermore, as compared to the conventional 1-transistor cell the new cell can be scaled down with less processing troubles and better performance improvements. Simple process and good scaled-down properties offer great potential for the proposed new cell to be used in the design of larger dynamic MOS RAM's.     

Bipolar transistor fabrication in low-temperature (745°C) ultra-low-pressure chemical-vapor-deposited epitaxial silicon

In this letter we report for the first time the successful fabrication of bipolar transistors in low-temperature (Tdep= 745°C) epitaxial silicon deposited by a chemical-vapor-deposition (CVD) technology. The epitaxial layers were deposited by an ultra-low-pressure CVD (U-LPCVD) technique utilizing an optimized in-situ predeposition argon sputter clean. The critical parameter during the sputter clean has been identified as the substrate bias. Bias voltages of -200 or -300 V create dislocations that form emitter-collector shunts during the bipolar transistor fabrication process; a bias voltage of -100 V, however, permits the deposition of essentially defect-free (<10 dislocations cm^-2by defect etching) epitaxial films suitable for bipolar transistor fabrication.     

Analysis and design of the dual-gate inversion layer emitter transistor

The dual-gate inversion layer emitter transistor (DGILET) is a device in which the injection of minority carriers takes place from an inversion layer formed under a MOS gate. Therefore, the device can be switched between MOS and bipolar modes using the gate giving the means to achieve a superior combination of low conduction losses and low switching losses. The structure of the device and operation in both the unipolar and bipolar modes are described in detail. Devices have been fabricated on bulk silicon wafers using junction isolation and experimental results confirm the expected superior performance. In particular, the results confirm predictions that if the inversion layer injector is properly designed, the voltage snapback that occurs during the transition between unipolar and bipolar modes can be completely suppressed. This can be achieved with a compact structure in contrast to the extended structures required in anode-shorted lateral insulated gate bipolar transistor (LIGBTs). An equivalent circuit for the DGILET is presented and the control of the minority carrier injection is also analyzed. Experimental results show that the DGILET can switch at speeds approaching those characteristic of MOSFETs with operating current densities comparable to LIGBTs. The results show that the DGILET offers lower overall losses than an LIGBT at switching frequencies above about 10 kHz.     

A model for the breakdown characteristics of p-channel MOS transistor protection devices

Gate controlled diodes, MOS transistors with grounded gate, source and substrate and gate controlled pnn + structures are compared when used as a protective input device on p-channel MOS integrated circuits. For this purpose two pulse techniques are developed which allow an accurate determination of the dynamic resistance by minimizing the walk-out of the breakdown voltage during the measurement. While the breakdown voltage does not differ much for the different types of devices, the dynamic resistance however is found to be considerably lower for the MOS transistor than for both other devices. For these low values the series resistance of the drain and source diffusion is shown to constitute already an important contribution. The lower dynamic resistance of MOST's can be ascribed to parasitic bipolar transistor operation during breakdown. The identification of this mechanism leads to a simple model for the MOS transistor in breakdown which has been experimentally verified and confirmed. Guidelines for the definition of the source diffusion for an optimal protective functioning can be obtained from this model.     

Selective low-pressure silicon epitaxy for MOS and bipolar transistor application

The selective low-pressure epitaxy is presented in this paper. In contrast to LOCOS technology, this process starts with structuring a thick field oxide by anisotropic RIE etching. Then monocrystalline silicon is grown selectively in the windows formed. Si-gate MOS transistors have been produced using this technology. In the field of bipolar transistors, reactive ion etching and selective low-pressure epitaxy has been used to optimize the Schottky collector transistor to a nearly one-dimensional structure. These transistors have been built on a submicrometer epitaxial layer.     

Comparison of input offset voltage of differential amplifiers using bipolar transistors and field-effect transistors

A field-effect transistor (whether junction type or MOS type) has very high input impedance. For those who desire to achieve a higher input impedance, it is often asked `Why aren't FET pairs used as input stages and bipolar transistors used as output stages, since compatible FET and bipolar transistor monolithic structures have been developed?' This correspondence is a study of this question.     

Properties of ESFI MOS transistors due to the floating substrate and the finite volume

The specific current-voltage characteristics of epitaxial silicon films on insulator (ESFI®) SOS MOS transistors are shown, discussed in comparison to bulk silicon MOST's, and explained by the differences in geometrical considerations, charge distribution, and operation mode, The ESFI MOST's are produced on silicon islands, in most applications, the electrical substrate is at floating potential. This results in two effects. At first a threshold voltage change occurs with increasing drain voltage, producing a kink in the current curve; if the drain voltage further increases, a parasitic bipolar transistor begins to work and effects another kink or bend in the curve. On the other hand, the finite vo|ume effects a strong dependence of the base width of the parasitic bipolar transistor on the drain voltage and causes a rise of the current amplification with the drain voltage. The finite volume below the gate oxide also limits the bulk-charge magnitudes with subsequent increase in mobile carrier charge, thereby increasing the transconductance. All these effects are also described theoretically; the ID-VDcharacteristics could be simulated by computer model based on the physical effects.     

The MOS inversion layer as a minority carrier injector

In this paper we report the first experimental demonstration of the concept of MOS inversion layer injection (ILI). The new physical concept is based on the use of a MOS inversion layer as a minority carrier injector as part of a dynamic junction. The carrier injection of such a junction is entirely controlled by the MOS gate. Moreover, when the gate potential is reduced under the MOS threshold voltage, the junction collapses ensuring a very efficient turn-off mechanism. Based on this concept we propose two novel lateral three-terminal structures termed inversion layer diode (ILD) and inversion layer bipolar transistor (ILBT). The concept of inversion layer injection can be applied in power devices where effective MOS gate control of the active junctions is important     

The effects of impact ionization on the operation of neighboringdevices and circuits

This paper examines the detrimental effects of excess majority carriers and photons induced by impact ionization on the operation of neighboring pn junctions, bipolar transistors, MOS transistors, and circuits. The experimental results show that in addition to an increase in the substrate surface potential due to the excess majority carriers, photons can lower the barrier of a pn junction and, as a consequence, shift the Gummel plot of an npn bipolar transistor. As for the neighboring circuits, an example in which the speed of an NMOS ring oscillator is retarded by impact ionization in a neighboring NMOS transistor is presented     

Study of hot electron degradation in submicrometer gate length MOS transistor fabricated with selectively doped substrate engineering

Investigations are made on the performance and hot electron degradation of sub-μm MOS transistors fabricated with an improved selectively doped substrate (SDS) and with the conventional deep punch through implant (DPI) structures. The sub-μm gate length of the transistor was defined by a novel subtractive photolithography technique. The technique is described and the process details are given. The sub-μm transistor performance is characterised by electron mobility, inverse subthreshold slope, substrate sensitivity and drain induced barrier lowering (DIBL) for the two structures. The substrate current and hot electron degradation effect (HED) were measured and the results are compared for SDS and DPI techniques. It is shown that SDS structure reduces HED and surface punchthrough effects in sub-μm MOS transistors.     

Device characterization on monocrystalline silicon grown over SiO2by the ELO (epitaxial lateral overgrowth) process

MOS and lateral bipolar transistors have been fabricated on epitaxial silicon layers which have been laterally overgrown over SiO2. These device characteristics were than compared to those measured on devices fabricated on homoepitaxial silicon and bulk silicon. The measurements indicate essentially identical MOS device characteristics for all three materials with a typical hole field effect mobility of about 180 cm²/vs. Lifetime measurements using pulsed C-V techniques showed essentially the same values for ELO material and homoepitaxial material with the ELO value being about 20 µS for 10¹⁵cm^-3doping level. These lifetime values correlate will with diode and bipolar transistor measurements.     

Vertical bipolar transistors on buried silicon nitride layers

The letter reports on the integration of vertically operating n-p-n-bipolar transistors with base widths of about 1 µm in silicon-on-insulator (SOI) structures. Nitrogen ion implantation at substrate temperatures of 550°C and subsequent SiCl4epitaxy provide SOI films with excellent crystalline quality. Conventional bipolar diffusion processes have been applied in order to fabricate diodes and vertical bipolar transistor arrays on thus isolated epitaxial layers. The leakage current of SOI diodes exceeds the value for bulk devices only by a factor of 2. The transistors exhibit emitter current gains of up to 100 and emitter-collector breakdown voltages of up to 35 V.