Electron fluence driven,Cu catalyzed,interface breakdown mechanism for BEOL low-k time dependent dielectric breakdown

During technology development, the study of low-k time dependent dielectric breakdown (TDDB) is important for assuring robust chip reliability. It has been proposed that the fundamentals of low-k TDDB are closely correlated with the leakage conduction mechanism of low-k dielectrics. In addition, low-k breakdown could also be catalyzed by Cu migration occurring mostly at the interface between capping layer and low-k dielectrics. In this paper, we first discuss several important experimental results including leakage modulation by changing the capping layer without changing the electric field, TDDB modulation by Cu-free and liner-free interconnect builds, 3D on-flight stress-induced leakage current (SILC) measurement, and triangular voltage sweep (TVS) versus TDDB to confirm the proposed electron fluence driven, Cu catalyzed interface low-k breakdown model. Then we review several other low-k TDDB models that consider only intrinsic low-k breakdown, especially the impact damage model. Experimental attempts on validation of various dielectric reliability models are discussed. Finally, we propose that low-k breakdown seems to be controlled by a complicated competing breakdown process from both intrinsic electron fluence and extrinsic Cu migration during bias and temperature stress. It is hypothesized that the amount of Cu migration during TDDB stress strongly depends on process integration. The different roles of Cu in low-k breakdown could take different dominating effects at different voltages and temperatures. A great care must be taken in evaluating low-k dielectric TDDB as its ultimate breakdown kinetics could be strongly dependent on interconnect space, process, material, stress field, and stress temperature.     

Air-Gaps for High-Performance On-Chip Interconnect Part II: Modeling, Fabrication, and Characterization

Air-gaps are the ultimate low-k material in microelectronics due to air having a low dielectric constant close to 1.0. The interconnect capacitance can further be reduced by extending the air-gaps into the interlayer dielectric region to reduce the fringing electric field. An electrostatic model (200 nm half-pitch interconnect with an aspect ratio of 2.0), was used to evaluate the dielectric properties of the air-gap structures. The incorporation of air-gaps into the intrametal dielectric region reduced the capacitance by 39% compared with SiO₂. Extending the air-gap 100 nm into the top and bottom interlayer SiO₂ region lowered the capacitance by 49%. The ability to fabricate air-gaps and ‹extended air-gaps’ was demonstrated, and the capacitance decrease was experimentally verified. Cu/air-gap and extended Cu/air-gap interconnect structures were fabricated using high-modulus tetracyclododecene (TD)-based sacrificial polymer. The aspect ratio of the air-gap was 1.8 and the air-gap was extended 80 nm and 100 nm into the top and bottom interlevel SiO₂ region, respectively. The measured effective dielectric constant (k _eff) of the Cu/air-gap and the extended Cu/air-gap structures with SiO₂ interlevel dielectric was 2.42 and 2.17, respectively. The effect of moisture uptake within the extended Cu/air-gap structure was investigated. As the relative humidity increased from 4% to 92%, the k _eff increased by 7%. Hexamethyldisilazane was used to remove adsorbed moisture and create a hydrophobic termination within the air-cavities, which lowered the effect of humidity on the k _eff. A dual Damascene air-gap and extended air-gap fabrication processes were proposed and the challenges of using a sacrificial polymer placeholder approach to form air-cavities are compared to other integration approaches of dual Damascene air-gap.     

Cu/low-k dielectric TDDB reliability issues for advanced CMOS technologies

With the wide application of low-k and ultra-low-k dielectric materials at the 90 nm technology node and beyond, the long-term reliability of such materials is rapidly becoming a critical challenge for technology qualification. Low-k time-dependent dielectric breakdown (TDDB) is usually considered as one of the most important reliability issues during Cu/low-k technology development because low-k materials generally have weaker intrinsic breakdown strength than traditional SiO₂ dielectrics. This problem is further exacerbated by the aggressive shrinking of the interconnect pitch size due to continuous technology scaling. In this paper, three critical issues of low-k TDDB characteristics during low-k development and qualification will be reviewed. In the first part, a low-k TDDB field acceleration model and its determination will be discussed. In the second part, low-k dielectric time-to-breakdown (t_BD) statistical distribution and TDDB area scaling law for reliability projection will be examined. In the last part, as low-k TDDB has been found to be sensitive to all aspects of integration, the effects of process variations on low-k TDDB degradation will be demonstrated. Some key aspects which need to be carefully addressed to control overall low-k TDDB performance from process and integration side will be discussed.     

Reliability challenges for copper interconnects

In the past few years, copper has been widely used as interconnect metallization for advanced ultralarge-scale integration (ULSI) circuits. Due to the unique chemical properties of copper compared to its predecessor, aluminum, different integration processes must be used for circuit fabrication, that is, the damascene versus reactive ion etch (RIE) process. This difference in integration processes introduces a series of reliability concerns for copper interconnects. After a brief comparison of copper and aluminum interconnects, this article discusses the impact of the differences in the material properties and integration process on reliability. Details are provided on two advanced metallization reliability failure mechanisms: electromigration and stress migration. For copper interconnects, the interface between the cap and the copper metal serves as the fast diffusion path. To improve copper interconnect reliability, development efforts have focused on suppressing copper or copper vacancy diffusion along the interface. Two copper interfaces, the copper/cap interface and the copper/liner (or diffusion barrier) interface, are critical for copper reliability. For commonly used liners, such as Ta/TaN, the copper/liner interface is relatively easy to control compared to the copper/cap interface. For dual-damascene copper lines, a copper via is used to connect the lower level to the upper level. Unlike the robust tungsten stud used in aluminum interconnects, the copper via has been identified as a weak link in dual-damascene copper connections; the majority of early reliability failures can be attributed to the copper vias. The three most critical process factors and elements affecting copper interconnect reliability are copper vias and interfaces and the liner coverage. Using a low-k dielectric with a copper interconnect introduces several new challenges to reliability, including dielectric breakdown, temperature cycle, and stability within packages. Extensive knowledge is urgently needed to understand these issues.     

The need for multi-scale approaches in Cu/low-k reliability issues

Since recent years, micro-electronic industry changed the basic materials from Al/SiO₂ to Cu/low-k in IC interconnect structure. As a consequence, new reliability issues at device/product level has been discovered, and most of the failure modes have the characteristics of multi-scale: the failure of the μm or nm induces the malfunction of the device/product. Under the pressure of the time-to-market, the industries, universities and research institutes developed numerous multi-scale simulation technologies/tools to analyze the failure mechanism and to achieve the high reliability design with the capability of high volume production and low cost. This paper reviews the multi-scale modeling techniques for reliability and processing issues in Cu/low-k IC back-end structure, from the continuum level to the atomic scale.     

Band diagram for low-k/Cu interconnects: The starting point for understanding back-end-of-line (BEOL) electrical reliability

The starting point for describing the electrostatic operation of any semiconductor device begins with a band diagram illustrating changes in the semiconductor Fermi level and the alignment of the valence and conduction bands with other interfacing semiconductors, insulating dielectrics and metal contacts. Such diagrams are essential for understanding the behavior and reliability of any semiconductor device. For metal interconnects, the band alignment between the metal conductor and the insulating intermetal and interlayer dielectric (ILD) is equally important. However, relatively few investigations have been made. In this regard, we have investigated the band alignment at the most common interfaces present in traditional single and dual damascene low-k/Cu interconnect structures. We specifically report combined X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy (REELS) measurements of the Schottky barrier present at the ILD and dielectric Cu capping layer (CCL) interfaces with the Ta(N) via/trench Cu diffusion barrier. We also report similar measurements of the valence and conduction band offsets present at the interface between a-SiN(C):H dielectric CCLs and low-k a-SiOC:H ILDs (porous and non-porous). The combined results point to metal interfaces with the CCL having the lowest interfacial barrier for electron transport. As trap and defect states in low-k dielectrics are also important to understanding low-k/Cu interconnect reliability, we additionally present combined electron paramagnetic resonance (EPR) and electrically detected magnetic resonance (EDMR) measurements to determine the chemical identity and energy level of some electrically active trap/defect states in low-k dielectrics. Combined with the photoemission derived band diagrams, the EPR/EDMR measurements point to mid-gap carbon and silicon dangling bond defects in the low-k ILD and CCL, respectively, playing a role in electronic transport in these materials. We show that in many cases the combined band and defect state diagrams can explain and predict some of the observed reliability issues reported for low-k/Cu interconnects.     

XPS studies of the ALD-growth of TaN diffusion barriers: Impact of the dielectric surface chemistry on the growth mechanism

The introduction of SiOCH low-k dielectrics in the copper interconnections of sub-45 nm node technologies is a challenge in terms of both material and process criteria. For instance, the deposition of a diffusion barrier between copper and dielectric is strongly dependent on the nature of the dielectric surface. In this study, we investigate the first steps of ALD TaN growth with respect to dielectric surface chemistry, using XPS measurements. Three different dielectrics have been tested: SiOCH, SiO₂ or SiOCH capped by a thin SiO₂ layer. We show that TaN can only grow over a monolayer-thick Ta₂O₅ formed at the early stages of deposition. A mechanism for the growth first steps is described, explaining the incubation delays observed for the appearing of Ta-O and Ta-N bonds. In addition, we show that a 3 nm-thick SiO₂ layer is able to hide the effect of SiOCH chemistry and obtain similar growth rates on SiOCH and SiO₂.     

Wire-bonding process development for low-k materials

A 60-μm bond-pad-pitch wire-bonding process was developed using test dies with a SiO₂ dielectric layer under aluminium pads, and was then fine-tuned for a low-k device using three types of gold wires with different mechanical properties. Bulk material hardness of the wires were characterised using a wire-bonding machine, the force applied and diameters of squashed free-air balls. It was found that stiffer wires needed higher ultrasonic-generator (USG) power than a softer wire to deform the ball after impact and achieve equivalent ball size and ball shear responses. Longer bond time was also needed for the low-k material than the SiO₂ material, to overcome the energy loss due to the compliance of the low-k material. Pad damage on the low-k device was proportional to bulk material hardness. The soft 4N (99.99% purity) wire required lower USG power to achieve the bonding specification, and was the most suitable wire to be used in wire bonding of the low-k device.     

Characterization of Self-Formed Ti-Rich Interface Layers in Cu(Ti)/Low-k Samples

In our previous studies, thin Ti-rich diffusion barrier layers were found to be formed at the interface between Cu(Ti) films and SiO₂/Si substrates after annealing at elevated temperatures. This technique was called self-formation of the diffusion barrier, and is attractive for fabrication of ultralarge-scale integrated (ULSI) interconnects. In the present study, we investigated the applicability of this technique to Cu(Ti) alloy films which were deposited on low dielectric constant (low-k) materials (SiO _x C _y ), SiCO, and SiCN dielectric layers, which are potential dielectric layers for future ULSI Si devices. The microstructures were analyzed by transmission electron microscopy (TEM) and secondary-ion mass spectrometry (SIMS), and correlated with the electrical properties of the Cu(Ti) films. It was concluded that the Ti-rich interface layers were formed in all the Cu(Ti)/dielectric-layer samples. The primary factor to control the composition of the self-formed Ti-rich interface layers was the C concentration in the dielectric layers rather than the enthalpy of formation of the Ti compounds (TiC, TiSi, and TiN). Crystalline TiC was formed on the dielectric layers with a C concentration higher than 17 at.%.     

UV-O3 treatment effects on structural changes of low-k thin films

The UV-O₃ treatment effects on the structural properties of low-k films as a function of the treatment time were investigated in this study. The thickness of the samples proportionally decreased with the surface treatment time due to highly reactive ozone and the process gradually modified surface layer more SiO₂-like. Excessive treatment of longer than 60 s adversely affected the low-k film, increasing the dielectric constant of underlying low-k film. After the UV-O₃ treatment for the optimized treatment time of 60 s, the poor nucleation problem of Ru deposition was solved and fully-covered Ru film on low-k film was obtained.     

Applications of finite element methods for reliability study of ULSI interconnections

Three main failure mechanisms of ULSI interconnects are the electromigration (EM), stress induced voiding (SIV) and low-k dielectric breakdown. Reliability tests for these mechanisms are too long to meet the development time requirement, and the underlying dominant mechanisms cannot be identified, rendering difficulty in design-in reliability for integrated circuit. Facing the challenges in the reliability study of the interconnect system, physics based simulation and modeling is found to be essential, and finite element method (FEM) is a suitable tool. A few examples on the application of FEM to study the degradation processes and identification of potential failure sites in interconnects due to EM and SIV are given here. The study of the process induced degradation of the effective k value of low-k dielectric in ULSI interconnect system using FEM is also presented.     

Conduction mechanisms of silicon oxide/titanium oxide MOS stack structures

During the last years, high-k dielectrics have been studied intensively looking for an alternative material to replace the SiO₂ films as gate dielectric in MOS transistors. Different materials and structures have been proposed. An important concern not yet solved, is the interfacial quality between high-k materials and silicon substrate. For this reason, stack structures with SiO₂ as an interfacial layer between silicon substrate and high-k film have been studied. In this contribution we analyze the main conduction mechanism observed in SiO₂/TiO₂ MOS stack structures obtained by room temperature plasma oxidation in different conditions and reactors. Films fabricated in a parallel-plate type reactor showed better quality with low current density where thermionic conduction mechanism is predominant. In lower quality films, for example those fabricated in a barrel type equipment, the current density is higher and the conduction mechanism observed is Poole–Frenkel. Finally we show that the presence of thermionic mechanism provides a weak thickness dependence and a strong current density reduction with respect to silicon oxide MOS structures with the same equivalent oxide thickness.     

具有复合k介质埋层的高压SOI器件解析模型

An analytical model for a novel high voltage silicon-on-insulator device with composite-k(relative permittivity) dielectric buried layer(CK SOI) is proposed. In this structure, the composite-k buried layer is composed by alternating Si3N4 and low-k(k D 2.65) dielectric in the lateral direction. Due to the composite-k buried layer, the breakdown voltage(BV) is improved both by the vertical and lateral direction. Taking the modulation effect of accumulated interface holes into account, an analytical model is developed. In the blocking state, the proposed model revealed the mechanism of hole accumulation above the Si3N4 buried layer and investigated the modulation effect of accumulated holes on the two-dimensional(2-D) potential and electric field distributions. This analytical model is verified by the simulation results. Compared with the low-k dielectric buried layer SOI(LK SOI), simulation results show that the BV for CK SOI is enhanced by 21% and the specific on-resistance is reduced by 32%, respectively.     

Effects of underfill materials on the reliability of low-K flip-chip packaging

The reliability of low-K flip-chip packaging has become a critical issue owing to the low strength and poor adhesion qualities of the low-K dielectric material when compared with that of SiO₂ or fluorinated silicate glass (FSG). The underfill must protect the solder bumps and the low-K chip from cracking and delamination. However, the material properties of underfill are contrary to those required for preventing solder bumps and low-K chip from cracking and delamination. This study describes the systematic methodologies for how to specify the adequate underfill materials for low-K flip-chip packaging. The structure of the test vehicle is seven copper layers with a low-K dielectric constant value of 2.7-2.9, produced by the chemical vapor deposition (CVD) process. Initially, the adhesion and the flow test of the underfill were evaluated, and then the low-K chip and the bumps stress were determined using the finite element method. The preliminary screened underfill candidates were acquired by means of the underfill adhesion and flow test, and balancing the low-K chip and the bumps stress simulation results. Next, the low-K chips were assembled with these preliminary screened underfills. All the flip-chip packaging specimens underwent the reliability test in order to evaluate the material properties of the underfill affecting the flip-chip packaging stress. In addition, the failed samples are subjected to failure analysis to verify the failure mechanism. The results of this study indicate that, of the underfill materials investigated, those with a glass transition temperature (T_g) and a Young’s modulus of approximately 70–80 °C and 8–10 GPa, respectively, are optimum for low-K flip-chip packaging with eutectic solder bumps.     

Theoretical study of mechanical properties of multi-layer ULSI interconnect dielectrics by surface acoustic wave method

The surface acoustic waves (SAWs) technique is becoming an attractive tool for accurately and nondestructively characterizing the mechanical property of the fragile low dielectric constant (low-k) thin film used in the advanced ULSI multi-layer interconnects. The dispersion features of SAWs propagating on the layered structure of low-k/SiO₂/Si substrate and low-k/Cu/Si substrate are investigated in detail. The influence of the film thickness on the dispersion curvature is provided as an instruction for an accurate and facile fitting process. Numerical results indicate that the mechanical property of low-k films is expected to determine effectively when the broadband frequency is up to 300 MHz.     

Effects of plasma treatment on the high frequency characteristics of Cu/Ta/hydrogen silsesquioxane (HSQ) system and electrical behaviors of Cu/Ta/HSQ/Pt MIM capacitors

With the increasing of the operating frequencies, insertion loss, signal propagation delay, and parasitic coupling capacitance become the significant problems. Small capacitance (C) between interconnects is required to reduce the crosstalk, insertion loss, and RC delay associated with the metal interconnect system. Therefore, the interconnect with low dielectric constant (k) material is required. Implementation of Cu/low-k dielectric is used for reducing insertion loss, RC delay, crosstalk noises, etc. In this work, Cu-hydrogen silsesquioxane (HSQ) systems are studied. Ammonia (NH₃) plasma is employed for the nitridation of HSQ. The effects of NH₃ plasma treatments on the high frequency characteristics (100 MHz to 20 GHz) of the interconnect structure Cu/Ta/HSQ and electrical behaviors of Cu/Ta/HSQ/Pt MIM capacitors are evaluated.Auger electron spectroscopy (AES) results suggest the diffusion of oxygen and copper atoms during copper annealing. This raises resistance of Cu interconnect and increases the conductance of the HSQ films. Hence, 400 °C-annealed Cu/Ta/HSQ interconnect systems become lossy at high frequencies (>2 GHz). Ammonia (NH₃) plasma bombardments break some of the Si-H bonds and the resulting dangling Si bonds increase the moisture absorption. Meanwhile, NH₃ plasma treatments reduce the leakage current by passivating the Si dangling bond and forming silicon nitride. The absorption of moisture and/or the formation of SiN_x result in high dielectric constant of HSQ after prolonged NH₃ plasma bombardment. The dielectric constant of HSQ decreases and then increases with the increase of NH₃ plasma treatment time and a minimum dielectric constant of 2.2 is obtained after 50 s NH₃ plasma treatment at 200 W. Among various specimens in this study, the smallest insertion loss is 1.97 dB/mm at 20 GHz for the 400°C-annealed Cu/Ta/HSQ (NH₃-plasma-treated for 50 s). Appropriate NH₃-plasma bombardment helps to form a thin SiN_x barrier layer which prevents the diffusion of oxygen without increasing the dielectric constant of the Cu-HSQ interconnect system. The leakage currents versus electric field characteristics suggest that a Schottky emission dominate conduction mechanism.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

Influence of the SiO2 layer thickness on the degradation of HfO2/SiO2 stacks subjected to static and dynamic stress conditions

The substitution of the SiO₂ gate oxide in MOS devices by a material with a high-k dielectric constant is being deeply studied nowadays to solve the problem of the leakage currents that appear with the progressive scaling of SiO₂ thickness. To improve the quality of the high-k/Si interface a very thin SiO₂ film is grown between both materials. In this work, HfO₂/SiO₂ stacks with different SiO₂ thickness were subjected to different types of stress (static and dynamic) to analyze the effect of this interfacial layer of SiO₂ in the degradation of the stack. The results show that the dielectric degradation depends on the stress applied and that the thickness of the SiO₂ interfacial layer influences the advanced stages of the stack degradation.     

Intra-level voltage ramping-up to dielectric breakdown failure on Cu/porous low-k interconnections in 45 nm ULSI generation

The degradation of reliability for intra-level voltage-breakdown in the 45 nm generation node has become an increasingly important issue with the introduction of porous low-k dielectrics. The dominant failure mechanism for lower voltage ramping-up to dielectric breakdown and higher leakage current was that more electrons easily transported through the percolation path in intra-level porous low-k interconnections damaged from HF corrosion. An optimal ultraviolet curing process and a less NH₃ plasma pre-treatment on porous low-k dielectrics before the SiCN capping layer are developed to improve performance in both of these cases. The stiff configuration of the reconstruction of Si-O network structures and less HF corrosion is expected to have high tolerance to electrical failure. As a result, the proposed model of this failure facilitates the understanding of the reliability issue for Cu/porous low-k interconnections in back-end of line (BEOL) beyond 45 nm nodes.     

Thermal modeling of localized laser heating in multi-level interconnects

Thermal modeling was used to simulate thermal profiles from localized laser heating on two multi-level interconnect structures with metallization complexity comparable to those used in advanced interconnect systems. The modeling focused on addressing issues with regard to the effectiveness of laser-based techniques in defect localization in state-of-the-art metallization schemes. Modeling results indicate that indirect heating from the laser does not propagate effectively through adjacent metal layers from both the front side and the back side. Poor heat conduction and its associated thermal spreading during laser heating make defect detection difficult beyond three levels of metal. Thermal distribution and spreading were found to be more affected by interconnect geometries than by variations in laser spot size. Smaller temperature rises during laser heating were observed in the newer interconnect structures consisting of copper and low-k dielectric materials than in those with conventional aluminum, tungsten, and silicon dioxide. The smaller temperature rise leads to weaker signal strength at the defect sites and makes it more difficult to detect defects in the newer-material structures. Metallization density also affects heat conduction in advanced interconnect systems but the temperature rise during laser heating varies slowly as a function of metallization density.